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[DAGCombine] Move AND nodes to multiple load leaves Search from AND nodes to find whether they can be propagated back to loads, so that the AND and load can be combined into a narrow load. We search through OR, XOR and other AND nodes and all bar one of the leaves are required to be loads or constants. The exception node then needs to be masked off meaning that the 'and' isn't removed, but the loads(s) are narrowed still. Differential Revision: https://reviews.llvm.org/D41177 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320962 91177308-0d34-0410-b5e6-96231b3b80d8 Sam Parker 2 years ago
2 changed file(s) with 528 addition(s) and 434 deletion(s). Raw diff Collapse all Expand all
503503 /// width reduced to ExtVT.
504504 bool isLegalNarrowLoad(LoadSDNode *LoadN, ISD::LoadExtType ExtType,
505505 EVT &ExtVT, unsigned ShAmt = 0);
506
507 /// Used by BackwardsPropagateMask to find suitable loads.
508 bool SearchForAndLoads(SDNode *N, SmallPtrSetImpl &Loads,
509 SmallPtrSetImpl &NodeWithConsts,
510 ConstantSDNode *Mask, SDNode *&UncombinedNode);
511 /// Attempt to propagate a given AND node back to load leaves so that they
512 /// can be combined into narrow loads.
513 bool BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG);
506514
507515 /// Helper function for MergeConsecutiveStores which merges the
508516 /// component store chains.
37973805 return true;
37983806 }
37993807
3808 bool DAGCombiner::SearchForAndLoads(SDNode *N,
3809 SmallPtrSetImpl &Loads,
3810 SmallPtrSetImpl &NodesWithConsts,
3811 ConstantSDNode *Mask,
3812 SDNode *&NodeToMask) {
3813 // Recursively search for the operands, looking for loads which can be
3814 // narrowed.
3815 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) {
3816 SDValue Op = N->getOperand(i);
3817
3818 if (Op.getValueType().isVector())
3819 return false;
3820
3821 // Some constants may need fixing up later if they are too large.
3822 if (auto *C = dyn_cast(Op)) {
3823 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) &&
3824 (Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue())
3825 NodesWithConsts.insert(N);
3826 continue;
3827 }
3828
3829 if (!Op.hasOneUse())
3830 return false;
3831
3832 switch(Op.getOpcode()) {
3833 case ISD::LOAD: {
3834 auto *Load = cast(Op);
3835 EVT ExtVT;
3836 if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) &&
3837 isLegalNarrowLoad(Load, ISD::ZEXTLOAD, ExtVT)) {
3838 // Only add this load if we can make it more narrow.
3839 if (ExtVT.bitsLT(Load->getMemoryVT()))
3840 Loads.insert(Load);
3841 continue;
3842 }
3843 return false;
3844 }
3845 case ISD::ZERO_EXTEND:
3846 case ISD::ANY_EXTEND:
3847 case ISD::AssertZext: {
3848 unsigned ActiveBits = Mask->getAPIntValue().countTrailingOnes();
3849 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
3850 EVT VT = Op.getOpcode() == ISD::AssertZext ?
3851 cast(Op.getOperand(1))->getVT() :
3852 Op.getOperand(0).getValueType();
3853
3854 // We can accept extending nodes if the mask is wider or an equal
3855 // width to the original type.
3856 if (ExtVT.bitsGE(VT))
3857 continue;
3858 break;
3859 }
3860 case ISD::OR:
3861 case ISD::XOR:
3862 case ISD::AND:
3863 if (!SearchForAndLoads(Op.getNode(), Loads, NodesWithConsts, Mask,
3864 NodeToMask))
3865 return false;
3866 continue;
3867 }
3868
3869 // Allow one node which will masked along with any loads found.
3870 if (NodeToMask)
3871 return false;
3872 NodeToMask = Op.getNode();
3873 }
3874 return true;
3875 }
3876
3877 bool DAGCombiner::BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG) {
3878 auto *Mask = dyn_cast(N->getOperand(1));
3879 if (!Mask)
3880 return false;
3881
3882 if (!Mask->getAPIntValue().isMask())
3883 return false;
3884
3885 // No need to do anything if the and directly uses a load.
3886 if (isa(N->getOperand(0)))
3887 return false;
3888
3889 SmallPtrSet Loads;
3890 SmallPtrSet NodesWithConsts;
3891 SDNode *FixupNode = nullptr;
3892 if (SearchForAndLoads(N, Loads, NodesWithConsts, Mask, FixupNode)) {
3893 if (Loads.size() == 0)
3894 return false;
3895
3896 SDValue MaskOp = N->getOperand(1);
3897
3898 // If it exists, fixup the single node we allow in the tree that needs
3899 // masking.
3900 if (FixupNode) {
3901 SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode),
3902 FixupNode->getValueType(0),
3903 SDValue(FixupNode, 0), MaskOp);
3904 DAG.ReplaceAllUsesOfValueWith(SDValue(FixupNode, 0), And);
3905 DAG.UpdateNodeOperands(And.getNode(), SDValue(FixupNode, 0),
3906 MaskOp);
3907 }
3908
3909 // Narrow any constants that need it.
3910 for (auto *LogicN : NodesWithConsts) {
3911 auto *C = cast(LogicN->getOperand(1));
3912 SDValue And = DAG.getNode(ISD::AND, SDLoc(C), C->getValueType(0),
3913 SDValue(C, 0), MaskOp);
3914 DAG.UpdateNodeOperands(LogicN, LogicN->getOperand(0), And);
3915 }
3916
3917 // Create narrow loads.
3918 for (auto *Load : Loads) {
3919 SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0),
3920 SDValue(Load, 0), MaskOp);
3921 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And);
3922 DAG.UpdateNodeOperands(And.getNode(), SDValue(Load, 0), MaskOp);
3923 SDValue NewLoad = ReduceLoadWidth(And.getNode());
3924 assert(NewLoad &&
3925 "Shouldn't be masking the load if it can't be narrowed");
3926 CombineTo(Load, NewLoad, NewLoad.getValue(1));
3927 }
3928 DAG.ReplaceAllUsesWith(N, N->getOperand(0).getNode());
3929 return true;
3930 }
3931 return false;
3932 }
3933
38003934 SDValue DAGCombiner::visitAND(SDNode *N) {
38013935 SDValue N0 = N->getOperand(0);
38023936 SDValue N1 = N->getOperand(1);
39944128
39954129 AddToWorklist(N);
39964130 CombineTo(LN0, Res, Res.getValue(1));
4131 return SDValue(N, 0);
4132 }
4133 }
4134
4135 if (Level >= AfterLegalizeTypes) {
4136 // Attempt to propagate the AND back up to the leaves which, if they're
4137 // loads, can be combined to narrow loads and the AND node can be removed.
4138 // Perform after legalization so that extend nodes will already be
4139 // combined into the loads.
4140 if (BackwardsPropagateMask(N, DAG)) {
39974141 return SDValue(N, 0);
39984142 }
39994143 }
44 ; RUN: llc -mtriple=thumbv8m.main %s -o - | FileCheck %s --check-prefix=THUMB2
55
66 define arm_aapcscc zeroext i1 @cmp_xor8_short_short(i16* nocapture readonly %a,
7 i16* nocapture readonly %b) {
78 ; ARM-LABEL: cmp_xor8_short_short:
8 ; ARM: @ %bb.0: @ %entry
9 ; ARM-NEXT: ldrh r0, [r0]
10 ; ARM-NEXT: ldrh r1, [r1]
11 ; ARM-NEXT: eor r1, r1, r0
12 ; ARM-NEXT: mov r0, #0
13 ; ARM-NEXT: tst r1, #255
9 ; ARM: ldrb r2, [r0]
10 ; ARM-NEXT: mov r0, #0
11 ; ARM-NEXT: ldrb r1, [r1]
12 ; ARM-NEXT: teq r1, r2
1413 ; ARM-NEXT: movweq r0, #1
1514 ; ARM-NEXT: bx lr
1615 ;
1716 ; ARMEB-LABEL: cmp_xor8_short_short:
18 ; ARMEB: @ %bb.0: @ %entry
19 ; ARMEB-NEXT: ldrh r0, [r0]
20 ; ARMEB-NEXT: ldrh r1, [r1]
21 ; ARMEB-NEXT: eor r1, r1, r0
22 ; ARMEB-NEXT: mov r0, #0
23 ; ARMEB-NEXT: tst r1, #255
17 ; ARMEB: ldrb r2, [r0, #1]
18 ; ARMEB-NEXT: mov r0, #0
19 ; ARMEB-NEXT: ldrb r1, [r1, #1]
20 ; ARMEB-NEXT: teq r1, r2
2421 ; ARMEB-NEXT: movweq r0, #1
2522 ; ARMEB-NEXT: bx lr
2623 ;
2724 ; THUMB1-LABEL: cmp_xor8_short_short:
28 ; THUMB1: @ %bb.0: @ %entry
29 ; THUMB1-NEXT: ldrh r0, [r0]
30 ; THUMB1-NEXT: ldrh r2, [r1]
25 ; THUMB1: ldrb r0, [r0]
26 ; THUMB1-NEXT: ldrb r2, [r1]
3127 ; THUMB1-NEXT: eors r2, r0
3228 ; THUMB1-NEXT: movs r0, #1
3329 ; THUMB1-NEXT: movs r1, #0
34 ; THUMB1-NEXT: lsls r2, r2, #24
30 ; THUMB1-NEXT: cmp r2, #0
3531 ; THUMB1-NEXT: beq .LBB0_2
3632 ; THUMB1-NEXT: @ %bb.1: @ %entry
3733 ; THUMB1-NEXT: mov r0, r1
3935 ; THUMB1-NEXT: bx lr
4036 ;
4137 ; THUMB2-LABEL: cmp_xor8_short_short:
42 ; THUMB2: @ %bb.0: @ %entry
43 ; THUMB2-NEXT: ldrh r0, [r0]
44 ; THUMB2-NEXT: ldrh r1, [r1]
45 ; THUMB2-NEXT: eors r0, r1
46 ; THUMB2-NEXT: lsls r0, r0, #24
47 ; THUMB2-NEXT: mov.w r0, #0
48 ; THUMB2-NEXT: it eq
49 ; THUMB2-NEXT: moveq r0, #1
50 ; THUMB2-NEXT: bx lr
51 i16* nocapture readonly %b) {
38 ; THUMB2: ldrb r2, [r0]
39 ; THUMB2-NEXT: movs r0, #0
40 ; THUMB2-NEXT: ldrb r1, [r1]
41 ; THUMB2-NEXT: teq.w r1, r2
42 ; THUMB2-NEXT: it eq
43 ; THUMB2-NEXT: moveq r0, #1
44 ; THUMB2-NEXT: bx lr
5245 entry:
5346 %0 = load i16, i16* %a, align 2
5447 %1 = load i16, i16* %b, align 2
5952 }
6053
6154 define arm_aapcscc zeroext i1 @cmp_xor8_short_int(i16* nocapture readonly %a,
55 i32* nocapture readonly %b) {
6256 ; ARM-LABEL: cmp_xor8_short_int:
63 ; ARM: @ %bb.0: @ %entry
64 ; ARM-NEXT: ldrh r0, [r0]
65 ; ARM-NEXT: ldr r1, [r1]
66 ; ARM-NEXT: eor r1, r1, r0
67 ; ARM-NEXT: mov r0, #0
68 ; ARM-NEXT: tst r1, #255
57 ; ARM: ldrb r2, [r0]
58 ; ARM-NEXT: mov r0, #0
59 ; ARM-NEXT: ldrb r1, [r1]
60 ; ARM-NEXT: teq r1, r2
6961 ; ARM-NEXT: movweq r0, #1
7062 ; ARM-NEXT: bx lr
7163 ;
7264 ; ARMEB-LABEL: cmp_xor8_short_int:
73 ; ARMEB: @ %bb.0: @ %entry
74 ; ARMEB-NEXT: ldrh r0, [r0]
75 ; ARMEB-NEXT: ldr r1, [r1]
76 ; ARMEB-NEXT: eor r1, r1, r0
77 ; ARMEB-NEXT: mov r0, #0
78 ; ARMEB-NEXT: tst r1, #255
65 ; ARMEB: ldrb r2, [r0, #1]
66 ; ARMEB-NEXT: mov r0, #0
67 ; ARMEB-NEXT: ldrb r1, [r1, #3]
68 ; ARMEB-NEXT: teq r1, r2
7969 ; ARMEB-NEXT: movweq r0, #1
8070 ; ARMEB-NEXT: bx lr
8171 ;
8272 ; THUMB1-LABEL: cmp_xor8_short_int:
83 ; THUMB1: @ %bb.0: @ %entry
84 ; THUMB1-NEXT: ldrh r0, [r0]
85 ; THUMB1-NEXT: ldr r2, [r1]
73 ; THUMB1: ldrb r0, [r0]
74 ; THUMB1-NEXT: ldrb r2, [r1]
8675 ; THUMB1-NEXT: eors r2, r0
8776 ; THUMB1-NEXT: movs r0, #1
8877 ; THUMB1-NEXT: movs r1, #0
89 ; THUMB1-NEXT: lsls r2, r2, #24
78 ; THUMB1-NEXT: cmp r2, #0
9079 ; THUMB1-NEXT: beq .LBB1_2
9180 ; THUMB1-NEXT: @ %bb.1: @ %entry
9281 ; THUMB1-NEXT: mov r0, r1
9483 ; THUMB1-NEXT: bx lr
9584 ;
9685 ; THUMB2-LABEL: cmp_xor8_short_int:
97 ; THUMB2: @ %bb.0: @ %entry
98 ; THUMB2-NEXT: ldrh r0, [r0]
99 ; THUMB2-NEXT: ldr r1, [r1]
100 ; THUMB2-NEXT: eors r0, r1
101 ; THUMB2-NEXT: lsls r0, r0, #24
102 ; THUMB2-NEXT: mov.w r0, #0
103 ; THUMB2-NEXT: it eq
104 ; THUMB2-NEXT: moveq r0, #1
105 ; THUMB2-NEXT: bx lr
106 i32* nocapture readonly %b) {
86 ; THUMB2: ldrb r2, [r0]
87 ; THUMB2-NEXT: movs r0, #0
88 ; THUMB2-NEXT: ldrb r1, [r1]
89 ; THUMB2-NEXT: teq.w r1, r2
90 ; THUMB2-NEXT: it eq
91 ; THUMB2-NEXT: moveq r0, #1
92 ; THUMB2-NEXT: bx lr
10793 entry:
10894 %0 = load i16, i16* %a, align 2
10995 %conv = zext i16 %0 to i32
115101 }
116102
117103 define arm_aapcscc zeroext i1 @cmp_xor8_int_int(i32* nocapture readonly %a,
104 i32* nocapture readonly %b) {
118105 ; ARM-LABEL: cmp_xor8_int_int:
119 ; ARM: @ %bb.0: @ %entry
120 ; ARM-NEXT: ldr r0, [r0]
121 ; ARM-NEXT: ldr r1, [r1]
122 ; ARM-NEXT: eor r1, r1, r0
123 ; ARM-NEXT: mov r0, #0
124 ; ARM-NEXT: tst r1, #255
106 ; ARM: ldrb r2, [r0]
107 ; ARM-NEXT: mov r0, #0
108 ; ARM-NEXT: ldrb r1, [r1]
109 ; ARM-NEXT: teq r1, r2
125110 ; ARM-NEXT: movweq r0, #1
126111 ; ARM-NEXT: bx lr
127112 ;
128113 ; ARMEB-LABEL: cmp_xor8_int_int:
129 ; ARMEB: @ %bb.0: @ %entry
130 ; ARMEB-NEXT: ldr r0, [r0]
131 ; ARMEB-NEXT: ldr r1, [r1]
132 ; ARMEB-NEXT: eor r1, r1, r0
133 ; ARMEB-NEXT: mov r0, #0
134 ; ARMEB-NEXT: tst r1, #255
114 ; ARMEB: ldrb r2, [r0, #3]
115 ; ARMEB-NEXT: mov r0, #0
116 ; ARMEB-NEXT: ldrb r1, [r1, #3]
117 ; ARMEB-NEXT: teq r1, r2
135118 ; ARMEB-NEXT: movweq r0, #1
136119 ; ARMEB-NEXT: bx lr
137120 ;
138121 ; THUMB1-LABEL: cmp_xor8_int_int:
139 ; THUMB1: @ %bb.0: @ %entry
140 ; THUMB1-NEXT: ldr r0, [r0]
141 ; THUMB1-NEXT: ldr r2, [r1]
122 ; THUMB1: ldrb r0, [r0]
123 ; THUMB1-NEXT: ldrb r2, [r1]
142124 ; THUMB1-NEXT: eors r2, r0
143125 ; THUMB1-NEXT: movs r0, #1
144126 ; THUMB1-NEXT: movs r1, #0
145 ; THUMB1-NEXT: lsls r2, r2, #24
127 ; THUMB1-NEXT: cmp r2, #0
146128 ; THUMB1-NEXT: beq .LBB2_2
147129 ; THUMB1-NEXT: @ %bb.1: @ %entry
148130 ; THUMB1-NEXT: mov r0, r1
150132 ; THUMB1-NEXT: bx lr
151133 ;
152134 ; THUMB2-LABEL: cmp_xor8_int_int:
153 ; THUMB2: @ %bb.0: @ %entry
154 ; THUMB2-NEXT: ldr r0, [r0]
155 ; THUMB2-NEXT: ldr r1, [r1]
156 ; THUMB2-NEXT: eors r0, r1
157 ; THUMB2-NEXT: lsls r0, r0, #24
158 ; THUMB2-NEXT: mov.w r0, #0
159 ; THUMB2-NEXT: it eq
160 ; THUMB2-NEXT: moveq r0, #1
161 ; THUMB2-NEXT: bx lr
162 i32* nocapture readonly %b) {
135 ; THUMB2: ldrb r2, [r0]
136 ; THUMB2-NEXT: movs r0, #0
137 ; THUMB2-NEXT: ldrb r1, [r1]
138 ; THUMB2-NEXT: teq.w r1, r2
139 ; THUMB2-NEXT: it eq
140 ; THUMB2-NEXT: moveq r0, #1
141 ; THUMB2-NEXT: bx lr
163142 entry:
164143 %0 = load i32, i32* %a, align 4
165144 %1 = load i32, i32* %b, align 4
170149 }
171150
172151 define arm_aapcscc zeroext i1 @cmp_xor16(i32* nocapture readonly %a,
152 i32* nocapture readonly %b) {
173153 ; ARM-LABEL: cmp_xor16:
174 ; ARM: @ %bb.0: @ %entry
175 ; ARM-NEXT: ldr r0, [r0]
176 ; ARM-NEXT: movw r2, #65535
177 ; ARM-NEXT: ldr r1, [r1]
178 ; ARM-NEXT: eor r1, r1, r0
179 ; ARM-NEXT: mov r0, #0
180 ; ARM-NEXT: tst r1, r2
154 ; ARM: ldrh r2, [r0]
155 ; ARM-NEXT: mov r0, #0
156 ; ARM-NEXT: ldrh r1, [r1]
157 ; ARM-NEXT: teq r1, r2
181158 ; ARM-NEXT: movweq r0, #1
182159 ; ARM-NEXT: bx lr
183160 ;
184161 ; ARMEB-LABEL: cmp_xor16:
185 ; ARMEB: @ %bb.0: @ %entry
186 ; ARMEB-NEXT: ldr r0, [r0]
187 ; ARMEB-NEXT: movw r2, #65535
188 ; ARMEB-NEXT: ldr r1, [r1]
189 ; ARMEB-NEXT: eor r1, r1, r0
190 ; ARMEB-NEXT: mov r0, #0
191 ; ARMEB-NEXT: tst r1, r2
162 ; ARMEB: ldrh r2, [r0, #2]
163 ; ARMEB-NEXT: mov r0, #0
164 ; ARMEB-NEXT: ldrh r1, [r1, #2]
165 ; ARMEB-NEXT: teq r1, r2
192166 ; ARMEB-NEXT: movweq r0, #1
193167 ; ARMEB-NEXT: bx lr
194168 ;
195169 ; THUMB1-LABEL: cmp_xor16:
196 ; THUMB1: @ %bb.0: @ %entry
197 ; THUMB1-NEXT: ldr r0, [r0]
198 ; THUMB1-NEXT: ldr r2, [r1]
170 ; THUMB1: ldrh r0, [r0]
171 ; THUMB1-NEXT: ldrh r2, [r1]
199172 ; THUMB1-NEXT: eors r2, r0
200173 ; THUMB1-NEXT: movs r0, #1
201174 ; THUMB1-NEXT: movs r1, #0
202 ; THUMB1-NEXT: lsls r2, r2, #16
175 ; THUMB1-NEXT: cmp r2, #0
203176 ; THUMB1-NEXT: beq .LBB3_2
204177 ; THUMB1-NEXT: @ %bb.1: @ %entry
205178 ; THUMB1-NEXT: mov r0, r1
207180 ; THUMB1-NEXT: bx lr
208181 ;
209182 ; THUMB2-LABEL: cmp_xor16:
210 ; THUMB2: @ %bb.0: @ %entry
211 ; THUMB2-NEXT: ldr r0, [r0]
212 ; THUMB2-NEXT: ldr r1, [r1]
213 ; THUMB2-NEXT: eors r0, r1
214 ; THUMB2-NEXT: lsls r0, r0, #16
215 ; THUMB2-NEXT: mov.w r0, #0
216 ; THUMB2-NEXT: it eq
217 ; THUMB2-NEXT: moveq r0, #1
218 ; THUMB2-NEXT: bx lr
219 i32* nocapture readonly %b) {
183 ; THUMB2: ldrh r2, [r0]
184 ; THUMB2-NEXT: movs r0, #0
185 ; THUMB2-NEXT: ldrh r1, [r1]
186 ; THUMB2-NEXT: teq.w r1, r2
187 ; THUMB2-NEXT: it eq
188 ; THUMB2-NEXT: moveq r0, #1
189 ; THUMB2-NEXT: bx lr
220190 entry:
221191 %0 = load i32, i32* %a, align 4
222192 %1 = load i32, i32* %b, align 4
227197 }
228198
229199 define arm_aapcscc zeroext i1 @cmp_or8_short_short(i16* nocapture readonly %a,
200 i16* nocapture readonly %b) {
230201 ; ARM-LABEL: cmp_or8_short_short:
231 ; ARM: @ %bb.0: @ %entry
232 ; ARM-NEXT: ldrh r0, [r0]
233 ; ARM-NEXT: ldrh r1, [r1]
234 ; ARM-NEXT: orr r1, r1, r0
235 ; ARM-NEXT: mov r0, #0
236 ; ARM-NEXT: tst r1, #255
202 ; ARM: ldrb r0, [r0]
203 ; ARM-NEXT: ldrb r1, [r1]
204 ; ARM-NEXT: orrs r0, r1, r0
205 ; ARM-NEXT: mov r0, #0
237206 ; ARM-NEXT: movweq r0, #1
238207 ; ARM-NEXT: bx lr
239208 ;
240209 ; ARMEB-LABEL: cmp_or8_short_short:
241 ; ARMEB: @ %bb.0: @ %entry
242 ; ARMEB-NEXT: ldrh r0, [r0]
243 ; ARMEB-NEXT: ldrh r1, [r1]
244 ; ARMEB-NEXT: orr r1, r1, r0
245 ; ARMEB-NEXT: mov r0, #0
246 ; ARMEB-NEXT: tst r1, #255
210 ; ARMEB: ldrb r0, [r0, #1]
211 ; ARMEB-NEXT: ldrb r1, [r1, #1]
212 ; ARMEB-NEXT: orrs r0, r1, r0
213 ; ARMEB-NEXT: mov r0, #0
247214 ; ARMEB-NEXT: movweq r0, #1
248215 ; ARMEB-NEXT: bx lr
249216 ;
250217 ; THUMB1-LABEL: cmp_or8_short_short:
251 ; THUMB1: @ %bb.0: @ %entry
252 ; THUMB1-NEXT: ldrh r0, [r0]
253 ; THUMB1-NEXT: ldrh r2, [r1]
218 ; THUMB1: ldrb r0, [r0]
219 ; THUMB1-NEXT: ldrb r2, [r1]
254220 ; THUMB1-NEXT: orrs r2, r0
255221 ; THUMB1-NEXT: movs r0, #1
256222 ; THUMB1-NEXT: movs r1, #0
257 ; THUMB1-NEXT: lsls r2, r2, #24
223 ; THUMB1-NEXT: cmp r2, #0
258224 ; THUMB1-NEXT: beq .LBB4_2
259225 ; THUMB1-NEXT: @ %bb.1: @ %entry
260226 ; THUMB1-NEXT: mov r0, r1
262228 ; THUMB1-NEXT: bx lr
263229 ;
264230 ; THUMB2-LABEL: cmp_or8_short_short:
265 ; THUMB2: @ %bb.0: @ %entry
266 ; THUMB2-NEXT: ldrh r0, [r0]
267 ; THUMB2-NEXT: ldrh r1, [r1]
231 ; THUMB2: ldrb r0, [r0]
232 ; THUMB2-NEXT: ldrb r1, [r1]
268233 ; THUMB2-NEXT: orrs r0, r1
269 ; THUMB2-NEXT: lsls r0, r0, #24
270234 ; THUMB2-NEXT: mov.w r0, #0
271235 ; THUMB2-NEXT: it eq
272236 ; THUMB2-NEXT: moveq r0, #1
273237 ; THUMB2-NEXT: bx lr
274 i16* nocapture readonly %b) {
275238 entry:
276239 %0 = load i16, i16* %a, align 2
277240 %1 = load i16, i16* %b, align 2
282245 }
283246
284247 define arm_aapcscc zeroext i1 @cmp_or8_short_int(i16* nocapture readonly %a,
248 i32* nocapture readonly %b) {
285249 ; ARM-LABEL: cmp_or8_short_int:
286 ; ARM: @ %bb.0: @ %entry
287 ; ARM-NEXT: ldrh r0, [r0]
288 ; ARM-NEXT: ldr r1, [r1]
289 ; ARM-NEXT: orr r1, r1, r0
290 ; ARM-NEXT: mov r0, #0
291 ; ARM-NEXT: tst r1, #255
250 ; ARM: ldrb r0, [r0]
251 ; ARM-NEXT: ldrb r1, [r1]
252 ; ARM-NEXT: orrs r0, r1, r0
253 ; ARM-NEXT: mov r0, #0
292254 ; ARM-NEXT: movweq r0, #1
293255 ; ARM-NEXT: bx lr
294256 ;
295257 ; ARMEB-LABEL: cmp_or8_short_int:
296 ; ARMEB: @ %bb.0: @ %entry
297 ; ARMEB-NEXT: ldrh r0, [r0]
298 ; ARMEB-NEXT: ldr r1, [r1]
299 ; ARMEB-NEXT: orr r1, r1, r0
300 ; ARMEB-NEXT: mov r0, #0
301 ; ARMEB-NEXT: tst r1, #255
258 ; ARMEB: ldrb r0, [r0, #1]
259 ; ARMEB-NEXT: ldrb r1, [r1, #3]
260 ; ARMEB-NEXT: orrs r0, r1, r0
261 ; ARMEB-NEXT: mov r0, #0
302262 ; ARMEB-NEXT: movweq r0, #1
303263 ; ARMEB-NEXT: bx lr
304264 ;
305265 ; THUMB1-LABEL: cmp_or8_short_int:
306 ; THUMB1: @ %bb.0: @ %entry
307 ; THUMB1-NEXT: ldrh r0, [r0]
308 ; THUMB1-NEXT: ldr r2, [r1]
266 ; THUMB1: ldrb r0, [r0]
267 ; THUMB1-NEXT: ldrb r2, [r1]
309268 ; THUMB1-NEXT: orrs r2, r0
310269 ; THUMB1-NEXT: movs r0, #1
311270 ; THUMB1-NEXT: movs r1, #0
312 ; THUMB1-NEXT: lsls r2, r2, #24
271 ; THUMB1-NEXT: cmp r2, #0
313272 ; THUMB1-NEXT: beq .LBB5_2
314273 ; THUMB1-NEXT: @ %bb.1: @ %entry
315274 ; THUMB1-NEXT: mov r0, r1
317276 ; THUMB1-NEXT: bx lr
318277 ;
319278 ; THUMB2-LABEL: cmp_or8_short_int:
320 ; THUMB2: @ %bb.0: @ %entry
321 ; THUMB2-NEXT: ldrh r0, [r0]
322 ; THUMB2-NEXT: ldr r1, [r1]
279 ; THUMB2: ldrb r0, [r0]
280 ; THUMB2-NEXT: ldrb r1, [r1]
323281 ; THUMB2-NEXT: orrs r0, r1
324 ; THUMB2-NEXT: lsls r0, r0, #24
325282 ; THUMB2-NEXT: mov.w r0, #0
326283 ; THUMB2-NEXT: it eq
327284 ; THUMB2-NEXT: moveq r0, #1
328285 ; THUMB2-NEXT: bx lr
329 i32* nocapture readonly %b) {
330286 entry:
331287 %0 = load i16, i16* %a, align 2
332288 %conv = zext i16 %0 to i32
338294 }
339295
340296 define arm_aapcscc zeroext i1 @cmp_or8_int_int(i32* nocapture readonly %a,
297 i32* nocapture readonly %b) {
341298 ; ARM-LABEL: cmp_or8_int_int:
342 ; ARM: @ %bb.0: @ %entry
343 ; ARM-NEXT: ldr r0, [r0]
344 ; ARM-NEXT: ldr r1, [r1]
345 ; ARM-NEXT: orr r1, r1, r0
346 ; ARM-NEXT: mov r0, #0
347 ; ARM-NEXT: tst r1, #255
299 ; ARM: ldrb r0, [r0]
300 ; ARM-NEXT: ldrb r1, [r1]
301 ; ARM-NEXT: orrs r0, r1, r0
302 ; ARM-NEXT: mov r0, #0
348303 ; ARM-NEXT: movweq r0, #1
349304 ; ARM-NEXT: bx lr
350305 ;
351306 ; ARMEB-LABEL: cmp_or8_int_int:
352 ; ARMEB: @ %bb.0: @ %entry
353 ; ARMEB-NEXT: ldr r0, [r0]
354 ; ARMEB-NEXT: ldr r1, [r1]
355 ; ARMEB-NEXT: orr r1, r1, r0
356 ; ARMEB-NEXT: mov r0, #0
357 ; ARMEB-NEXT: tst r1, #255
307 ; ARMEB: ldrb r0, [r0, #3]
308 ; ARMEB-NEXT: ldrb r1, [r1, #3]
309 ; ARMEB-NEXT: orrs r0, r1, r0
310 ; ARMEB-NEXT: mov r0, #0
358311 ; ARMEB-NEXT: movweq r0, #1
359312 ; ARMEB-NEXT: bx lr
360313 ;
361314 ; THUMB1-LABEL: cmp_or8_int_int:
362 ; THUMB1: @ %bb.0: @ %entry
363 ; THUMB1-NEXT: ldr r0, [r0]
364 ; THUMB1-NEXT: ldr r2, [r1]
315 ; THUMB1: ldrb r0, [r0]
316 ; THUMB1-NEXT: ldrb r2, [r1]
365317 ; THUMB1-NEXT: orrs r2, r0
366318 ; THUMB1-NEXT: movs r0, #1
367319 ; THUMB1-NEXT: movs r1, #0
368 ; THUMB1-NEXT: lsls r2, r2, #24
320 ; THUMB1-NEXT: cmp r2, #0
369321 ; THUMB1-NEXT: beq .LBB6_2
370322 ; THUMB1-NEXT: @ %bb.1: @ %entry
371323 ; THUMB1-NEXT: mov r0, r1
373325 ; THUMB1-NEXT: bx lr
374326 ;
375327 ; THUMB2-LABEL: cmp_or8_int_int:
376 ; THUMB2: @ %bb.0: @ %entry
377 ; THUMB2-NEXT: ldr r0, [r0]
378 ; THUMB2-NEXT: ldr r1, [r1]
328 ; THUMB2: ldrb r0, [r0]
329 ; THUMB2-NEXT: ldrb r1, [r1]
379330 ; THUMB2-NEXT: orrs r0, r1
380 ; THUMB2-NEXT: lsls r0, r0, #24
381331 ; THUMB2-NEXT: mov.w r0, #0
382332 ; THUMB2-NEXT: it eq
383333 ; THUMB2-NEXT: moveq r0, #1
384334 ; THUMB2-NEXT: bx lr
385 i32* nocapture readonly %b) {
386335 entry:
387336 %0 = load i32, i32* %a, align 4
388337 %1 = load i32, i32* %b, align 4
393342 }
394343
395344 define arm_aapcscc zeroext i1 @cmp_or16(i32* nocapture readonly %a,
345 i32* nocapture readonly %b) {
396346 ; ARM-LABEL: cmp_or16:
397 ; ARM: @ %bb.0: @ %entry
398 ; ARM-NEXT: ldr r0, [r0]
399 ; ARM-NEXT: movw r2, #65535
400 ; ARM-NEXT: ldr r1, [r1]
401 ; ARM-NEXT: orr r1, r1, r0
402 ; ARM-NEXT: mov r0, #0
403 ; ARM-NEXT: tst r1, r2
347 ; ARM: ldrh r0, [r0]
348 ; ARM-NEXT: ldrh r1, [r1]
349 ; ARM-NEXT: orrs r0, r1, r0
350 ; ARM-NEXT: mov r0, #0
404351 ; ARM-NEXT: movweq r0, #1
405352 ; ARM-NEXT: bx lr
406353 ;
407354 ; ARMEB-LABEL: cmp_or16:
408 ; ARMEB: @ %bb.0: @ %entry
409 ; ARMEB-NEXT: ldr r0, [r0]
410 ; ARMEB-NEXT: movw r2, #65535
411 ; ARMEB-NEXT: ldr r1, [r1]
412 ; ARMEB-NEXT: orr r1, r1, r0
413 ; ARMEB-NEXT: mov r0, #0
414 ; ARMEB-NEXT: tst r1, r2
355 ; ARMEB: ldrh r0, [r0, #2]
356 ; ARMEB-NEXT: ldrh r1, [r1, #2]
357 ; ARMEB-NEXT: orrs r0, r1, r0
358 ; ARMEB-NEXT: mov r0, #0
415359 ; ARMEB-NEXT: movweq r0, #1
416360 ; ARMEB-NEXT: bx lr
417361 ;
418362 ; THUMB1-LABEL: cmp_or16:
419 ; THUMB1: @ %bb.0: @ %entry
420 ; THUMB1-NEXT: ldr r0, [r0]
421 ; THUMB1-NEXT: ldr r2, [r1]
363 ; THUMB1: ldrh r0, [r0]
364 ; THUMB1-NEXT: ldrh r2, [r1]
422365 ; THUMB1-NEXT: orrs r2, r0
423366 ; THUMB1-NEXT: movs r0, #1
424367 ; THUMB1-NEXT: movs r1, #0
425 ; THUMB1-NEXT: lsls r2, r2, #16
368 ; THUMB1-NEXT: cmp r2, #0
426369 ; THUMB1-NEXT: beq .LBB7_2
427370 ; THUMB1-NEXT: @ %bb.1: @ %entry
428371 ; THUMB1-NEXT: mov r0, r1
430373 ; THUMB1-NEXT: bx lr
431374 ;
432375 ; THUMB2-LABEL: cmp_or16:
433 ; THUMB2: @ %bb.0: @ %entry
434 ; THUMB2-NEXT: ldr r0, [r0]
435 ; THUMB2-NEXT: ldr r1, [r1]
376 ; THUMB2: ldrh r0, [r0]
377 ; THUMB2-NEXT: ldrh r1, [r1]
436378 ; THUMB2-NEXT: orrs r0, r1
437 ; THUMB2-NEXT: lsls r0, r0, #16
438379 ; THUMB2-NEXT: mov.w r0, #0
439380 ; THUMB2-NEXT: it eq
440381 ; THUMB2-NEXT: moveq r0, #1
441382 ; THUMB2-NEXT: bx lr
442 i32* nocapture readonly %b) {
443383 entry:
444384 %0 = load i32, i32* %a, align 4
445385 %1 = load i32, i32* %b, align 4
450390 }
451391
452392 define arm_aapcscc zeroext i1 @cmp_and8_short_short(i16* nocapture readonly %a,
393 i16* nocapture readonly %b) {
453394 ; ARM-LABEL: cmp_and8_short_short:
454 ; ARM: @ %bb.0: @ %entry
455 ; ARM-NEXT: ldrh r1, [r1]
456 ; ARM-NEXT: ldrh r0, [r0]
457 ; ARM-NEXT: and r1, r0, r1
458 ; ARM-NEXT: mov r0, #0
459 ; ARM-NEXT: tst r1, #255
395 ; ARM: ldrb r2, [r0]
396 ; ARM-NEXT: mov r0, #0
397 ; ARM-NEXT: ldrb r1, [r1]
398 ; ARM-NEXT: tst r2, r1
460399 ; ARM-NEXT: movweq r0, #1
461400 ; ARM-NEXT: bx lr
462401 ;
463402 ; ARMEB-LABEL: cmp_and8_short_short:
464 ; ARMEB: @ %bb.0: @ %entry
465 ; ARMEB-NEXT: ldrh r1, [r1]
466 ; ARMEB-NEXT: ldrh r0, [r0]
467 ; ARMEB-NEXT: and r1, r0, r1
468 ; ARMEB-NEXT: mov r0, #0
469 ; ARMEB-NEXT: tst r1, #255
403 ; ARMEB: ldrb r2, [r0, #1]
404 ; ARMEB-NEXT: mov r0, #0
405 ; ARMEB-NEXT: ldrb r1, [r1, #1]
406 ; ARMEB-NEXT: tst r2, r1
470407 ; ARMEB-NEXT: movweq r0, #1
471408 ; ARMEB-NEXT: bx lr
472409 ;
473410 ; THUMB1-LABEL: cmp_and8_short_short:
474 ; THUMB1: @ %bb.0: @ %entry
475 ; THUMB1-NEXT: ldrh r1, [r1]
476 ; THUMB1-NEXT: ldrh r2, [r0]
477 ; THUMB1-NEXT: ands r2, r1
478 ; THUMB1-NEXT: movs r0, #1
479 ; THUMB1-NEXT: movs r1, #0
480 ; THUMB1-NEXT: lsls r2, r2, #24
411 ; THUMB1: ldrb r2, [r1]
412 ; THUMB1-NEXT: ldrb r3, [r0]
413 ; THUMB1-NEXT: movs r0, #1
414 ; THUMB1-NEXT: movs r1, #0
415 ; THUMB1-NEXT: tst r3, r2
481416 ; THUMB1-NEXT: beq .LBB8_2
482417 ; THUMB1-NEXT: @ %bb.1: @ %entry
483418 ; THUMB1-NEXT: mov r0, r1
485420 ; THUMB1-NEXT: bx lr
486421 ;
487422 ; THUMB2-LABEL: cmp_and8_short_short:
488 ; THUMB2: @ %bb.0: @ %entry
489 ; THUMB2-NEXT: ldrh r1, [r1]
490 ; THUMB2-NEXT: ldrh r0, [r0]
491 ; THUMB2-NEXT: ands r0, r1
492 ; THUMB2-NEXT: lsls r0, r0, #24
493 ; THUMB2-NEXT: mov.w r0, #0
494 ; THUMB2-NEXT: it eq
495 ; THUMB2-NEXT: moveq r0, #1
496 ; THUMB2-NEXT: bx lr
497 i16* nocapture readonly %b) {
423 ; THUMB2: ldrb r2, [r0]
424 ; THUMB2-NEXT: movs r0, #0
425 ; THUMB2-NEXT: ldrb r1, [r1]
426 ; THUMB2-NEXT: tst r2, r1
427 ; THUMB2-NEXT: it eq
428 ; THUMB2-NEXT: moveq r0, #1
429 ; THUMB2-NEXT: bx lr
498430 entry:
499431 %0 = load i16, i16* %a, align 2
500432 %1 = load i16, i16* %b, align 2
505437 }
506438
507439 define arm_aapcscc zeroext i1 @cmp_and8_short_int(i16* nocapture readonly %a,
440 i32* nocapture readonly %b) {
508441 ; ARM-LABEL: cmp_and8_short_int:
509 ; ARM: @ %bb.0: @ %entry
510 ; ARM-NEXT: ldrh r0, [r0]
511 ; ARM-NEXT: ldr r1, [r1]
512 ; ARM-NEXT: and r1, r1, r0
513 ; ARM-NEXT: mov r0, #0
514 ; ARM-NEXT: tst r1, #255
442 ; ARM: ldrb r2, [r0]
443 ; ARM-NEXT: mov r0, #0
444 ; ARM-NEXT: ldrb r1, [r1]
445 ; ARM-NEXT: tst r1, r2
515446 ; ARM-NEXT: movweq r0, #1
516447 ; ARM-NEXT: bx lr
517448 ;
518449 ; ARMEB-LABEL: cmp_and8_short_int:
519 ; ARMEB: @ %bb.0: @ %entry
520 ; ARMEB-NEXT: ldrh r0, [r0]
521 ; ARMEB-NEXT: ldr r1, [r1]
522 ; ARMEB-NEXT: and r1, r1, r0
523 ; ARMEB-NEXT: mov r0, #0
524 ; ARMEB-NEXT: tst r1, #255
450 ; ARMEB: ldrb r2, [r0, #1]
451 ; ARMEB-NEXT: mov r0, #0
452 ; ARMEB-NEXT: ldrb r1, [r1, #3]
453 ; ARMEB-NEXT: tst r1, r2
525454 ; ARMEB-NEXT: movweq r0, #1
526455 ; ARMEB-NEXT: bx lr
527456 ;
528457 ; THUMB1-LABEL: cmp_and8_short_int:
529 ; THUMB1: @ %bb.0: @ %entry
530 ; THUMB1-NEXT: ldrh r0, [r0]
531 ; THUMB1-NEXT: ldr r2, [r1]
532 ; THUMB1-NEXT: ands r2, r0
533 ; THUMB1-NEXT: movs r0, #1
534 ; THUMB1-NEXT: movs r1, #0
535 ; THUMB1-NEXT: lsls r2, r2, #24
458 ; THUMB1: ldrb r2, [r0]
459 ; THUMB1-NEXT: ldrb r3, [r1]
460 ; THUMB1-NEXT: movs r0, #1
461 ; THUMB1-NEXT: movs r1, #0
462 ; THUMB1-NEXT: tst r3, r2
536463 ; THUMB1-NEXT: beq .LBB9_2
537464 ; THUMB1-NEXT: @ %bb.1: @ %entry
538465 ; THUMB1-NEXT: mov r0, r1
540467 ; THUMB1-NEXT: bx lr
541468 ;
542469 ; THUMB2-LABEL: cmp_and8_short_int:
543 ; THUMB2: @ %bb.0: @ %entry
544 ; THUMB2-NEXT: ldrh r0, [r0]
545 ; THUMB2-NEXT: ldr r1, [r1]
546 ; THUMB2-NEXT: ands r0, r1
547 ; THUMB2-NEXT: lsls r0, r0, #24
548 ; THUMB2-NEXT: mov.w r0, #0
549 ; THUMB2-NEXT: it eq
550 ; THUMB2-NEXT: moveq r0, #1
551 ; THUMB2-NEXT: bx lr
552 i32* nocapture readonly %b) {
470 ; THUMB2: ldrb r2, [r0]
471 ; THUMB2-NEXT: movs r0, #0
472 ; THUMB2-NEXT: ldrb r1, [r1]
473 ; THUMB2-NEXT: tst r1, r2
474 ; THUMB2-NEXT: it eq
475 ; THUMB2-NEXT: moveq r0, #1
476 ; THUMB2-NEXT: bx lr
553477 entry:
554478 %0 = load i16, i16* %a, align 2
555479 %1 = load i32, i32* %b, align 4
561485 }
562486
563487 define arm_aapcscc zeroext i1 @cmp_and8_int_int(i32* nocapture readonly %a,
488 i32* nocapture readonly %b) {
564489 ; ARM-LABEL: cmp_and8_int_int:
565 ; ARM: @ %bb.0: @ %entry
566 ; ARM-NEXT: ldr r1, [r1]
567 ; ARM-NEXT: ldr r0, [r0]
568 ; ARM-NEXT: and r1, r0, r1
569 ; ARM-NEXT: mov r0, #0
570 ; ARM-NEXT: tst r1, #255
490 ; ARM: ldrb r2, [r0]
491 ; ARM-NEXT: mov r0, #0
492 ; ARM-NEXT: ldrb r1, [r1]
493 ; ARM-NEXT: tst r2, r1
571494 ; ARM-NEXT: movweq r0, #1
572495 ; ARM-NEXT: bx lr
573496 ;
574497 ; ARMEB-LABEL: cmp_and8_int_int:
575 ; ARMEB: @ %bb.0: @ %entry
576 ; ARMEB-NEXT: ldr r1, [r1]
577 ; ARMEB-NEXT: ldr r0, [r0]
578 ; ARMEB-NEXT: and r1, r0, r1
579 ; ARMEB-NEXT: mov r0, #0
580 ; ARMEB-NEXT: tst r1, #255
498 ; ARMEB: ldrb r2, [r0, #3]
499 ; ARMEB-NEXT: mov r0, #0
500 ; ARMEB-NEXT: ldrb r1, [r1, #3]
501 ; ARMEB-NEXT: tst r2, r1
581502 ; ARMEB-NEXT: movweq r0, #1
582503 ; ARMEB-NEXT: bx lr
583504 ;
584505 ; THUMB1-LABEL: cmp_and8_int_int:
585 ; THUMB1: @ %bb.0: @ %entry
586 ; THUMB1-NEXT: ldr r1, [r1]
587 ; THUMB1-NEXT: ldr r2, [r0]
588 ; THUMB1-NEXT: ands r2, r1
589 ; THUMB1-NEXT: movs r0, #1
590 ; THUMB1-NEXT: movs r1, #0
591 ; THUMB1-NEXT: lsls r2, r2, #24
506 ; THUMB1: ldrb r2, [r1]
507 ; THUMB1-NEXT: ldrb r3, [r0]
508 ; THUMB1-NEXT: movs r0, #1
509 ; THUMB1-NEXT: movs r1, #0
510 ; THUMB1-NEXT: tst r3, r2
592511 ; THUMB1-NEXT: beq .LBB10_2
593512 ; THUMB1-NEXT: @ %bb.1: @ %entry
594513 ; THUMB1-NEXT: mov r0, r1
596515 ; THUMB1-NEXT: bx lr
597516 ;
598517 ; THUMB2-LABEL: cmp_and8_int_int:
599 ; THUMB2: @ %bb.0: @ %entry
600 ; THUMB2-NEXT: ldr r1, [r1]
601 ; THUMB2-NEXT: ldr r0, [r0]
602 ; THUMB2-NEXT: ands r0, r1
603 ; THUMB2-NEXT: lsls r0, r0, #24
604 ; THUMB2-NEXT: mov.w r0, #0
605 ; THUMB2-NEXT: it eq
606 ; THUMB2-NEXT: moveq r0, #1
607 ; THUMB2-NEXT: bx lr
608 i32* nocapture readonly %b) {
518 ; THUMB2: ldrb r2, [r0]
519 ; THUMB2-NEXT: movs r0, #0
520 ; THUMB2-NEXT: ldrb r1, [r1]
521 ; THUMB2-NEXT: tst r2, r1
522 ; THUMB2-NEXT: it eq
523 ; THUMB2-NEXT: moveq r0, #1
524 ; THUMB2-NEXT: bx lr
609525 entry:
610526 %0 = load i32, i32* %a, align 4
611527 %1 = load i32, i32* %b, align 4
616532 }
617533
618534 define arm_aapcscc zeroext i1 @cmp_and16(i32* nocapture readonly %a,
535 i32* nocapture readonly %b) {
619536 ; ARM-LABEL: cmp_and16:
620 ; ARM: @ %bb.0: @ %entry
621 ; ARM-NEXT: ldr r1, [r1]
622 ; ARM-NEXT: movw r2, #65535
623 ; ARM-NEXT: ldr r0, [r0]
624 ; ARM-NEXT: and r1, r0, r1
625 ; ARM-NEXT: mov r0, #0
626 ; ARM-NEXT: tst r1, r2
537 ; ARM: ldrh r2, [r0]
538 ; ARM-NEXT: mov r0, #0
539 ; ARM-NEXT: ldrh r1, [r1]
540 ; ARM-NEXT: tst r2, r1
627541 ; ARM-NEXT: movweq r0, #1
628542 ; ARM-NEXT: bx lr
629543 ;
630544 ; ARMEB-LABEL: cmp_and16:
631 ; ARMEB: @ %bb.0: @ %entry
632 ; ARMEB-NEXT: ldr r1, [r1]
633 ; ARMEB-NEXT: movw r2, #65535
634 ; ARMEB-NEXT: ldr r0, [r0]
635 ; ARMEB-NEXT: and r1, r0, r1
636 ; ARMEB-NEXT: mov r0, #0
637 ; ARMEB-NEXT: tst r1, r2
545 ; ARMEB: ldrh r2, [r0, #2]
546 ; ARMEB-NEXT: mov r0, #0
547 ; ARMEB-NEXT: ldrh r1, [r1, #2]
548 ; ARMEB-NEXT: tst r2, r1
638549 ; ARMEB-NEXT: movweq r0, #1
639550 ; ARMEB-NEXT: bx lr
640551 ;
641552 ; THUMB1-LABEL: cmp_and16:
642 ; THUMB1: @ %bb.0: @ %entry
643 ; THUMB1-NEXT: ldr r1, [r1]
644 ; THUMB1-NEXT: ldr r2, [r0]
645 ; THUMB1-NEXT: ands r2, r1
646 ; THUMB1-NEXT: movs r0, #1
647 ; THUMB1-NEXT: movs r1, #0
648 ; THUMB1-NEXT: lsls r2, r2, #16
553 ; THUMB1: ldrh r2, [r1]
554 ; THUMB1-NEXT: ldrh r3, [r0]
555 ; THUMB1-NEXT: movs r0, #1
556 ; THUMB1-NEXT: movs r1, #0
557 ; THUMB1-NEXT: tst r3, r2
649558 ; THUMB1-NEXT: beq .LBB11_2
650559 ; THUMB1-NEXT: @ %bb.1: @ %entry
651560 ; THUMB1-NEXT: mov r0, r1
653562 ; THUMB1-NEXT: bx lr
654563 ;
655564 ; THUMB2-LABEL: cmp_and16:
656 ; THUMB2: @ %bb.0: @ %entry
657 ; THUMB2-NEXT: ldr r1, [r1]
658 ; THUMB2-NEXT: ldr r0, [r0]
659 ; THUMB2-NEXT: ands r0, r1
660 ; THUMB2-NEXT: lsls r0, r0, #16
661 ; THUMB2-NEXT: mov.w r0, #0
662 ; THUMB2-NEXT: it eq
663 ; THUMB2-NEXT: moveq r0, #1
664 ; THUMB2-NEXT: bx lr
665 i32* nocapture readonly %b) {
565 ; THUMB2: ldrh r2, [r0]
566 ; THUMB2-NEXT: movs r0, #0
567 ; THUMB2-NEXT: ldrh r1, [r1]
568 ; THUMB2-NEXT: tst r2, r1
569 ; THUMB2-NEXT: it eq
570 ; THUMB2-NEXT: moveq r0, #1
571 ; THUMB2-NEXT: bx lr
666572 entry:
667573 %0 = load i32, i32* %a, align 4
668574 %1 = load i32, i32* %b, align 4
674580
675581 define arm_aapcscc i32 @add_and16(i32* nocapture readonly %a, i32 %y, i32 %z) {
676582 ; ARM-LABEL: add_and16:
677 ; ARM: @ %bb.0: @ %entry
678 ; ARM-NEXT: ldr r0, [r0]
679 ; ARM-NEXT: add r1, r1, r2
583 ; ARM: add r1, r1, r2
584 ; ARM-NEXT: ldrh r0, [r0]
585 ; ARM-NEXT: uxth r1, r1
680586 ; ARM-NEXT: orr r0, r0, r1
681 ; ARM-NEXT: uxth r0, r0
682587 ; ARM-NEXT: bx lr
683588 ;
684589 ; ARMEB-LABEL: add_and16:
685 ; ARMEB: @ %bb.0: @ %entry
686 ; ARMEB-NEXT: ldr r0, [r0]
687 ; ARMEB-NEXT: add r1, r1, r2
590 ; ARMEB: add r1, r1, r2
591 ; ARMEB-NEXT: ldrh r0, [r0, #2]
592 ; ARMEB-NEXT: uxth r1, r1
688593 ; ARMEB-NEXT: orr r0, r0, r1
689 ; ARMEB-NEXT: uxth r0, r0
690594 ; ARMEB-NEXT: bx lr
691595 ;
692596 ; THUMB1-LABEL: add_and16:
693 ; THUMB1: @ %bb.0: @ %entry
694 ; THUMB1-NEXT: adds r1, r1, r2
695 ; THUMB1-NEXT: ldr r0, [r0]
597 ; THUMB1: adds r1, r1, r2
598 ; THUMB1-NEXT: uxth r1, r1
599 ; THUMB1-NEXT: ldrh r0, [r0]
696600 ; THUMB1-NEXT: orrs r0, r1
697 ; THUMB1-NEXT: uxth r0, r0
698601 ; THUMB1-NEXT: bx lr
699602 ;
700603 ; THUMB2-LABEL: add_and16:
701 ; THUMB2: @ %bb.0: @ %entry
702 ; THUMB2-NEXT: ldr r0, [r0]
703 ; THUMB2-NEXT: add r1, r2
604 ; THUMB2: add r1, r2
605 ; THUMB2-NEXT: ldrh r0, [r0]
606 ; THUMB2-NEXT: uxth r1, r1
704607 ; THUMB2-NEXT: orrs r0, r1
705 ; THUMB2-NEXT: uxth r0, r0
706608 ; THUMB2-NEXT: bx lr
707609 entry:
708610 %x = load i32, i32* %a, align 4
714616
715617 define arm_aapcscc i32 @test1(i32* %a, i32* %b, i32 %x, i32 %y) {
716618 ; ARM-LABEL: test1:
717 ; ARM: @ %bb.0: @ %entry
718 ; ARM-NEXT: mul r2, r2, r3
719 ; ARM-NEXT: ldr r1, [r1]
720 ; ARM-NEXT: ldr r0, [r0]
619 ; ARM: mul r2, r2, r3
620 ; ARM-NEXT: ldrh r1, [r1]
621 ; ARM-NEXT: ldrh r0, [r0]
721622 ; ARM-NEXT: eor r0, r0, r1
722 ; ARM-NEXT: orr r0, r0, r2
723 ; ARM-NEXT: uxth r0, r0
623 ; ARM-NEXT: uxth r1, r2
624 ; ARM-NEXT: orr r0, r0, r1
724625 ; ARM-NEXT: bx lr
725626 ;
726627 ; ARMEB-LABEL: test1:
727 ; ARMEB: @ %bb.0: @ %entry
728 ; ARMEB-NEXT: mul r2, r2, r3
729 ; ARMEB-NEXT: ldr r1, [r1]
730 ; ARMEB-NEXT: ldr r0, [r0]
628 ; ARMEB: mul r2, r2, r3
629 ; ARMEB-NEXT: ldrh r1, [r1, #2]
630 ; ARMEB-NEXT: ldrh r0, [r0, #2]
731631 ; ARMEB-NEXT: eor r0, r0, r1
732 ; ARMEB-NEXT: orr r0, r0, r2
733 ; ARMEB-NEXT: uxth r0, r0
632 ; ARMEB-NEXT: uxth r1, r2
633 ; ARMEB-NEXT: orr r0, r0, r1
734634 ; ARMEB-NEXT: bx lr
735635 ;
736636 ; THUMB1-LABEL: test1:
737 ; THUMB1: @ %bb.0: @ %entry
637 ; THUMB1: ldrh r1, [r1]
638 ; THUMB1-NEXT: ldrh r4, [r0]
639 ; THUMB1-NEXT: eors r4, r1
738640 ; THUMB1-NEXT: muls r2, r3, r2
739 ; THUMB1-NEXT: ldr r1, [r1]
740 ; THUMB1-NEXT: ldr r0, [r0]
741 ; THUMB1-NEXT: eors r0, r1
742 ; THUMB1-NEXT: orrs r0, r2
743 ; THUMB1-NEXT: uxth r0, r0
744 ; THUMB1-NEXT: bx lr
641 ; THUMB1-NEXT: uxth r0, r2
642 ; THUMB1-NEXT: orrs r0, r4
643 ; THUMB1-NEXT: pop
745644 ;
746645 ; THUMB2-LABEL: test1:
747 ; THUMB2: @ %bb.0: @ %entry
748 ; THUMB2-NEXT: muls r2, r3, r2
749 ; THUMB2-NEXT: ldr r1, [r1]
750 ; THUMB2-NEXT: ldr r0, [r0]
646 ; THUMB2: ldrh r1, [r1]
647 ; THUMB2-NEXT: ldrh r0, [r0]
751648 ; THUMB2-NEXT: eors r0, r1
752 ; THUMB2-NEXT: orrs r0, r2
753 ; THUMB2-NEXT: uxth r0, r0
649 ; THUMB2-NEXT: mul r1, r2, r3
650 ; THUMB2-NEXT: uxth r1, r1
651 ; THUMB2-NEXT: orrs r0, r1
754652 ; THUMB2-NEXT: bx lr
755653 entry:
756654 %0 = load i32, i32* %a, align 4
764662
765663 define arm_aapcscc i32 @test2(i32* %a, i32* %b, i32 %x, i32 %y) {
766664 ; ARM-LABEL: test2:
767 ; ARM: @ %bb.0: @ %entry
768 ; ARM-NEXT: ldr r1, [r1]
665 ; ARM: ldr r1, [r1]
769666 ; ARM-NEXT: ldr r0, [r0]
770667 ; ARM-NEXT: mul r1, r2, r1
771668 ; ARM-NEXT: eor r0, r0, r3
774671 ; ARM-NEXT: bx lr
775672 ;
776673 ; ARMEB-LABEL: test2:
777 ; ARMEB: @ %bb.0: @ %entry
778 ; ARMEB-NEXT: ldr r1, [r1]
674 ; ARMEB: ldr r1, [r1]
779675 ; ARMEB-NEXT: ldr r0, [r0]
780676 ; ARMEB-NEXT: mul r1, r2, r1
781677 ; ARMEB-NEXT: eor r0, r0, r3
784680 ; ARMEB-NEXT: bx lr
785681 ;
786682 ; THUMB1-LABEL: test2:
787 ; THUMB1: @ %bb.0: @ %entry
788 ; THUMB1-NEXT: ldr r1, [r1]
683 ; THUMB1: ldr r1, [r1]
789684 ; THUMB1-NEXT: muls r1, r2, r1
790685 ; THUMB1-NEXT: ldr r0, [r0]
791686 ; THUMB1-NEXT: eors r0, r3
794689 ; THUMB1-NEXT: bx lr
795690 ;
796691 ; THUMB2-LABEL: test2:
797 ; THUMB2: @ %bb.0: @ %entry
798 ; THUMB2-NEXT: ldr r1, [r1]
692 ; THUMB2: ldr r1, [r1]
799693 ; THUMB2-NEXT: ldr r0, [r0]
800694 ; THUMB2-NEXT: muls r1, r2, r1
801695 ; THUMB2-NEXT: eors r0, r3
814708
815709 define arm_aapcscc i32 @test3(i32* %a, i32* %b, i32 %x, i16* %y) {
816710 ; ARM-LABEL: test3:
817 ; ARM: @ %bb.0: @ %entry
818 ; ARM-NEXT: ldr r0, [r0]
711 ; ARM: ldr r0, [r0]
819712 ; ARM-NEXT: mul r1, r2, r0
820713 ; ARM-NEXT: ldrh r2, [r3]
821714 ; ARM-NEXT: eor r0, r0, r2
824717 ; ARM-NEXT: bx lr
825718 ;
826719 ; ARMEB-LABEL: test3:
827 ; ARMEB: @ %bb.0: @ %entry
828 ; ARMEB-NEXT: ldr r0, [r0]
720 ; ARMEB: ldr r0, [r0]
829721 ; ARMEB-NEXT: mul r1, r2, r0
830722 ; ARMEB-NEXT: ldrh r2, [r3]
831723 ; ARMEB-NEXT: eor r0, r0, r2
834726 ; ARMEB-NEXT: bx lr
835727 ;
836728 ; THUMB1-LABEL: test3:
837 ; THUMB1: @ %bb.0: @ %entry
838 ; THUMB1-NEXT: ldr r0, [r0]
729 ; THUMB1: ldr r0, [r0]
839730 ; THUMB1-NEXT: muls r2, r0, r2
840731 ; THUMB1-NEXT: ldrh r1, [r3]
841732 ; THUMB1-NEXT: eors r1, r0
844735 ; THUMB1-NEXT: bx lr
845736 ;
846737 ; THUMB2-LABEL: test3:
847 ; THUMB2: @ %bb.0: @ %entry
848 ; THUMB2-NEXT: ldr r0, [r0]
738 ; THUMB2: ldr r0, [r0]
849739 ; THUMB2-NEXT: mul r1, r2, r0
850740 ; THUMB2-NEXT: ldrh r2, [r3]
851741 ; THUMB2-NEXT: eors r0, r2
865755
866756 define arm_aapcscc i32 @test4(i32* %a, i32* %b, i32 %x, i32 %y) {
867757 ; ARM-LABEL: test4:
868 ; ARM: @ %bb.0: @ %entry
869 ; ARM-NEXT: mul r2, r2, r3
870 ; ARM-NEXT: ldr r1, [r1]
871 ; ARM-NEXT: ldr r0, [r0]
758 ; ARM: mul r2, r2, r3
759 ; ARM-NEXT: ldrh r1, [r1]
760 ; ARM-NEXT: ldrh r0, [r0]
872761 ; ARM-NEXT: eor r0, r0, r1
873 ; ARM-NEXT: orr r0, r0, r2
874 ; ARM-NEXT: uxth r0, r0
762 ; ARM-NEXT: uxth r1, r2
763 ; ARM-NEXT: orr r0, r0, r1
875764 ; ARM-NEXT: bx lr
876765 ;
877766 ; ARMEB-LABEL: test4:
878 ; ARMEB: @ %bb.0: @ %entry
879 ; ARMEB-NEXT: mul r2, r2, r3
880 ; ARMEB-NEXT: ldr r1, [r1]
881 ; ARMEB-NEXT: ldr r0, [r0]
767 ; ARMEB: mul r2, r2, r3
768 ; ARMEB-NEXT: ldrh r1, [r1, #2]
769 ; ARMEB-NEXT: ldrh r0, [r0, #2]
882770 ; ARMEB-NEXT: eor r0, r0, r1
883 ; ARMEB-NEXT: orr r0, r0, r2
884 ; ARMEB-NEXT: uxth r0, r0
771 ; ARMEB-NEXT: uxth r1, r2
772 ; ARMEB-NEXT: orr r0, r0, r1
885773 ; ARMEB-NEXT: bx lr
886774 ;
887775 ; THUMB1-LABEL: test4:
888 ; THUMB1: @ %bb.0: @ %entry
776 ; THUMB1: ldrh r1, [r1]
777 ; THUMB1-NEXT: ldrh r4, [r0]
778 ; THUMB1-NEXT: eors r4, r1
889779 ; THUMB1-NEXT: muls r2, r3, r2
890 ; THUMB1-NEXT: ldr r1, [r1]
891 ; THUMB1-NEXT: ldr r0, [r0]
892 ; THUMB1-NEXT: eors r0, r1
893 ; THUMB1-NEXT: orrs r0, r2
894 ; THUMB1-NEXT: uxth r0, r0
895 ; THUMB1-NEXT: bx lr
780 ; THUMB1-NEXT: uxth r0, r2
781 ; THUMB1-NEXT: orrs r0, r4
782 ; THUMB1-NEXT: pop
896783 ;
897784 ; THUMB2-LABEL: test4:
898 ; THUMB2: @ %bb.0: @ %entry
899 ; THUMB2-NEXT: muls r2, r3, r2
900 ; THUMB2-NEXT: ldr r1, [r1]
901 ; THUMB2-NEXT: ldr r0, [r0]
785 ; THUMB2: ldrh r1, [r1]
786 ; THUMB2-NEXT: ldrh r0, [r0]
902787 ; THUMB2-NEXT: eors r0, r1
903 ; THUMB2-NEXT: orrs r0, r2
904 ; THUMB2-NEXT: uxth r0, r0
788 ; THUMB2-NEXT: mul r1, r2, r3
789 ; THUMB2-NEXT: uxth r1, r1
790 ; THUMB2-NEXT: orrs r0, r1
905791 ; THUMB2-NEXT: bx lr
906792 entry:
907793 %0 = load i32, i32* %a, align 4
915801
916802 define arm_aapcscc i32 @test5(i32* %a, i32* %b, i32 %x, i16 zeroext %y) {
917803 ; ARM-LABEL: test5:
918 ; ARM: @ %bb.0: @ %entry
919 ; ARM-NEXT: ldr r1, [r1]
920 ; ARM-NEXT: ldr r0, [r0]
804 ; ARM: ldr r1, [r1]
805 ; ARM-NEXT: ldrh r0, [r0]
921806 ; ARM-NEXT: mul r1, r2, r1
922807 ; ARM-NEXT: eor r0, r0, r3
808 ; ARM-NEXT: uxth r1, r1
923809 ; ARM-NEXT: orr r0, r0, r1
924 ; ARM-NEXT: uxth r0, r0
925810 ; ARM-NEXT: bx lr
926811 ;
927812 ; ARMEB-LABEL: test5:
928 ; ARMEB: @ %bb.0: @ %entry
929 ; ARMEB-NEXT: ldr r1, [r1]
930 ; ARMEB-NEXT: ldr r0, [r0]
813 ; ARMEB: ldr r1, [r1]
814 ; ARMEB-NEXT: ldrh r0, [r0, #2]
931815 ; ARMEB-NEXT: mul r1, r2, r1
932816 ; ARMEB-NEXT: eor r0, r0, r3
817 ; ARMEB-NEXT: uxth r1, r1
933818 ; ARMEB-NEXT: orr r0, r0, r1
934 ; ARMEB-NEXT: uxth r0, r0
935819 ; ARMEB-NEXT: bx lr
936820 ;
937821 ; THUMB1-LABEL: test5:
938 ; THUMB1: @ %bb.0: @ %entry
939 ; THUMB1-NEXT: ldr r1, [r1]
940 ; THUMB1-NEXT: muls r1, r2, r1
941 ; THUMB1-NEXT: ldr r0, [r0]
942 ; THUMB1-NEXT: eors r0, r3
943 ; THUMB1-NEXT: orrs r0, r1
822 ; THUMB1: ldrh r4, [r0]
823 ; THUMB1-NEXT: eors r4, r3
824 ; THUMB1-NEXT: ldr r0, [r1]
825 ; THUMB1-NEXT: muls r0, r2, r0
944826 ; THUMB1-NEXT: uxth r0, r0
945 ; THUMB1-NEXT: bx lr
827 ; THUMB1-NEXT: orrs r0, r4
828 ; THUMB1-NEXT: pop
946829 ;
947830 ; THUMB2-LABEL: test5:
948 ; THUMB2: @ %bb.0: @ %entry
949 ; THUMB2-NEXT: ldr r1, [r1]
950 ; THUMB2-NEXT: ldr r0, [r0]
831 ; THUMB2: ldr r1, [r1]
832 ; THUMB2-NEXT: ldrh r0, [r0]
951833 ; THUMB2-NEXT: muls r1, r2, r1
952834 ; THUMB2-NEXT: eors r0, r3
835 ; THUMB2-NEXT: uxth r1, r1
953836 ; THUMB2-NEXT: orrs r0, r1
954 ; THUMB2-NEXT: uxth r0, r0
955837 ; THUMB2-NEXT: bx lr
956838 entry:
957839 %0 = load i32, i32* %a, align 4
1023905 define arm_aapcscc i1 @test7(i16* %x, i16 %y, i8 %z) {
1024906 ; ARM-LABEL: test7:
1025907 ; ARM: @ %bb.0: @ %entry
1026 ; ARM-NEXT: ldrh r0, [r0]
908 ; ARM-NEXT: ldrb r0, [r0]
1027909 ; ARM-NEXT: uxtb r2, r2
1028 ; ARM-NEXT: and r0, r0, r1
1029 ; ARM-NEXT: uxtb r1, r0
910 ; ARM-NEXT: and r1, r0, r1
1030911 ; ARM-NEXT: mov r0, #0
1031912 ; ARM-NEXT: cmp r1, r2
1032913 ; ARM-NEXT: movweq r0, #1
1034915 ;
1035916 ; ARMEB-LABEL: test7:
1036917 ; ARMEB: @ %bb.0: @ %entry
1037 ; ARMEB-NEXT: ldrh r0, [r0]
918 ; ARMEB-NEXT: ldrb r0, [r0, #1]
1038919 ; ARMEB-NEXT: uxtb r2, r2
1039 ; ARMEB-NEXT: and r0, r0, r1
1040 ; ARMEB-NEXT: uxtb r1, r0
920 ; ARMEB-NEXT: and r1, r0, r1
1041921 ; ARMEB-NEXT: mov r0, #0
1042922 ; ARMEB-NEXT: cmp r1, r2
1043923 ; ARMEB-NEXT: movweq r0, #1
1045925 ;
1046926 ; THUMB1-LABEL: test7:
1047927 ; THUMB1: @ %bb.0: @ %entry
1048 ; THUMB1-NEXT: ldrh r0, [r0]
1049 ; THUMB1-NEXT: ands r0, r1
1050 ; THUMB1-NEXT: uxtb r3, r0
928 ; THUMB1-NEXT: ldrb r3, [r0]
929 ; THUMB1-NEXT: ands r3, r1
1051930 ; THUMB1-NEXT: uxtb r2, r2
1052931 ; THUMB1-NEXT: movs r0, #1
1053932 ; THUMB1-NEXT: movs r1, #0
1060939 ;
1061940 ; THUMB2-LABEL: test7:
1062941 ; THUMB2: @ %bb.0: @ %entry
1063 ; THUMB2-NEXT: ldrh r0, [r0]
942 ; THUMB2-NEXT: ldrb r0, [r0]
1064943 ; THUMB2-NEXT: uxtb r2, r2
1065 ; THUMB2-NEXT: ands r0, r1
1066 ; THUMB2-NEXT: uxtb r1, r0
944 ; THUMB2-NEXT: ands r1, r0
1067945 ; THUMB2-NEXT: movs r0, #0
1068946 ; THUMB2-NEXT: cmp r1, r2
1069947 ; THUMB2-NEXT: it eq
1080958 define arm_aapcscc void @test8(i32* nocapture %p) {
1081959 ; ARM-LABEL: test8:
1082960 ; ARM: @ %bb.0: @ %entry
1083 ; ARM-NEXT: ldr r1, [r0]
1084 ; ARM-NEXT: mvn r1, r1
1085 ; ARM-NEXT: uxtb r1, r1
961 ; ARM-NEXT: ldrb r1, [r0]
962 ; ARM-NEXT: eor r1, r1, #255
1086963 ; ARM-NEXT: str r1, [r0]
1087964 ; ARM-NEXT: bx lr
1088965 ;
1089966 ; ARMEB-LABEL: test8:
1090967 ; ARMEB: @ %bb.0: @ %entry
1091 ; ARMEB-NEXT: ldr r1, [r0]
1092 ; ARMEB-NEXT: mvn r1, r1
1093 ; ARMEB-NEXT: uxtb r1, r1
968 ; ARMEB-NEXT: ldrb r1, [r0, #3]
969 ; ARMEB-NEXT: eor r1, r1, #255
1094970 ; ARMEB-NEXT: str r1, [r0]
1095971 ; ARMEB-NEXT: bx lr
1096972 ;
1097973 ; THUMB1-LABEL: test8:
1098974 ; THUMB1: @ %bb.0: @ %entry
1099 ; THUMB1-NEXT: ldr r1, [r0]
975 ; THUMB1-NEXT: ldrb r1, [r0]
1100976 ; THUMB1-NEXT: movs r2, #255
1101 ; THUMB1-NEXT: bics r2, r1
977 ; THUMB1-NEXT: eors r2, r1
1102978 ; THUMB1-NEXT: str r2, [r0]
1103979 ; THUMB1-NEXT: bx lr
1104980 ;
1105981 ; THUMB2-LABEL: test8:
1106982 ; THUMB2: @ %bb.0: @ %entry
1107 ; THUMB2-NEXT: ldr r1, [r0]
1108 ; THUMB2-NEXT: mvns r1, r1
1109 ; THUMB2-NEXT: uxtb r1, r1
983 ; THUMB2-NEXT: ldrb r1, [r0]
984 ; THUMB2-NEXT: eor r1, r1, #255
1110985 ; THUMB2-NEXT: str r1, [r0]
1111986 ; THUMB2-NEXT: bx lr
1112987 entry:
1116991 store i32 %and, i32* %p, align 4
1117992 ret void
1118993 }
994
995 define arm_aapcscc void @test9(i32* nocapture %p) {
996 ; ARM-LABEL: test9:
997 ; ARM: @ %bb.0: @ %entry
998 ; ARM-NEXT: ldrb r1, [r0]
999 ; ARM-NEXT: eor r1, r1, #255
1000 ; ARM-NEXT: str r1, [r0]
1001 ; ARM-NEXT: bx lr
1002 ;
1003 ; ARMEB-LABEL: test9:
1004 ; ARMEB: @ %bb.0: @ %entry
1005 ; ARMEB-NEXT: ldrb r1, [r0, #3]
1006 ; ARMEB-NEXT: eor r1, r1, #255
1007 ; ARMEB-NEXT: str r1, [r0]
1008 ; ARMEB-NEXT: bx lr
1009 ;
1010 ; THUMB1-LABEL: test9:
1011 ; THUMB1: @ %bb.0: @ %entry
1012 ; THUMB1-NEXT: ldrb r1, [r0]
1013 ; THUMB1-NEXT: movs r2, #255
1014 ; THUMB1-NEXT: eors r2, r1
1015 ; THUMB1-NEXT: str r2, [r0]
1016 ; THUMB1-NEXT: bx lr
1017 ;
1018 ; THUMB2-LABEL: test9:
1019 ; THUMB2: @ %bb.0: @ %entry
1020 ; THUMB2-NEXT: ldrb r1, [r0]
1021 ; THUMB2-NEXT: eor r1, r1, #255
1022 ; THUMB2-NEXT: str r1, [r0]
1023 ; THUMB2-NEXT: bx lr
1024 entry:
1025 %0 = load i32, i32* %p, align 4
1026 %neg = xor i32 %0, -1
1027 %and = and i32 %neg, 255
1028 store i32 %and, i32* %p, align 4
1029 ret void
1030 }
1031
1032 ; ARM-LABEL: test10:
1033 ; ARM: @ %bb.0: @ %entry
1034 ; ARM-NEXT: ldrb r1, [r0]
1035 ; ARM-NEXT: eor r1, r1, #255
1036 ; ARM-NEXT: str r1, [r0]
1037 ; ARM-NEXT: bx lr
1038 ;
1039 ; ARMEB-LABEL: test10:
1040 ; ARMEB: @ %bb.0: @ %entry
1041 ; ARMEB-NEXT: ldrb r1, [r0, #3]
1042 ; ARMEB-NEXT: eor r1, r1, #255
1043 ; ARMEB-NEXT: str r1, [r0]
1044 ; ARMEB-NEXT: bx lr
1045 ;
1046 ; THUMB1-LABEL: test10:
1047 ; THUMB1: @ %bb.0: @ %entry
1048 ; THUMB1-NEXT: ldrb r1, [r0]
1049 ; THUMB1-NEXT: movs r2, #255
1050 ; THUMB1-NEXT: eors r2, r1
1051 ; THUMB1-NEXT: str r2, [r0]
1052 ; THUMB1-NEXT: bx lr
1053 ;
1054 ; THUMB2-LABEL: test10:
1055 ; THUMB2: @ %bb.0: @ %entry
1056 ; THUMB2-NEXT: ldrb r1, [r0]
1057 ; THUMB2-NEXT: eor r1, r1, #255
1058 ; THUMB2-NEXT: str r1, [r0]
1059 ; THUMB2-NEXT: bx lr
1060 define arm_aapcscc void @test10(i32* nocapture %p) {
1061 entry:
1062 %0 = load i32, i32* %p, align 4
1063 %neg = and i32 %0, 255
1064 %and = xor i32 %neg, 255
1065 store i32 %and, i32* %p, align 4
1066 ret void
1067 }
1068