llvm.org GIT mirror llvm / 72aadc0
Fix bad EXTRACT_SUBREG in instruction selection for extending-loads on NEON. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154915 91177308-0d34-0410-b5e6-96231b3b80d8 James Molloy 7 years ago
2 changed file(s) with 58 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
56335633
56345634 // extload, zextload and sextload for a lengthening load followed by another
56355635 // lengthening load, to quadruple the initial length.
5636 //
56365637 // Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0> =
56375638 // Pat<(v4i32 (extloadvi8 addrmode5:$addr))
56385639 // (EXTRACT_SUBREG (VMOVLuv4i32
56435644 // qsub_0)>;
56445645 multiclass Lengthen_Double
56455646 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
5646 string Insn2Ty, SubRegIndex RegType> {
5647 string Insn2Ty> {
5648 def _Any : Pat<(!cast("v" # DestLanes # DestTy)
5649 (!cast("extloadv" # SrcTy) addrmode5:$addr)),
5650 (!cast("VMOVLuv" # Insn2Lanes # Insn2Ty)
5651 (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn1Lanes # Insn1Ty)
5652 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
5653 ssub_0)), dsub_0))>;
5654 def _Z : Pat<(!cast("v" # DestLanes # DestTy)
5655 (!cast("zextloadv" # SrcTy) addrmode5:$addr)),
5656 (!cast("VMOVLuv" # Insn2Lanes # Insn2Ty)
5657 (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn1Lanes # Insn1Ty)
5658 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
5659 ssub_0)), dsub_0))>;
5660 def _S : Pat<(!cast("v" # DestLanes # DestTy)
5661 (!cast("sextloadv" # SrcTy) addrmode5:$addr)),
5662 (!cast("VMOVLsv" # Insn2Lanes # Insn2Ty)
5663 (EXTRACT_SUBREG (!cast("VMOVLsv" # Insn1Lanes # Insn1Ty)
5664 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
5665 ssub_0)), dsub_0))>;
5666 }
5667
5668 // extload, zextload and sextload for a lengthening load followed by another
5669 // lengthening load, to quadruple the initial length, but which ends up only
5670 // requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
5671 //
5672 // Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
5673 // Pat<(v4i32 (extloadvi8 addrmode5:$addr))
5674 // (EXTRACT_SUBREG (VMOVLuv4i32
5675 // (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
5676 // (VLDRS addrmode5:$addr),
5677 // ssub_0)),
5678 // dsub_0)),
5679 // dsub_0)>;
5680 multiclass Lengthen_HalfDouble
5681 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
5682 string Insn2Ty> {
56475683 def _Any : Pat<(!cast("v" # DestLanes # DestTy)
56485684 (!cast("extloadv" # SrcTy) addrmode5:$addr)),
56495685 (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn2Lanes # Insn2Ty)
56505686 (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn1Lanes # Insn1Ty)
56515687 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
56525688 ssub_0)), dsub_0)),
5653 RegType)>;
5689 dsub_0)>;
56545690 def _Z : Pat<(!cast("v" # DestLanes # DestTy)
56555691 (!cast("zextloadv" # SrcTy) addrmode5:$addr)),
56565692 (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn2Lanes # Insn2Ty)
56575693 (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn1Lanes # Insn1Ty)
56585694 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
56595695 ssub_0)), dsub_0)),
5660 RegType)>;
5696 dsub_0)>;
56615697 def _S : Pat<(!cast("v" # DestLanes # DestTy)
56625698 (!cast("sextloadv" # SrcTy) addrmode5:$addr)),
56635699 (EXTRACT_SUBREG (!cast("VMOVLsv" # Insn2Lanes # Insn2Ty)
56645700 (EXTRACT_SUBREG (!cast("VMOVLsv" # Insn1Lanes # Insn1Ty)
56655701 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
56665702 ssub_0)), dsub_0)),
5667 RegType)>;
5703 dsub_0)>;
56685704 }
56695705
56705706 defm : Lengthen_Single<"8", "i16", "i8">; // v8i8 -> v8i16
56755711 defm : Lengthen_HalfSingle<"2", "i16", "i8", "8", "i16">; // v2i8 -> v2i16
56765712 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
56775713
5678 // Double lengthening - v4i8 -> v4i16 -> v4i32
5679 defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0>;
5714 // Double lengthening - v4i8 -> v4i16 -> v4i32
5715 defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32">;
56805716 // v2i8 -> v2i16 -> v2i32
5681 defm : Lengthen_Double<"2", "i32", "i8", "8", "i16", "4", "i32", dsub_0>;
5717 defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">;
56825718 // v2i16 -> v2i32 -> v2i64
5683 defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64", qsub_0>;
5719 defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">;
56845720
56855721 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
56865722 def : Pat<(v2i64 (extloadvi8 addrmode5:$addr)),
4343 %1 = fptoui <4 x float> %v to <4 x i8>
4444 ret <4 x i8> %1
4545 }
46
47 ; CHECK: i:
48 define <4 x i8> @i(<4 x i8>* %x) {
49 ; CHECK: vldr
50 ; CHECK: vmovl.s8
51 ; CHECK: vmovl.s16
52 ; CHECK: vrecpe
53 ; CHECK: vrecps
54 ; CHECK: vmul
55 ; CHECK: vmovn
56 %1 = load <4 x i8>* %x, align 4
57 %2 = sdiv <4 x i8> zeroinitializer, %1
58 ret <4 x i8> %2
59 }