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Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 17 years ago
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0 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
1 //
2 // This file defines a simple peephole instruction selector for the x86 platform
3 //
4 //===----------------------------------------------------------------------===//
5
6 #include "X86.h"
7 #include "X86InstructionInfo.h"
8 #include "llvm/Function.h"
9 #include "llvm/iTerminators.h"
10 #include "llvm/Type.h"
11 #include "llvm/CodeGen/MFunction.h"
12 #include "llvm/CodeGen/MInstBuilder.h"
13 #include "llvm/Support/InstVisitor.h"
14 #include
15
16 namespace {
17 struct ISel : public InstVisitor { // eventually will be a FunctionPass
18 MFunction *F; // The function we are compiling into
19 MBasicBlock *BB; // The current basic block we are compiling
20
21 unsigned CurReg;
22 std::map RegMap; // Mapping between Val's and SSA Regs
23
24 ISel(MFunction *f)
25 : F(f), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
26
27 /// runOnFunction - Top level implementation of instruction selection for
28 /// the entire function.
29 ///
30 bool runOnFunction(Function &F) {
31 visit(F);
32 RegMap.clear();
33 return false; // We never modify the LLVM itself.
34 }
35
36 /// visitBasicBlock - This method is called when we are visiting a new basic
37 /// block. This simply creates a new MBasicBlock to emit code into and adds
38 /// it to the current MFunction. Subsequent visit* for instructions will be
39 /// invoked for all instructions in the basic block.
40 ///
41 void visitBasicBlock(BasicBlock &LLVM_BB) {
42 BB = new MBasicBlock();
43 // FIXME: Use the auto-insert form when it's available
44 F->getBasicBlockList().push_back(BB);
45 }
46
47 // Visitation methods for various instructions. These methods simply emit
48 // fixed X86 code for each instruction.
49 //
50 void visitReturnInst(ReturnInst &RI);
51 void visitAdd(BinaryOperator &B);
52
53 void visitInstruction(Instruction &I) {
54 std::cerr << "Cannot instruction select: " << I;
55 abort();
56 }
57
58 /// getReg - This method turns an LLVM value into a register number. This
59 /// is guaranteed to produce the same register number for a particular value
60 /// every time it is queried.
61 ///
62 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
63 unsigned getReg(Value *V) {
64 unsigned &Reg = RegMap[V];
65 if (Reg == 0)
66 Reg = CurReg++;
67
68 // FIXME: Constants should be thrown into registers here and appended to
69 // the end of the current basic block!
70
71 return Reg;
72 }
73
74 };
75 }
76
77 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
78 /// we have the following possibilities:
79 ///
80 /// ret void: No return value, simply emit a 'ret' instruction
81 /// ret sbyte, ubyte : Extend value into EAX and return
82 /// ret short, ushort: Extend value into EAX and return
83 /// ret int, uint : Move value into EAX and return
84 /// ret pointer : Move value into EAX and return
85 /// ret long, ulong : Move value into EAX/EDX (?) and return
86 /// ret float/double : ? Top of FP stack? XMM0?
87 ///
88 void ISel::visitReturnInst(ReturnInst &I) {
89 if (I.getNumOperands() != 0) { // Not 'ret void'?
90 // Move result into a hard register... then emit a ret
91 visitInstruction(I); // abort
92 }
93
94 // Emit a simple 'ret' instruction... appending it to the end of the basic
95 // block
96 new MInstruction(BB, X86::RET);
97 }
98
99
100 /// 'add' instruction - Simply turn this into an x86 reg,reg add instruction.
101 void ISel::visitAdd(BinaryOperator &B) {
102 unsigned Op0r = getReg(B.getOperand(0)), Op1r = getReg(B.getOperand(1));
103 unsigned DestReg = getReg(B);
104
105 switch (B.getType()->getPrimitiveSize()) {
106 case 1: // UByte, SByte
107 BuildMInst(BB, X86::ADDrr8, DestReg).addReg(Op0r).addReg(Op1r);
108 break;
109 case 2: // UShort, Short
110 BuildMInst(BB, X86::ADDrr16, DestReg).addReg(Op0r).addReg(Op1r);
111 break;
112 case 4: // UInt, Int
113 BuildMInst(BB, X86::ADDrr32, DestReg).addReg(Op0r).addReg(Op1r);
114 break;
115
116 case 8: // ULong, Long
117 default:
118 visitInstruction(B); // abort
119 }
120 }
121
122
123
124 /// X86SimpleInstructionSelection - This function converts an LLVM function into
125 /// a machine code representation is a very simple peep-hole fashion. The
126 /// generated code sucks but the implementation is nice and simple.
127 ///
128 MFunction *X86SimpleInstructionSelection(Function &F) {
129 MFunction *Result = new MFunction();
130 ISel(Result).runOnFunction(F);
131 return Result;
132 }
0 LEVEL = ../../..
1 LIBRARYNAME = x86
2 include $(LEVEL)/Makefile.common
3
0 //===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
1 //
2 // This file contains a printer that converts from our internal representation
3 // of LLVM code to a nice human readable form that is suitable for debuggging.
4 //
5 //===----------------------------------------------------------------------===//
6
7 #include "X86.h"
8 #include
9
10 /// X86PrintCode - Print out the specified machine code function to the
11 /// specified stream. This function should work regardless of whether or not
12 /// the function is in SSA form or not, although when in SSA form, we obviously
13 /// don't care about being consumable by an assembler.
14 ///
15 void X86PrintCode(const MFunction *MF, std::ostream &O) {
16 O << "x86 printing not implemented yet!\n";
17
18 // This should use the X86InstructionInfo::print method to print assembly for
19 // each instruction
20 }
0 //===- README.txt - Information about the X86 backend and related files ---===//
1 //
2 // This file contains random notes and points of interest about the X86 backend.
3 //
4 // Snippets of this document will probably become the final report for CS497
5 //
6 //===----------------------------------------------------------------------===//
7
8 ===========
9 I. Overview
10 ===========
11
12 This directory contains a machine description for the X86 processor. Currently
13 this machine description is used for a high performance code generator used by a
14 LLVM JIT. One of the main objectives that we would like to support with this
15 project is to build a nice clean code generator that may be extended in the
16 future in a variety of ways: new targets, new optimizations, new
17 transformations, etc.
18
19 This document describes the current state of the LLVM JIT, along with
20 implementation notes, design decisions, and other stuff.
21
22
23 ===================================
24 II. Architecture / Design Decisions
25 ===================================
26
27 We designed the infrastructure for the machine specific representation to be as
28 light-weight as possible, while also being able to support as many targets as
29 possible with our framework. This framework should allow us to share many
30 common machine specific transformations (register allocation, instruction
31 scheduling, etc...) among all of the backends that may eventually be supported
32 by the JIT, and unify the JIT and static compiler backends.
33
34 At the high-level, LLVM code is translated to a machine specific representation
35 formed out of MFunction, MBasicBlock, and MInstruction instances (defined in
36 include/llvm/CodeGen). This representation is completely target agnostic,
37 representing instructions in their most abstract form: an opcode, a destination,
38 and a series of operands. This representation is designed to support both SSA
39 representation for machine code, as well as a register allocated, non-SSA form.
40
41 Because the M* representation must work regardless of the target machine, it
42 contains very little semantic information about the program. To get semantic
43 information about the program, a layer of Target description datastructures are
44 used, defined in include/llvm/Target.
45
46 Currently the Sparc backend and the X86 backend do not share a common
47 representation. This is an intentional decision, and will be rectified in the
48 future (after the project is done).
49
50
51 =======================
52 III. Source Code Layout
53 =======================
54
55 The LLVM-JIT is composed of source files primarily in the following locations:
56
57 include/llvm/CodeGen
58 --------------------
59
60 This directory contains header files that are used to represent the program in a
61 machine specific representation. It currently also contains a bunch of stuff
62 used by the Sparc backend that we don't want to get mixed up in.
63
64 include/llvm/Target
65 -------------------
66
67 This directory contains header files that are used to interpret the machine
68 specific representation of the program. This allows us to write generic
69 transformations that will work on any target that implements the interfaces
70 defined in this directory. Again, this also contains a bunch of stuff from the
71 Sparc Backend that we don't want to deal with.
72
73 lib/CodeGen
74 -----------
75 This directory will contain all of the target independant transformations (for
76 example, register allocation) that we write. These transformations should only
77 use information exposed through the Target interface, it should not include any
78 target specific header files.
79
80 lib/Target/X86
81 --------------
82 This directory contains the machine description for X86 that is required to the
83 rest of the compiler working. It contains any code that is truely specific to
84 the X86 backend, for example the instruction selector and machine code emitter.
85
86 tools/jello
87 -----------
88 This directory contains the top-level code for the JIT compiler.
89
90 test/Regression/Jello
91 ---------------------
92 This directory contains regression tests for the JIT. Initially it contains a
93 bunch of really trivial testcases that we should build up to supporting.
94
95
96 ==========================
97 IV. TODO / Future Projects
98 ==========================
99
100 There are a large number of things remaining to do. Here is a partial list:
101
102 Critial path:
103 -------------
104
105 0. Finish providing SSA form. This involves keeping track of some information
106 when instructions are added to the function, but should not affect that API
107 for creating new MInstructions or adding them to the program. There are
108 also various FIXMEs in the M* files that need to get taken care of in the
109 near term.
110 1. Finish dumb instruction selector
111 2. Write dumb register allocator
112 3. Write assembly language emitter
113 4. Write machine code emitter
114
115 Next Phase:
116 -----------
117 1. Implement linear time optimal instruction selector
118 2. Implement smarter (linear scan?) register allocator
119
120 After this project:
121 -------------------
122 1. Implement lots of nifty runtime optimizations
123 2. Implement a static compiler backend for x86
124 3. Migrate Sparc backend to new representation
125 4. Implement new spiffy targets: IA64? X86-64? M68k? Who knows...
126
127 Infrastructure Improvements:
128 ----------------------------
129
130 1. Bytecode is designed to be able to read particular functions from the
131 bytecode without having to read the whole program. Bytecode reader should be
132 extended to allow on demand loading of functions.
133
134 2. PassManager needs to be able to run just a single function through a pipeline
135 of FunctionPass's. When this happens, all of our code will become
136 FunctionPass's for real.
137
138 3. llvmgcc needs to be modified to output 32-bit little endian LLVM files.
139 Preferably it will be parameterizable so that multiple binaries need not
140 exist. Until this happens, we will be restricted to using type safe
141 programs (most of the Olden suite and many smaller tests), which should be
142 sufficient for our 497 project.
0 //===-- X86.h - Top-level interface for X86 representation ------*- C++ -*-===//
1 //
2 // This file contains the entry points for global functions defined in the x86
3 // target library, as used by the LLVM JIT.
4 //
5 // FIXME: This file will be dramatically changed in the future
6 //
7 //===----------------------------------------------------------------------===//
8
9 #ifndef TARGET_X86_H
10 #define TARGET_X86_H
11
12 #include
13 class MFunction;
14 class Function;
15
16 /// X86PrintCode - Print out the specified machine code function to the
17 /// specified stream. This function should work regardless of whether or not
18 /// the function is in SSA form or not.
19 ///
20 void X86PrintCode(const MFunction *MF, std::ostream &O);
21
22 /// X86SimpleInstructionSelection - This function converts an LLVM function into
23 /// a machine code representation is a very simple peep-hole fashion. The
24 /// generated code sucks but the implementation is nice and simple.
25 ///
26 MFunction *X86SimpleInstructionSelection(Function &F);
27
28 /// X86SimpleRegisterAllocation - This function converts the specified machine
29 /// code function from SSA form to use explicit registers by spilling every
30 /// register. Wow, great policy huh?
31 ///
32 inline void X86SimpleRegisterAllocation(MFunction *MF) {}
33
34 /// X86EmitCodeToMemory - This function converts a register allocated function
35 /// into raw machine code in a dynamically allocated chunk of memory. A pointer
36 /// to the start of the function is returned.
37 ///
38 inline void *X86EmitCodeToMemory(MFunction *MF) { return 0; }
39
40
41 // Put symbolic names in a namespace to avoid causing these to clash with all
42 // kinds of other things...
43 //
44 namespace X86 {
45 // Defines a large number of symbolic names for X86 registers. This defines a
46 // mapping from register name to register number.
47 //
48 enum Register {
49 #define R(ENUM, NAME, FLAGS, TSFLAGS) ENUM,
50 #include "X86RegisterInfo.def"
51 };
52
53 // This defines a large number of symbolic names for X86 instruction opcodes.
54 enum Opcode {
55 #define I(ENUM, NAME, FLAGS, TSFLAGS) ENUM,
56 #include "X86InstructionInfo.def"
57 };
58 }
59
60 #endif
0 //===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
1 //
2 // This file contains a printer that converts from our internal representation
3 // of LLVM code to a nice human readable form that is suitable for debuggging.
4 //
5 //===----------------------------------------------------------------------===//
6
7 #include "X86.h"
8 #include
9
10 /// X86PrintCode - Print out the specified machine code function to the
11 /// specified stream. This function should work regardless of whether or not
12 /// the function is in SSA form or not, although when in SSA form, we obviously
13 /// don't care about being consumable by an assembler.
14 ///
15 void X86PrintCode(const MFunction *MF, std::ostream &O) {
16 O << "x86 printing not implemented yet!\n";
17
18 // This should use the X86InstructionInfo::print method to print assembly for
19 // each instruction
20 }
0 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
1 //
2 // This file defines a simple peephole instruction selector for the x86 platform
3 //
4 //===----------------------------------------------------------------------===//
5
6 #include "X86.h"
7 #include "X86InstructionInfo.h"
8 #include "llvm/Function.h"
9 #include "llvm/iTerminators.h"
10 #include "llvm/Type.h"
11 #include "llvm/CodeGen/MFunction.h"
12 #include "llvm/CodeGen/MInstBuilder.h"
13 #include "llvm/Support/InstVisitor.h"
14 #include
15
16 namespace {
17 struct ISel : public InstVisitor { // eventually will be a FunctionPass
18 MFunction *F; // The function we are compiling into
19 MBasicBlock *BB; // The current basic block we are compiling
20
21 unsigned CurReg;
22 std::map RegMap; // Mapping between Val's and SSA Regs
23
24 ISel(MFunction *f)
25 : F(f), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
26
27 /// runOnFunction - Top level implementation of instruction selection for
28 /// the entire function.
29 ///
30 bool runOnFunction(Function &F) {
31 visit(F);
32 RegMap.clear();
33 return false; // We never modify the LLVM itself.
34 }
35
36 /// visitBasicBlock - This method is called when we are visiting a new basic
37 /// block. This simply creates a new MBasicBlock to emit code into and adds
38 /// it to the current MFunction. Subsequent visit* for instructions will be
39 /// invoked for all instructions in the basic block.
40 ///
41 void visitBasicBlock(BasicBlock &LLVM_BB) {
42 BB = new MBasicBlock();
43 // FIXME: Use the auto-insert form when it's available
44 F->getBasicBlockList().push_back(BB);
45 }
46
47 // Visitation methods for various instructions. These methods simply emit
48 // fixed X86 code for each instruction.
49 //
50 void visitReturnInst(ReturnInst &RI);
51 void visitAdd(BinaryOperator &B);
52
53 void visitInstruction(Instruction &I) {
54 std::cerr << "Cannot instruction select: " << I;
55 abort();
56 }
57
58 /// getReg - This method turns an LLVM value into a register number. This
59 /// is guaranteed to produce the same register number for a particular value
60 /// every time it is queried.
61 ///
62 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
63 unsigned getReg(Value *V) {
64 unsigned &Reg = RegMap[V];
65 if (Reg == 0)
66 Reg = CurReg++;
67
68 // FIXME: Constants should be thrown into registers here and appended to
69 // the end of the current basic block!
70
71 return Reg;
72 }
73
74 };
75 }
76
77 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
78 /// we have the following possibilities:
79 ///
80 /// ret void: No return value, simply emit a 'ret' instruction
81 /// ret sbyte, ubyte : Extend value into EAX and return
82 /// ret short, ushort: Extend value into EAX and return
83 /// ret int, uint : Move value into EAX and return
84 /// ret pointer : Move value into EAX and return
85 /// ret long, ulong : Move value into EAX/EDX (?) and return
86 /// ret float/double : ? Top of FP stack? XMM0?
87 ///
88 void ISel::visitReturnInst(ReturnInst &I) {
89 if (I.getNumOperands() != 0) { // Not 'ret void'?
90 // Move result into a hard register... then emit a ret
91 visitInstruction(I); // abort
92 }
93
94 // Emit a simple 'ret' instruction... appending it to the end of the basic
95 // block
96 new MInstruction(BB, X86::RET);
97 }
98
99
100 /// 'add' instruction - Simply turn this into an x86 reg,reg add instruction.
101 void ISel::visitAdd(BinaryOperator &B) {
102 unsigned Op0r = getReg(B.getOperand(0)), Op1r = getReg(B.getOperand(1));
103 unsigned DestReg = getReg(B);
104
105 switch (B.getType()->getPrimitiveSize()) {
106 case 1: // UByte, SByte
107 BuildMInst(BB, X86::ADDrr8, DestReg).addReg(Op0r).addReg(Op1r);
108 break;
109 case 2: // UShort, Short
110 BuildMInst(BB, X86::ADDrr16, DestReg).addReg(Op0r).addReg(Op1r);
111 break;
112 case 4: // UInt, Int
113 BuildMInst(BB, X86::ADDrr32, DestReg).addReg(Op0r).addReg(Op1r);
114 break;
115
116 case 8: // ULong, Long
117 default:
118 visitInstruction(B); // abort
119 }
120 }
121
122
123
124 /// X86SimpleInstructionSelection - This function converts an LLVM function into
125 /// a machine code representation is a very simple peep-hole fashion. The
126 /// generated code sucks but the implementation is nice and simple.
127 ///
128 MFunction *X86SimpleInstructionSelection(Function &F) {
129 MFunction *Result = new MFunction();
130 ISel(Result).runOnFunction(F);
131 return Result;
132 }
0 //===- X86InstructionInfo.cpp - X86 Instruction Information ---------------===//
1 //
2 // This file contains the X86 implementation of the MInstructionInfo class.
3 //
4 //===----------------------------------------------------------------------===//
5
6 #include "X86InstructionInfo.h"
7 #include "llvm/CodeGen/MInstruction.h"
8 #include
9
10 // X86Insts - Turn the InstructionInfo.def file into a bunch of instruction
11 // descriptors
12 //
13 static const MInstructionDesc X86Insts[] = {
14 #define I(ENUM, NAME, FLAGS, TSFLAGS) { NAME, FLAGS, TSFLAGS },
15 #include "X86InstructionInfo.def"
16 };
17
18 X86InstructionInfo::X86InstructionInfo()
19 : MInstructionInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) {
20 }
21
22
23 // print - Print out an x86 instruction in GAS syntax
24 void X86InstructionInfo::print(const MInstruction *MI, std::ostream &O) const {
25 // FIXME: This sucks.
26 O << get(MI->getOpcode()).Name << "\n";
27 }
28
0 //===-- X86InstructionInfo.def - X86 Instruction Information ----*- C++ -*-===//
1 //
2 // This file describes all of the instructions that the X86 backend uses. It
3 // relys on an external 'I' macro being defined that takes the arguments
4 // specified below, and is used to make all of the information relevant to an
5 // instruction be in one place.
6 //
7 //===----------------------------------------------------------------------===//
8
9 // NOTE: No include guards desired
10
11 #ifndef I
12 #errror "Must define I macro before including X86/X86InstructionInfo.def!"
13 #endif
14
15 // Arguments to be passed into the I macro
16 // #1: Enum name - This ends up being the opcode symbol in the X86 namespace
17 // #2: Opcode name, as used by the gnu assembler
18 // #3: Instruction Flags - This should be a field or'd together that contains
19 // constants from the MInstructionInfo.h file.
20 // #4: Target Specific Flags - Another bitfield containing X86 specific flags
21 // that we are interested in for each instruction
22 //
23
24 // The first instruction must always be the PHI instruction:
25 I(PHI , "phi", 0, 0)
26
27 // The second instruction must always be the noop instruction
28 I(NOOP , "nop", 0, 0) // nop 90
29
30 // Miscellaneous instructions
31 I(RET , "ret", MIF::RET, 0) // ret CB
32
33 I(ADDrr8 , "add", 0, 0) // R8 += R8 00/r
34 I(ADDrr16 , "add", 0, 0) // R16 += R16 01/r
35 I(ADDrr32 , "addl", 0, 0) // R32 += R32 02/r
36
37
38 // At this point, I is dead to undefine the macro
39 #undef I
0 //===- X86InstructionInfo.h - X86 Instruction Information ---------*-C++-*-===//
1 //
2 // This file contains the X86 implementation of the MInstructionInfo class.
3 //
4 //===----------------------------------------------------------------------===//
5
6 #ifndef X86INSTRUCTIONINFO_H
7 #define X86INSTRUCTIONINFO_H
8
9 #include "llvm/Target/MInstructionInfo.h"
10 #include "X86RegisterInfo.h"
11
12 class X86InstructionInfo : public MInstructionInfo {
13 const X86RegisterInfo RI;
14 public:
15 X86InstructionInfo();
16
17 /// getRegisterInfo - MInstructionInfo is a superset of MRegister info. As
18 /// such, whenever a client has an instance of instruction info, it should
19 /// always be able to get register info as well (through this method).
20 ///
21 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
22
23 /// print - Print out an x86 instruction in GAS syntax
24 ///
25 virtual void print(const MInstruction *MI, std::ostream &O) const;
26 };
27
28
29 #endif
0 //===- X86RegisterInfo.cpp - X86 Register Information ---------------------===//
1 //
2 // This file contains the X86 implementation of the MRegisterInfo class.
3 //
4 //===----------------------------------------------------------------------===//
5
6 #include "X86RegisterInfo.h"
7
8 // X86Regs - Turn the X86RegisterInfo.def file into a bunch of register
9 // descriptors
10 //
11 static const MRegisterDesc X86Regs[] = {
12 #define R(ENUM, NAME, FLAGS, TSFLAGS) { NAME, FLAGS, TSFLAGS },
13 #include "X86RegisterInfo.def"
14 };
15
16 X86RegisterInfo::X86RegisterInfo()
17 : MRegisterInfo(X86Regs, sizeof(X86Regs)/sizeof(X86Regs[0])) {
18 }
0 //===-- X86RegisterInfo.def - X86 Register Information ----------*- C++ -*-===//
1 //
2 // This file describes all of the registers that the X86 backend uses. It relys
3 // on an external 'R' macro being defined that takes the arguments specified
4 // below, and is used to make all of the information relevant to an registers be
5 // in one place.
6 //
7 //===----------------------------------------------------------------------===//
8
9 // NOTE: No include guards desired
10
11 #ifndef R
12 #errror "Must define R macro before including X86/X86RegisterInfo.def!"
13 #endif
14
15 // Arguments passed into the R macro
16 // #1: Enum Name - This ends up being a symbol in the X86 namespace
17 // #2: Register name - The name of the register as used by the gnu assembler
18 // #3: Register Flags - A bitfield of flags or'd together from the
19 // MRegisterInfo.h file.
20 // #4: Target Specific Flags - Another bitfield containing X86 specific flags
21 // as neccesary.
22
23
24 // The first register must always be a 'noop' register for all backends. This
25 // is used as the destination register for instructions that do not produce a
26 // value. Some frontends may use this as an operand register to mean special
27 // things, for example, the Sparc backend uses R#0 to mean %g0 which always
28 // PRODUCES the value 0. The X86 backend does not use this value as an operand
29 // register.
30 //
31 R(NoReg, "none", 0, 0)
32
33
34 // 32 bit registers, ordered as the processor does...
35 R(EAX, "eax", MRF::INT32, 0)
36 R(ECX, "ecx", MRF::INT32, 0)
37 R(EDX, "edx", MRF::INT32, 0)
38 R(EBX, "ebx", MRF::INT32, 0)
39 R(ESP, "esp", MRF::INT32, 0)
40 R(EBP, "ebp", MRF::INT32, 0)
41 R(ESI, "esi", MRF::INT32, 0)
42 R(EDI, "edi", MRF::INT32, 0)
43
44 // 16 bit registers, aliased with the corresponding 32 bit registers above
45 R(AX, "ax", MRF::INT16, 0)
46 R(CX, "cx", MRF::INT16, 0)
47 R(DX, "dx", MRF::INT16, 0)
48 R(BX, "bx", MRF::INT16, 0)
49 R(SP, "sp", MRF::INT16, 0)
50 R(BP, "bp", MRF::INT16, 0)
51 R(SI, "si", MRF::INT16, 0)
52 R(DI, "di", MRF::INT16, 0)
53
54 // 8 bit registers aliased with registers above as well
55 R(AL, "al", MRF::INT8, 0)
56 R(CL, "cl", MRF::INT8, 0)
57 R(DL, "dl", MRF::INT8, 0)
58 R(BL, "bl", MRF::INT8, 0)
59 R(AH, "ah", MRF::INT8, 0)
60 R(CH, "ch", MRF::INT8, 0)
61 R(DH, "dh", MRF::INT8, 0)
62 R(BH, "bh", MRF::INT8, 0)
63
64 // Flags, Segment registers, etc...
65
66 // We are now done with the R macro
67 #undef R
0 //===- X86RegisterInfo.h - X86 Register Information Impl ----------*-C++-*-===//
1 //
2 // This file contains the X86 implementation of the MRegisterInfo class.
3 //
4 //===----------------------------------------------------------------------===//
5
6 #ifndef X86REGISTERINFO_H
7 #define X86REGISTERINFO_H
8
9 #include "llvm/Target/MRegisterInfo.h"
10
11 struct X86RegisterInfo : public MRegisterInfo {
12 X86RegisterInfo();
13
14 };
15
16 #endif