llvm.org GIT mirror llvm / 7237ece
Moved enum and command-line option in separate file. Also added function that returns the user selected register allocator to the caller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8819 91177308-0d34-0410-b5e6-96231b3b80d8 Alkis Evlogimenos 17 years ago
3 changed file(s) with 40 addition(s) and 30 deletion(s). Raw diff Collapse all Expand all
1818 //
1919 extern const PassInfo *PHIEliminationID;
2020
21 enum RegAllocName { simple, local };
21 /// Creates a register allocator as the user specified on the command
22 /// line.
23 FunctionPass *createRegisterAllocator();
2224
2325 /// SimpleRegisterAllocation Pass - This pass converts the input machine code
2426 /// from SSA form to use explicit registers by spilling every register. Wow,
0 //===-- Passes.cpp - Target independent code generation passes -*- C++ -*-===//
1 //
2 // This file defines interfaces to access the target independent code
3 // generation passes provided by the LLVM backend.
4 //
5 //===---------------------------------------------------------------------===//
6
7 #include "llvm/CodeGen/Passes.h"
8 #include "Support/CommandLine.h"
9
10 namespace {
11 enum RegAllocName { simple, local };
12
13 cl::opt
14 RegAlloc("regalloc",
15 cl::desc("Register allocator to use: (default = simple)"),
16 cl::Prefix,
17 cl::values(clEnumVal(simple, " simple register allocator"),
18 clEnumVal(local, " local register allocator"),
19 0),
20 cl::init(local));
21 }
22
23 FunctionPass *createRegisterAllocator()
24 {
25 switch (RegAlloc) {
26 case simple:
27 return createSimpleRegisterAllocator();
28 case local:
29 return createLocalRegisterAllocator();
30 default:
31 assert(0 && "no register allocator selected");
32 return 0; // not reached
33 }
34 }
1515 #include "Support/Statistic.h"
1616
1717 namespace {
18 cl::opt
19 RegAlloc("regalloc",
20 cl::desc("Register allocator to use: (default = simple)"),
21 cl::Prefix,
22 cl::values(clEnumVal(simple, " simple register allocator"),
23 clEnumVal(local, " local register allocator"),
24 0),
25 cl::init(local));
26
2718 cl::opt PrintCode("print-machineinstrs",
2819 cl::desc("Print generated machine code"));
2920 cl::opt NoPatternISel("disable-pattern-isel", cl::init(true),
7263 PM.add(createMachineFunctionPrinterPass());
7364
7465 // Perform register allocation to convert to a concrete x86 representation
75 switch (RegAlloc) {
76 case simple:
77 PM.add(createSimpleRegisterAllocator());
78 break;
79 case local:
80 PM.add(createLocalRegisterAllocator());
81 break;
82 default:
83 assert(0 && "no register allocator selected");
84 }
66 PM.add(createRegisterAllocator());
8567
8668 if (PrintCode)
8769 PM.add(createMachineFunctionPrinterPass());
125107 PM.add(createMachineFunctionPrinterPass());
126108
127109 // Perform register allocation to convert to a concrete x86 representation
128 switch (RegAlloc) {
129 case simple:
130 PM.add(createSimpleRegisterAllocator());
131 break;
132 case local:
133 PM.add(createLocalRegisterAllocator());
134 break;
135 default:
136 assert(0 && "no register allocator selected");
137 }
110 PM.add(createRegisterAllocator());
138111
139112 if (PrintCode)
140113 PM.add(createMachineFunctionPrinterPass());