llvm.org GIT mirror llvm / 7221fef
[WebAssembly][NFC] Group SIMD-related ISel configuration Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish Differential Revision: https://reviews.llvm.org/D57263 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352262 91177308-0d34-0410-b5e6-96231b3b80d8 Thomas Lively 1 year, 3 months ago
1 changed file(s) with 52 addition(s) and 66 deletion(s). Raw diff Collapse all Expand all
6262 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
6363 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
6464 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
65 if (Subtarget->hasUnimplementedSIMD128()) {
66 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
67 addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass);
68 }
65 }
66 if (Subtarget->hasUnimplementedSIMD128()) {
67 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
68 addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass);
6969 }
7070 // Compute derived properties from the register classes.
7171 computeRegisterProperties(Subtarget->getRegisterInfo());
109109 setTruncStoreAction(T, MVT::f16, Expand);
110110 }
111111
112 // Support saturating add for i8x16 and i16x8
113 if (Subtarget->hasSIMD128())
114 for (auto T : {MVT::v16i8, MVT::v8i16})
115 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT})
116 setOperationAction(Op, T, Legal);
117
118112 // Expand unavailable integer operations.
119113 for (auto Op :
120114 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU,
121115 ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS,
122116 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
123 for (auto T : {MVT::i32, MVT::i64}) {
117 for (auto T : {MVT::i32, MVT::i64})
124118 setOperationAction(Op, T, Expand);
119 if (Subtarget->hasSIMD128())
120 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
121 setOperationAction(Op, T, Expand);
122 if (Subtarget->hasUnimplementedSIMD128())
123 setOperationAction(Op, MVT::v2i64, Expand);
124 }
125
126 // SIMD-specific configuration
127 if (Subtarget->hasSIMD128()) {
128 // Support saturating add for i8x16 and i16x8
129 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT})
130 for (auto T : {MVT::v16i8, MVT::v8i16})
131 setOperationAction(Op, T, Legal);
132
133 // We have custom shuffle lowering to expose the shuffle mask
134 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
135 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom);
136 if (Subtarget->hasUnimplementedSIMD128())
137 for (auto T: {MVT::v2i64, MVT::v2f64})
138 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom);
139
140 // Custom lowering since wasm shifts must have a scalar shift amount
141 for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL}) {
142 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
143 setOperationAction(Op, T, Custom);
144 if (Subtarget->hasUnimplementedSIMD128())
145 setOperationAction(Op, MVT::v2i64, Custom);
125146 }
126 if (Subtarget->hasSIMD128()) {
127 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) {
128 setOperationAction(Op, T, Expand);
129 }
130 if (Subtarget->hasUnimplementedSIMD128()) {
131 setOperationAction(Op, MVT::v2i64, Expand);
132 }
147
148 // Custom lower lane accesses to expand out variable indices
149 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) {
150 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
151 setOperationAction(Op, T, Custom);
152 if (Subtarget->hasUnimplementedSIMD128())
153 for (auto T : {MVT::v2i64, MVT::v2f64})
154 setOperationAction(Op, T, Custom);
133155 }
134 }
135
136 // There is no i64x2.mul instruction
137 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
138
139 // We have custom shuffle lowering to expose the shuffle mask
140 if (Subtarget->hasSIMD128()) {
141 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) {
142 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom);
143 }
144 if (Subtarget->hasUnimplementedSIMD128()) {
145 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
146 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
147 }
148 }
149
150 // Custom lowering since wasm shifts must have a scalar shift amount
151 if (Subtarget->hasSIMD128()) {
152 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
153 for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL})
154 setOperationAction(Op, T, Custom);
155 if (Subtarget->hasUnimplementedSIMD128())
156 for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL})
157 setOperationAction(Op, MVT::v2i64, Custom);
158 }
159
160 // There are no select instructions for vectors
161 if (Subtarget->hasSIMD128())
156
157 // There is no i64x2.mul instruction
158 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
159
160 // There are no vector select instructions
162161 for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT}) {
163162 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
164163 setOperationAction(Op, T, Expand);
166165 for (auto T : {MVT::v2i64, MVT::v2f64})
167166 setOperationAction(Op, T, Expand);
168167 }
168
169 // Expand additional SIMD ops that V8 hasn't implemented yet
170 if (!Subtarget->hasUnimplementedSIMD128()) {
171 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
172 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
173 }
174 }
169175
170176 // As a special case, these operators use the type to mean the type to
171177 // sign-extend from.
214220 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
215221 setLoadExtAction(Ext, T, MemT, Expand);
216222 }
217 }
218 }
219 }
220
221 // Expand additional SIMD ops that V8 hasn't implemented yet
222 if (Subtarget->hasSIMD128() && !Subtarget->hasUnimplementedSIMD128()) {
223 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
224 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
225 }
226
227 // Custom lower lane accesses to expand out variable indices
228 if (Subtarget->hasSIMD128()) {
229 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) {
230 setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom);
231 setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom);
232 }
233 if (Subtarget->hasUnimplementedSIMD128()) {
234 for (auto T : {MVT::v2i64, MVT::v2f64}) {
235 setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom);
236 setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom);
237223 }
238224 }
239225 }