llvm.org GIT mirror llvm / 71fbed4
Tweak MachineLICM heuristics for cheap instructions. Allow cheap instructions to be hoisted if they are register pressure neutral or better. This happens if the instruction is the last loop use of another virtual register. Only expensive instructions are allowed to increase loop register pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154455 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
1 changed file(s) with 97 addition(s) and 77 deletion(s). Raw diff Collapse all Expand all
204204 /// CanCauseHighRegPressure - Visit BBs from header to current BB,
205205 /// check if hoisting an instruction of the given cost matrix can cause high
206206 /// register pressure.
207 bool CanCauseHighRegPressure(DenseMap &Cost);
207 bool CanCauseHighRegPressure(DenseMap &Cost, bool Cheap);
208208
209209 /// UpdateBackTraceRegPressure - Traverse the back trace from header to
210210 /// the current block and update their register pressures to reflect the
10661066 /// CanCauseHighRegPressure - Visit BBs from header to current BB, check
10671067 /// if hoisting an instruction of the given cost matrix can cause high
10681068 /// register pressure.
1069 bool MachineLICM::CanCauseHighRegPressure(DenseMap &Cost) {
1069 bool MachineLICM::CanCauseHighRegPressure(DenseMap &Cost,
1070 bool CheapInstr) {
10701071 for (DenseMap::iterator CI = Cost.begin(), CE = Cost.end();
10711072 CI != CE; ++CI) {
10721073 if (CI->second <= 0)
10751076 unsigned RCId = CI->first;
10761077 unsigned Limit = RegLimit[RCId];
10771078 int Cost = CI->second;
1079
1080 // Don't hoist cheap instructions if they would increase register pressure,
1081 // even if we're under the limit.
1082 if (CheapInstr)
1083 return true;
1084
10781085 for (unsigned i = BackTrace.size(); i != 0; --i) {
10791086 SmallVector &RP = BackTrace[i-1];
10801087 if (RP[RCId] + Cost >= Limit)
11371144 if (MI.isImplicitDef())
11381145 return true;
11391146
1140 // If the instruction is cheap, only hoist if it is re-materilizable. LICM
1141 // will increase register pressure. It's probably not worth it if the
1142 // instruction is cheap.
1143 // Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting
1144 // these tend to help performance in low register pressure situation. The
1145 // trade off is it may cause spill in high pressure situation. It will end up
1146 // adding a store in the loop preheader. But the reload is no more expensive.
1147 // The side benefit is these loads are frequently CSE'ed.
1148 if (IsCheapInstruction(MI)) {
1149 if (!TII->isTriviallyReMaterializable(&MI, AA))
1150 return false;
1151 } else {
1152 // Estimate register pressure to determine whether to LICM the instruction.
1153 // In low register pressure situation, we can be more aggressive about
1154 // hoisting. Also, favors hoisting long latency instructions even in
1155 // moderately high pressure situation.
1156 // FIXME: If there are long latency loop-invariant instructions inside the
1157 // loop at this point, why didn't the optimizer's LICM hoist them?
1158 DenseMap Cost;
1159 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
1160 const MachineOperand &MO = MI.getOperand(i);
1161 if (!MO.isReg() || MO.isImplicit())
1162 continue;
1163 unsigned Reg = MO.getReg();
1164 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1165 continue;
1166
1167 unsigned RCId, RCCost;
1168 getRegisterClassIDAndCost(&MI, Reg, i, RCId, RCCost);
1169 if (MO.isDef()) {
1170 if (HasHighOperandLatency(MI, i, Reg)) {
1171 ++NumHighLatency;
1172 return true;
1173 }
1174
1175 DenseMap::iterator CI = Cost.find(RCId);
1176 if (CI != Cost.end())
1177 CI->second += RCCost;
1178 else
1179 Cost.insert(std::make_pair(RCId, RCCost));
1180 } else if (isOperandKill(MO, MRI)) {
1181 // Is a virtual register use is a kill, hoisting it out of the loop
1182 // may actually reduce register pressure or be register pressure
1183 // neutral.
1184 DenseMap::iterator CI = Cost.find(RCId);
1185 if (CI != Cost.end())
1186 CI->second -= RCCost;
1187 else
1188 Cost.insert(std::make_pair(RCId, -RCCost));
1147 // Besides removing computation from the loop, hoisting an instruction has
1148 // these effects:
1149 //
1150 // - The value defined by the instruction becomes live across the entire
1151 // loop. This increases register pressure in the loop.
1152 //
1153 // - If the value is used by a PHI in the loop, a copy will be required for
1154 // lowering the PHI after extending the live range.
1155 //
1156 // - When hoisting the last use of a value in the loop, that value no longer
1157 // needs to be live in the loop. This lowers register pressure in the loop.
1158
1159 bool CheapInstr = IsCheapInstruction(MI);
1160 bool CreatesCopy = HasLoopPHIUse(&MI);
1161
1162 // Don't hoist a cheap instruction if it would create a copy in the loop.
1163 if (CheapInstr && CreatesCopy) {
1164 DEBUG(dbgs() << "Won't hoist cheap instr with loop PHI use: " << MI);
1165 return false;
1166 }
1167
1168 // Rematerializable instructions should always be hoisted since the register
1169 // allocator can just pull them down again when needed.
1170 if (TII->isTriviallyReMaterializable(&MI, AA))
1171 return true;
1172
1173 // Estimate register pressure to determine whether to LICM the instruction.
1174 // In low register pressure situation, we can be more aggressive about
1175 // hoisting. Also, favors hoisting long latency instructions even in
1176 // moderately high pressure situation.
1177 // Cheap instructions will only be hoisted if they don't increase register
1178 // pressure at all.
1179 // FIXME: If there are long latency loop-invariant instructions inside the
1180 // loop at this point, why didn't the optimizer's LICM hoist them?
1181 DenseMap Cost;
1182 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
1183 const MachineOperand &MO = MI.getOperand(i);
1184 if (!MO.isReg() || MO.isImplicit())
1185 continue;
1186 unsigned Reg = MO.getReg();
1187 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1188 continue;
1189
1190 unsigned RCId, RCCost;
1191 getRegisterClassIDAndCost(&MI, Reg, i, RCId, RCCost);
1192 if (MO.isDef()) {
1193 if (HasHighOperandLatency(MI, i, Reg)) {
1194 DEBUG(dbgs() << "Hoist High Latency: " << MI);
1195 ++NumHighLatency;
1196 return true;
11891197 }
1190 }
1191
1192 // Visit BBs from header to current BB, if hoisting this doesn't cause
1193 // high register pressure, then it's safe to proceed.
1194 if (!CanCauseHighRegPressure(Cost)) {
1195 ++NumLowRP;
1196 return true;
1197 }
1198
1199 // Do not "speculate" in high register pressure situation. If an
1200 // instruction is not guaranteed to be executed in the loop, it's best to be
1201 // conservative.
1202 if (AvoidSpeculation &&
1203 (!IsGuaranteedToExecute(MI.getParent()) && !MayCSE(&MI)))
1204 return false;
1205
1206 // High register pressure situation, only hoist if the instruction is going
1207 // to be remat'ed.
1208 if (!TII->isTriviallyReMaterializable(&MI, AA) &&
1209 !MI.isInvariantLoad(AA))
1210 return false;
1211 }
1212
1213 // If result(s) of this instruction is used by PHIs inside the loop, then
1214 // don't hoist it because it will introduce an extra copy.
1215 if (HasLoopPHIUse(&MI))
1198 Cost[RCId] += RCCost;
1199 } else if (isOperandKill(MO, MRI)) {
1200 // Is a virtual register use is a kill, hoisting it out of the loop
1201 // may actually reduce register pressure or be register pressure
1202 // neutral.
1203 Cost[RCId] -= RCCost;
1204 }
1205 }
1206
1207 // Visit BBs from header to current BB, if hoisting this doesn't cause
1208 // high register pressure, then it's safe to proceed.
1209 if (!CanCauseHighRegPressure(Cost, CheapInstr)) {
1210 DEBUG(dbgs() << "Hoist non-reg-pressure: " << MI);
1211 ++NumLowRP;
1212 return true;
1213 }
1214
1215 // Don't risk increasing register pressure if it would create copies.
1216 if (CreatesCopy) {
1217 DEBUG(dbgs() << "Won't hoist instr with loop PHI use: " << MI);
12161218 return false;
1219 }
1220
1221 // Do not "speculate" in high register pressure situation. If an
1222 // instruction is not guaranteed to be executed in the loop, it's best to be
1223 // conservative.
1224 if (AvoidSpeculation &&
1225 (!IsGuaranteedToExecute(MI.getParent()) && !MayCSE(&MI))) {
1226 DEBUG(dbgs() << "Won't speculate: " << MI);
1227 return false;
1228 }
1229
1230 // High register pressure situation, only hoist if the instruction is going
1231 // to be remat'ed.
1232 if (!TII->isTriviallyReMaterializable(&MI, AA) &&
1233 !MI.isInvariantLoad(AA)) {
1234 DEBUG(dbgs() << "Can't remat / high reg-pressure: " << MI);
1235 return false;
1236 }
12171237
12181238 return true;
12191239 }