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Merging r259059: ------------------------------------------------------------------------ r259059 | thomas.stellard | 2016-01-28 09:13:44 -0800 (Thu, 28 Jan 2016) | 14 lines AMDGPU: waitcnt operand fixes Summary: Allow lgkmcnt up to 0xF (hardware allows that). Fix mask for ExpCnt in AMDGPUInstPrinter. Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16314 Patch by: Nikolay Haustov ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@271590 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 years ago
4 changed file(s) with 16 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
15151515 CntMask = 0x7;
15161516 CntShift = 4;
15171517 } else if (CntName == "lgkmcnt") {
1518 CntMask = 0x7;
1518 CntMask = 0xf;
15191519 CntShift = 8;
15201520 } else {
15211521 return true;
15311531 // Disable all counters by default.
15321532 // vmcnt [3:0]
15331533 // expcnt [6:4]
1534 // lgkmcnt [10:8]
1535 int64_t CntVal = 0x77f;
1534 // lgkmcnt [11:8]
1535 int64_t CntVal = 0xf7f;
15361536 SMLoc S = Parser.getTok().getLoc();
15371537
15381538 switch(getLexer().getKind()) {
615615
616616 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
617617 raw_ostream &O) {
618 // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
619 // SIInsertWaits.cpp bits usage does not match ISA docs description but it
620 // works so it might be a misprint in docs.
621618 unsigned SImm16 = MI->getOperand(OpNo).getImm();
622619 unsigned Vmcnt = SImm16 & 0xF;
623 unsigned Expcnt = (SImm16 >> 4) & 0xF;
620 unsigned Expcnt = (SImm16 >> 4) & 0x7;
624621 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
625622
626623 bool NeedSpace = false;
637634 NeedSpace = true;
638635 }
639636
640 if (Lgkmcnt != 0x7) {
637 if (Lgkmcnt != 0xF) {
641638 if (NeedSpace)
642639 O << ' ';
643640 O << "lgkmcnt(" << Lgkmcnt << ')';
137137
138138 char SIInsertWaits::ID = 0;
139139
140 const Counters SIInsertWaits::WaitCounts = { { 15, 7, 7 } };
140 const Counters SIInsertWaits::WaitCounts = { { 15, 7, 15 } };
141141 const Counters SIInsertWaits::ZeroCounts = { { 0, 0, 0 } };
142142
143143 FunctionPass *llvm::createSIInsertWaits(TargetMachine &tm) {
378378 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
379379 .addImm((Counts.Named.VM & 0xF) |
380380 ((Counts.Named.EXP & 0x7) << 4) |
381 ((Counts.Named.LGKM & 0x7) << 8));
381 ((Counts.Named.LGKM & 0xF) << 8));
382382
383383 LastOpcodeType = OTHER;
384384 LastInstWritesM0 = false;
3939 // CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
4040
4141 s_waitcnt vmcnt(1)
42 // CHECK: s_waitcnt vmcnt(1) ; encoding: [0x71,0x07,0x8c,0xbf]
42 // CHECK: s_waitcnt vmcnt(1) ; encoding: [0x71,0x0f,0x8c,0xbf]
43
44 s_waitcnt vmcnt(9)
45 // CHECK: s_waitcnt vmcnt(9) ; encoding: [0x79,0x0f,0x8c,0xbf]
4346
4447 s_waitcnt expcnt(2)
45 // CHECK: s_waitcnt expcnt(2) ; encoding: [0x2f,0x07,0x8c,0xbf]
48 // CHECK: s_waitcnt expcnt(2) ; encoding: [0x2f,0x0f,0x8c,0xbf]
4649
4750 s_waitcnt lgkmcnt(3)
4851 // CHECK: s_waitcnt lgkmcnt(3) ; encoding: [0x7f,0x03,0x8c,0xbf]
4952
53 s_waitcnt lgkmcnt(9)
54 // CHECK: s_waitcnt lgkmcnt(9) ; encoding: [0x7f,0x09,0x8c,0xbf]
55
5056 s_waitcnt vmcnt(0), expcnt(0)
51 // CHECK: s_waitcnt vmcnt(0) expcnt(0) ; encoding: [0x00,0x07,0x8c,0xbf]
57 // CHECK: s_waitcnt vmcnt(0) expcnt(0) ; encoding: [0x00,0x0f,0x8c,0xbf]
5258
5359
5460 s_sethalt 9 // CHECK: s_sethalt 9 ; encoding: [0x09,0x00,0x8d,0xbf]