llvm.org GIT mirror llvm / 7142f87
- If fp (r7) is used to reference stack objects, use [r, r] address mode. - If there is a dynamic alloca, in the epilogue, restore the value of sp using r7 - offset. - Other bug fixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33997 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
1 changed file(s) with 67 addition(s) and 28 deletion(s). Raw diff Collapse all Expand all
358358 return NumMIs;
359359 }
360360
361 /// emitLoadConstPool - Emits a load from constpool to materialize NumBytes
362 /// immediate.
363 static void emitLoadConstPool(MachineBasicBlock &MBB,
364 MachineBasicBlock::iterator &MBBI,
365 unsigned DestReg, int NumBytes,
366 const TargetInstrInfo &TII) {
367 MachineFunction &MF = *MBB.getParent();
368 MachineConstantPool *ConstantPool = MF.getConstantPool();
369 Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes);
370 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
371 BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), DestReg).addConstantPoolIndex(Idx);
372 }
373
361374 /// emitThumbRegPlusConstPool - Emits a series of instructions to materialize
362375 /// a destreg = basereg + immediate in Thumb code. Load the immediate from a
363376 /// constpool entry.
367380 unsigned DestReg, unsigned BaseReg,
368381 int NumBytes, bool CanChangeCC,
369382 const TargetInstrInfo &TII) {
370 MachineFunction &MF = *MBB.getParent();
371 MachineConstantPool *ConstantPool = MF.getConstantPool();
372 bool isHigh = !isLowRegister(DestReg) || !isLowRegister(BaseReg);
383 bool isHigh = !isLowRegister(DestReg) ||
384 (BaseReg != 0 && !isLowRegister(BaseReg));
373385 bool isSub = false;
374386 // Subtract doesn't have high register version. Load the negative value
375387 // if either base or dest register is a high register. Also, if do not
388400
389401 if (NumBytes <= 255 && NumBytes >= 0)
390402 BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes);
391 else {
392 // Load the constant.
393 Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes);
394 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
395 BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), LdReg).addConstantPoolIndex(Idx);
396 }
403 else
404 emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII);
405
397406 // Emit add / sub.
398407 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
399408 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
720729 case ARMII::AddrModeTs: {
721730 ImmIdx = i+1;
722731 InstrOffs = MI.getOperand(ImmIdx).getImm();
723 NumBits = isSub ? 3 : ((FrameReg == ARM::SP) ? 8 : 5);
724 Scale = isSub ? 1 : 4;
732 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
733 Scale = 4;
725734 break;
726735 }
727736 default:
753762 // If this is a thumb spill / restore, we will be using a constpool load to
754763 // materialize the offset.
755764 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
756 if (AddrMode == ARMII::AddrModeTs || !isThumSpillRestore) {
765 if (AddrMode == ARMII::AddrModeTs && !isThumSpillRestore) {
757766 if (AddrMode == ARMII::AddrModeTs) {
758767 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
759768 // a different base register.
778787 if (TII.isLoad(Opcode)) {
779788 // Use the destination register to materialize sp + offset.
780789 unsigned TmpReg = MI.getOperand(0).getReg();
781 if (Opcode == ARM::tRestore)
782 emitThumbRegPlusConstPool(MBB, II, TmpReg, FrameReg, Offset, false, TII);
783 else
790 bool UseRR = false;
791 if (Opcode == ARM::tRestore) {
792 if (FrameReg == ARM::SP)
793 emitThumbRegPlusConstPool(MBB, II, TmpReg, FrameReg,Offset,false,TII);
794 else {
795 emitLoadConstPool(MBB, II, TmpReg, Offset, TII);
796 UseRR = true;
797 }
798 } else
784799 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
785800 MI.setInstrDescriptor(TII.get(ARM::tLDR));
786801 MI.getOperand(i).ChangeToRegister(TmpReg, false);
802 if (UseRR)
803 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
804 else
787805 MI.addRegOperand(0, false); // tLDR has an extra register operand.
788806 } else if (TII.isStore(Opcode)) {
789807 // FIXME! This is horrific!!! We need register scavenging.
796814 // r2 = r12
797815 unsigned ValReg = MI.getOperand(0).getReg();
798816 unsigned TmpReg = ARM::R3;
817 bool UseRR = false;
799818 if (ValReg == ARM::R3) {
800819 BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R2);
801820 TmpReg = ARM::R2;
802821 }
803 if (Opcode == ARM::tSpill)
804 emitThumbRegPlusConstPool(MBB, II, TmpReg, FrameReg, Offset, false, TII);
805 else
822 if (Opcode == ARM::tSpill) {
823 if (FrameReg == ARM::SP)
824 emitThumbRegPlusConstPool(MBB, II, TmpReg, FrameReg,Offset,false,TII);
825 else {
826 emitLoadConstPool(MBB, II, TmpReg, Offset, TII);
827 UseRR = true;
828 }
829 } else
806830 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
807831 MI.setInstrDescriptor(TII.get(ARM::tSTR));
808832 MI.getOperand(i).ChangeToRegister(TmpReg, false);
809 MI.addRegOperand(0, false); // tSTR has an extra register operand.
810 if (ValReg == ARM::R3)
811 BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R2).addReg(ARM::R12);
833 if (UseRR)
834 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
835 else
836 MI.addRegOperand(0, false); // tSTR has an extra register operand.
837 if (ValReg == ARM::R3) {
838 MachineBasicBlock::iterator NII = next(II);
839 BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R2).addReg(ARM::R12);
840 }
812841 } else
813842 assert(false && "Unexpected opcode!");
814843 } else {
11511180 AFI->getGPRCalleeSavedArea2Size() +
11521181 AFI->getDPRCalleeSavedAreaSize());
11531182 if (isThumb) {
1154 if (MBBI->getOpcode() == ARM::tBX_RET &&
1155 &MBB.front() != MBBI &&
1156 prior(MBBI)->getOpcode() == ARM::tPOP) {
1157 MachineBasicBlock::iterator PMBBI = prior(MBBI);
1158 emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII);
1159 } else
1160 emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII);
1183 if (hasFP(MF)) {
1184 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1185 // Reset SP based on frame pointer only if the stack frame extends beyond
1186 // frame pointer stack slot or target is ELF and the function has FP.
1187 if (NumBytes)
1188 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII);
1189 else
1190 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::SP).addReg(FramePtr);
1191 } else {
1192 if (MBBI->getOpcode() == ARM::tBX_RET &&
1193 &MBB.front() != MBBI &&
1194 prior(MBBI)->getOpcode() == ARM::tPOP) {
1195 MachineBasicBlock::iterator PMBBI = prior(MBBI);
1196 emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII);
1197 } else
1198 emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII);
1199 }
11611200 } else {
11621201 // Darwin ABI requires FP to point to the stack slot that contains the
11631202 // previous FP.