llvm.org GIT mirror llvm / 7137d0d
AMDGPU: R600 code splitting cleanup Move a few functions only used by R600 to R600 specific code, fix header macros to stop using R600, mark classes as final. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263204 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 4 years ago
32 changed file(s) with 93 addition(s) and 105 deletion(s). Raw diff Collapse all Expand all
77 /// \file
88 //===----------------------------------------------------------------------===//
99
10 #ifndef LLVM_LIB_TARGET_R600_AMDGPU_H
11 #define LLVM_LIB_TARGET_R600_AMDGPU_H
10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
1212
1313 #include "llvm/Support/TargetRegistry.h"
1414 #include "llvm/Target/TargetMachine.h"
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #ifndef LLVM_LIB_TARGET_R600_AMDGPUASMPRINTER_H
15 #define LLVM_LIB_TARGET_R600_AMDGPUASMPRINTER_H
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUASMPRINTER_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUASMPRINTER_H
1616
1717 #include "llvm/CodeGen/AsmPrinter.h"
1818 #include
1919
2020 namespace llvm {
2121
22 class AMDGPUAsmPrinter : public AsmPrinter {
22 class AMDGPUAsmPrinter final : public AsmPrinter {
2323 private:
2424 struct SIProgramInfo {
2525 SIProgramInfo() :
27072707 Ins[i].OrigArgIndex, Ins[i].PartOffset);
27082708 OrigIns.push_back(Arg);
27092709 }
2710 }
2711
2712 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2713 if (ConstantFPSDNode * CFP = dyn_cast(Op)) {
2714 return CFP->isExactlyValue(1.0);
2715 }
2716 return isAllOnesConstant(Op);
2717 }
2718
2719 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2720 if (ConstantFPSDNode * CFP = dyn_cast(Op)) {
2721 return CFP->getValueAPF().isZero();
2722 }
2723 return isNullConstant(Op);
27242710 }
27252711
27262712 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1212 //
1313 //===----------------------------------------------------------------------===//
1414
15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
1717
1818 #include "llvm/Target/TargetLowering.h"
1919
105105 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
106106 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
107107 SmallVectorImpl &Results) const;
108 bool isHWTrueValue(SDValue Op) const;
109 bool isHWFalseValue(SDValue Op) const;
110
111108 /// The SelectionDAGBuilder will automatically promote function arguments
112109 /// with illegal types. However, this does not work for the AMDGPU targets
113110 /// since the function arguments are stored in memory as these illegal types.
192189 unsigned &RefinementSteps) const override;
193190
194191 virtual SDNode *PostISelFolding(MachineSDNode *N,
195 SelectionDAG &DAG) const {
196 return N;
197 }
192 SelectionDAG &DAG) const = 0;
198193
199194 /// \brief Determine which of the bits specified in \p Mask are known to be
200195 /// either zero or one and return them in the \p KnownZero and \p KnownOne
1212 //
1313 //===----------------------------------------------------------------------===//
1414
15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUINSTRINFO_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUINSTRINFO_H
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
1717
1818 #include "AMDGPURegisterInfo.h"
1919 #include "llvm/Target/TargetInstrInfo.h"
20 #include
2120
2221 #define GET_INSTRINFO_HEADER
2322 #define GET_INSTRINFO_ENUM
1010 /// \brief Interface for the AMDGPU Implementation of the Intrinsic Info class.
1111 //
1212 //===-----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_R600_AMDGPUINTRINSICINFO_H
14 #define LLVM_LIB_TARGET_R600_AMDGPUINTRINSICINFO_H
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINTRINSICINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINTRINSICINFO_H
1515
1616 #include "llvm/IR/Intrinsics.h"
1717 #include "llvm/Target/TargetIntrinsicInfo.h"
3030
3131 } // end namespace AMDGPUIntrinsic
3232
33 class AMDGPUIntrinsicInfo : public TargetIntrinsicInfo {
33 class AMDGPUIntrinsicInfo final : public TargetIntrinsicInfo {
3434 public:
3535 AMDGPUIntrinsicInfo();
3636 std::string getName(unsigned IntrId, Type **Tys = nullptr,
77 /// \file
88 //===----------------------------------------------------------------------===//
99
10 #ifndef LLVM_LIB_TARGET_R600_AMDGPUMCINSTLOWER_H
11 #define LLVM_LIB_TARGET_R600_AMDGPUMCINSTLOWER_H
10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMCINSTLOWER_H
11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMCINSTLOWER_H
1212
1313 namespace llvm {
1414
None //===-- R600MachineFunctionInfo.h - R600 Machine Function Info ----*- C++ -*-=//
0 //===-- AMDGPUMachineFunctionInfo.h -------------------------------*- C++ -*-=//
11 //
22 // The LLVM Compiler Infrastructure
33 //
55 // License. See LICENSE.TXT for details.
66 //
77 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //===----------------------------------------------------------------------===//
118
12 #ifndef LLVM_LIB_TARGET_R600_AMDGPUMACHINEFUNCTION_H
13 #define LLVM_LIB_TARGET_R600_AMDGPUMACHINEFUNCTION_H
9 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINEFUNCTION_H
10 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINEFUNCTION_H
1411
1512 #include "llvm/CodeGen/MachineFunction.h"
1613 #include
1212 //
1313 //===----------------------------------------------------------------------===//
1414
15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUREGISTERINFO_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUREGISTERINFO_H
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H
1717
1818 #include "llvm/ADT/BitVector.h"
1919 #include "llvm/Target/TargetRegisterInfo.h"
184184 bool addGCPasses() override;
185185 };
186186
187 class R600PassConfig : public AMDGPUPassConfig {
187 class R600PassConfig final : public AMDGPUPassConfig {
188188 public:
189189 R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
190190 : AMDGPUPassConfig(TM, PM) { }
195195 void addPreEmitPass() override;
196196 };
197197
198 class GCNPassConfig : public AMDGPUPassConfig {
198 class GCNPassConfig final : public AMDGPUPassConfig {
199199 public:
200200 GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
201201 : AMDGPUPassConfig(TM, PM) { }
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #ifndef LLVM_LIB_TARGET_R600_AMDGPUTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_R600_AMDGPUTARGETMACHINE_H
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
1616
1717 #include "AMDGPUFrameLowering.h"
1818 #include "AMDGPUInstrInfo.h"
5959 // R600 Target Machine (R600 -> Cayman)
6060 //===----------------------------------------------------------------------===//
6161
62 class R600TargetMachine : public AMDGPUTargetMachine {
62 class R600TargetMachine final : public AMDGPUTargetMachine {
6363
6464 public:
6565 R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
7373 // GCN Target Machine (SI+)
7474 //===----------------------------------------------------------------------===//
7575
76 class GCNTargetMachine : public AMDGPUTargetMachine {
76 class GCNTargetMachine final : public AMDGPUTargetMachine {
7777
7878 public:
7979 GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
1313 ///
1414 //===----------------------------------------------------------------------===//
1515
16 #ifndef LLVM_LIB_TARGET_R600_AMDGPUTARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_R600_AMDGPUTARGETTRANSFORMINFO_H
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
1818
1919 #include "AMDGPU.h"
2020 #include "AMDGPUTargetMachine.h"
2424
2525 namespace llvm {
2626
27 class AMDGPUTTIImpl : public BasicTTIImplBase {
27 class AMDGPUTTIImpl final : public BasicTTIImplBase {
2828 typedef BasicTTIImplBase BaseT;
2929 typedef TargetTransformInfo TTI;
3030 friend BaseT;
99 /// \file
1010 //===----------------------------------------------------------------------===//
1111
12 #ifndef LLVM_LIB_TARGET_R600_INSTPRINTER_AMDGPUINSTPRINTER_H
13 #define LLVM_LIB_TARGET_R600_INSTPRINTER_AMDGPUINSTPRINTER_H
12 #ifndef LLVM_LIB_TARGET_AMDGPU_INSTPRINTER_AMDGPUINSTPRINTER_H
13 #define LLVM_LIB_TARGET_AMDGPU_INSTPRINTER_AMDGPUINSTPRINTER_H
1414
1515 #include "llvm/MC/MCInstPrinter.h"
1616
None //===-------- AMDGPUELFStreamer.h - ELF Object Output ---------------------===//
0 //===-------- AMDGPUELFStreamer.h - ELF Object Output -----------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
66 //
77 //===----------------------------------------------------------------------===//
88
9 #ifndef LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUFIXUPKINDS_H
10 #define LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUFIXUPKINDS_H
9 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUFIXUPKINDS_H
10 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUFIXUPKINDS_H
1111
1212 #include "llvm/MC/MCFixup.h"
1313
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #ifndef LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCASMINFO_H
14 #define LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCASMINFO_H
13 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCASMINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCASMINFO_H
1515
1616 #include "llvm/MC/MCAsmInfoELF.h"
1717 namespace llvm {
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #ifndef LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCCODEEMITTER_H
15 #define LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCCODEEMITTER_H
14 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCCODEEMITTER_H
15 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCCODEEMITTER_H
1616
1717 #include "llvm/MC/MCCodeEmitter.h"
1818 #include "llvm/Support/raw_ostream.h"
1212 //===----------------------------------------------------------------------===//
1313 //
1414
15 #ifndef LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCTARGETDESC_H
16 #define LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCTARGETDESC_H
15 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
16 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
1717
1818 #include "llvm/Support/DataTypes.h"
1919 #include "llvm/ADT/StringRef.h"
66 //
77 //===----------------------------------------------------------------------===//
88
9 #ifndef LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUTARGETSTREAMER_H
10 #define LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUTARGETSTREAMER_H
9 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUTARGETSTREAMER_H
10 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUTARGETSTREAMER_H
1111
1212 #include "AMDKernelCodeT.h"
1313 #include "llvm/MC/MCStreamer.h"
14 #include "llvm/MC/MCSymbol.h"
15 #include "llvm/Support/Debug.h"
14
1615 namespace llvm {
1716
1817 class MCELFStreamer;
18 class MCSymbol;
1919
2020 class AMDGPUTargetStreamer : public MCTargetStreamer {
2121 public:
77 /// \file
88 //===----------------------------------------------------------------------===//
99
10 #ifndef LLVM_LIB_TARGET_R600_R600DEFINES_H
11 #define LLVM_LIB_TARGET_R600_R600DEFINES_H
10 #ifndef LLVM_LIB_TARGET_AMDGPU_R600DEFINES_H
11 #define LLVM_LIB_TARGET_AMDGPU_R600DEFINES_H
1212
1313 #include "llvm/MC/MCRegisterInfo.h"
1414
10661066 }
10671067 }
10681068
1069 bool R600TargetLowering::isHWTrueValue(SDValue Op) const {
1070 if (ConstantFPSDNode * CFP = dyn_cast(Op)) {
1071 return CFP->isExactlyValue(1.0);
1072 }
1073 return isAllOnesConstant(Op);
1074 }
1075
1076 bool R600TargetLowering::isHWFalseValue(SDValue Op) const {
1077 if (ConstantFPSDNode * CFP = dyn_cast(Op)) {
1078 return CFP->getValueAPF().isZero();
1079 }
1080 return isNullConstant(Op);
1081 }
1082
10691083 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
10701084 SDLoc DL(Op);
10711085 EVT VT = Op.getValueType();
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #ifndef LLVM_LIB_TARGET_R600_R600ISELLOWERING_H
15 #define LLVM_LIB_TARGET_R600_R600ISELLOWERING_H
14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
1616
1717 #include "AMDGPUISelLowering.h"
1818
2020
2121 class R600InstrInfo;
2222
23 class R600TargetLowering : public AMDGPUTargetLowering {
23 class R600TargetLowering final : public AMDGPUTargetLowering {
2424 public:
2525 R600TargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI);
2626 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI,
8282 void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
8383 unsigned &Channel, unsigned &PtrIncr) const;
8484 bool isZero(SDValue Op) const;
85 bool isHWTrueValue(SDValue Op) const;
86 bool isHWFalseValue(SDValue Op) const;
87
8588 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
8689 };
8790
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #ifndef LLVM_LIB_TARGET_R600_R600INSTRINFO_H
15 #define LLVM_LIB_TARGET_R600_R600INSTRINFO_H
14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
1616
1717 #include "AMDGPUInstrInfo.h"
1818 #include "R600Defines.h"
2020 #include
2121
2222 namespace llvm {
23
2423 class AMDGPUTargetMachine;
2524 class DFAPacketizer;
26 class ScheduleDAG;
2725 class MachineFunction;
2826 class MachineInstr;
2927 class MachineInstrBuilder;
3028
31 class R600InstrInfo : public AMDGPUInstrInfo {
29 class R600InstrInfo final : public AMDGPUInstrInfo {
3230 private:
3331 const R600RegisterInfo RI;
3432
99 /// \file
1010 //===----------------------------------------------------------------------===//
1111
12 #ifndef LLVM_LIB_TARGET_R600_R600MACHINEFUNCTIONINFO_H
13 #define LLVM_LIB_TARGET_R600_R600MACHINEFUNCTIONINFO_H
12 #ifndef LLVM_LIB_TARGET_AMDGPU_R600MACHINEFUNCTIONINFO_H
13 #define LLVM_LIB_TARGET_AMDGPU_R600MACHINEFUNCTIONINFO_H
1414
1515 #include "AMDGPUMachineFunction.h"
1616 #include "llvm/ADT/BitVector.h"
1919
2020 namespace llvm {
2121
22 class R600MachineFunctionInfo : public AMDGPUMachineFunction {
22 class R600MachineFunctionInfo final : public AMDGPUMachineFunction {
2323 void anchor() override;
2424 public:
2525 R600MachineFunctionInfo(const MachineFunction &MF);
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #ifndef LLVM_LIB_TARGET_R600_R600MACHINESCHEDULER_H
15 #define LLVM_LIB_TARGET_R600_R600MACHINESCHEDULER_H
14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
1616
1717 #include "R600InstrInfo.h"
18 #include "llvm/ADT/PriorityQueue.h"
1918 #include "llvm/CodeGen/MachineScheduler.h"
20 #include "llvm/Support/Debug.h"
2119
2220 using namespace llvm;
2321
2422 namespace llvm {
2523
26 class R600SchedStrategy : public MachineSchedStrategy {
24 class R600SchedStrategy final : public MachineSchedStrategy {
2725
2826 const ScheduleDAGMILive *DAG;
2927 const R600InstrInfo *TII;
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #ifndef LLVM_LIB_TARGET_R600_R600REGISTERINFO_H
15 #define LLVM_LIB_TARGET_R600_R600REGISTERINFO_H
14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
1616
1717 #include "AMDGPURegisterInfo.h"
1818
2020
2121 class AMDGPUSubtarget;
2222
23 struct R600RegisterInfo : public AMDGPURegisterInfo {
23 struct R600RegisterInfo final : public AMDGPURegisterInfo {
2424 RegClassWeight RCW;
2525
2626 R600RegisterInfo();
99
1010 #include "llvm/MC/MCInstrDesc.h"
1111
12 #ifndef LLVM_LIB_TARGET_R600_SIDEFINES_H
13 #define LLVM_LIB_TARGET_R600_SIDEFINES_H
12 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
13 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
1414
1515 namespace SIInstrFlags {
1616 // This needs to be kept in sync with the field bits in InstSI.
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #ifndef LLVM_LIB_TARGET_R600_SIISELLOWERING_H
15 #define LLVM_LIB_TARGET_R600_SIISELLOWERING_H
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
1616
1717 #include "AMDGPUISelLowering.h"
1818 #include "SIInstrInfo.h"
1919
2020 namespace llvm {
2121
22 class SITargetLowering : public AMDGPUTargetLowering {
22 class SITargetLowering final : public AMDGPUTargetLowering {
2323 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
2424 SDValue Chain, unsigned Offset, bool Signed) const;
2525 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
1212 //===----------------------------------------------------------------------===//
1313
1414
15 #ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
16 #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
1717
1818 #include "AMDGPUInstrInfo.h"
1919 #include "SIDefines.h"
2121
2222 namespace llvm {
2323
24 class SIInstrInfo : public AMDGPUInstrInfo {
24 class SIInstrInfo final : public AMDGPUInstrInfo {
2525 private:
2626 const SIRegisterInfo RI;
2727
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13
14 #ifndef LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
15 #define LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
1615
1716 #include "AMDGPUMachineFunction.h"
1817 #include "SIRegisterInfo.h"
2423
2524 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
2625 /// tells the hardware which interpolation parameters to load.
27 class SIMachineFunctionInfo : public AMDGPUMachineFunction {
26 class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
2827 // FIXME: This should be removed and getPreloadedValue moved here.
2928 friend struct SIRegisterInfo;
3029 void anchor() override;
321320
322321 } // End namespace llvm
323322
324
325323 #endif
417417 SISchedulerBlockSchedulerVariant ScheduleVariant);
418418 };
419419
420 class SIScheduleDAGMI : public ScheduleDAGMILive {
420 class SIScheduleDAGMI final : public ScheduleDAGMILive {
421421 const SIInstrInfo *SITII;
422422 const SIRegisterInfo *SITRI;
423423
1212 //===----------------------------------------------------------------------===//
1313
1414
15 #ifndef LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
16 #define LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
1717
1818 #include "AMDGPURegisterInfo.h"
1919 #include "AMDGPUSubtarget.h"
2222
2323 namespace llvm {
2424
25 struct SIRegisterInfo : public AMDGPURegisterInfo {
25 struct SIRegisterInfo final : public AMDGPURegisterInfo {
2626 private:
2727 unsigned SGPR32SetID;
2828 unsigned VGPR32SetID;