llvm.org GIT mirror llvm / 7104616
Add callback to allow target to adjust latency of schedule dependency edge. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78910 91177308-0d34-0410-b5e6-96231b3b80d8 David Goodwin 10 years ago
4 changed file(s) with 31 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
142142 /// between them.
143143 unsigned getLatency() const {
144144 return Latency;
145 }
146
147 /// setLatency - Set the latency for this edge.
148 void setLatency(unsigned Lat) {
149 Latency = Lat;
145150 }
146151
147152 //// getSUnit - Return the SUnit to which this edge points.
1414 #define LLVM_TARGET_TARGETSUBTARGET_H
1515
1616 namespace llvm {
17
18 class SDep;
1719
1820 //===----------------------------------------------------------------------===//
1921 ///
3436 /// indicating the number of scheduling cycles of backscheduling that
3537 /// should be attempted.
3638 virtual unsigned getSpecialAddressLatency() const { return 0; }
39
40 // adjustSchedDependency - Perform target specific adjustments to
41 // the latency of a schedule dependency.
42 virtual void adjustSchedDependency(SDep&) const { };
3743 };
3844
3945 } // End llvm namespace
144144 bool UnitLatencies = ForceUnitLatencies();
145145
146146 // Ask the target if address-backscheduling is desirable, and if so how much.
147 unsigned SpecialAddressLatency =
148 TM.getSubtarget().getSpecialAddressLatency();
147 const TargetSubtarget &ST = TM.getSubtarget();
148 unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
149149
150150 // Walk the list of instructions, from bottom moving up.
151151 for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin;
219219 UseTID.OpInfo[RegUseIndex].isLookupPtrRegClass())
220220 LDataLatency += SpecialAddressLatency;
221221 }
222 UseSU->addPred(SDep(SU, SDep::Data, LDataLatency, Reg));
222 const SDep& dep = SDep(SU, SDep::Data, LDataLatency, Reg);
223 ST.adjustSchedDependency((SDep &)dep);
224 UseSU->addPred(dep);
223225 }
224226 }
225227 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
226228 std::vector &UseList = Uses[*Alias];
227229 for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
228230 SUnit *UseSU = UseList[i];
229 if (UseSU != SU)
230 UseSU->addPred(SDep(SU, SDep::Data, DataLatency, *Alias));
231 if (UseSU != SU) {
232 const SDep& dep = SDep(SU, SDep::Data, DataLatency, *Alias);
233 ST.adjustSchedDependency((SDep &)dep);
234 UseSU->addPred(dep);
235 }
231236 }
232237 }
233238
1717 #include "llvm/Target/TargetMachine.h"
1818 #include "llvm/Target/TargetInstrInfo.h"
1919 #include "llvm/Target/TargetRegisterInfo.h"
20 #include "llvm/Target/TargetSubtarget.h"
2021 #include "llvm/Support/Debug.h"
2122 #include "llvm/Support/raw_ostream.h"
2223 using namespace llvm;
151152 }
152153
153154 void ScheduleDAGSDNodes::AddSchedEdges() {
155 const TargetSubtarget &ST = TM.getSubtarget();
156
154157 // Pass 2: add the preds, succs, etc.
155158 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
156159 SUnit *SU = &SUnits[su];
205208 // dependency. This may change in the future though.
206209 if (Cost >= 0)
207210 PhysReg = 0;
208 SU->addPred(SDep(OpSU, isChain ? SDep::Order : SDep::Data,
209 OpSU->Latency, PhysReg));
211
212 const SDep& dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
213 OpSU->Latency, PhysReg);
214 if (!isChain)
215 ST.adjustSchedDependency((SDep &)dep);
216
217 SU->addPred(dep);
210218 }
211219 }
212220 }