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AMDGPU/GlobalISel: Enable TableGen'd instruction selector Reviewers: arsenm, nhaehnle Reviewed By: arsenm Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45994 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332039 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
8 changed file(s) with 177 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
0 //===-- AMDGPUGIsel.td - AMDGPU GlobalISel Patterns---------*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 // This files contains patterns that should only be used by GlobalISel. For
9 // example patterns for V_* instructions that have S_* equivalents.
10 // SelectionDAG does not support selecting V_* instructions.
11 //===----------------------------------------------------------------------===//
12
13 include "AMDGPU.td"
14
15 def sd_vsrc0 : ComplexPattern;
16 def gi_vsrc0 :
17 GIComplexOperandMatcher,
18 GIComplexPatternEquiv;
19
20 class GISelSop2Pat <
21 SDPatternOperator node,
22 Instruction inst,
23 ValueType dst_vt,
24 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
25
26 (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
27 (inst src0_vt:$src0, src1_vt:$src1)
28 >;
29
30 class GISelVop2Pat <
31 SDPatternOperator node,
32 Instruction inst,
33 ValueType dst_vt,
34 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
35
36 (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))),
37 (inst src0_vt:$src0, src1_vt:$src1)
38 >;
39
40 def : GISelSop2Pat ;
41 def : GISelVop2Pat ;
1616 #include "AMDGPURegisterBankInfo.h"
1717 #include "AMDGPURegisterInfo.h"
1818 #include "AMDGPUSubtarget.h"
19 #include "AMDGPUTargetMachine.h"
20 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
1922 #include "llvm/CodeGen/GlobalISel/Utils.h"
2023 #include "llvm/CodeGen/MachineBasicBlock.h"
2124 #include "llvm/CodeGen/MachineFunction.h"
3033
3134 using namespace llvm;
3235
36 #define GET_GLOBALISEL_IMPL
37 #include "AMDGPUGenGlobalISel.inc"
38 #undef GET_GLOBALISEL_IMPL
39
3340 AMDGPUInstructionSelector::AMDGPUInstructionSelector(
34 const SISubtarget &STI, const AMDGPURegisterBankInfo &RBI)
41 const SISubtarget &STI, const AMDGPURegisterBankInfo &RBI,
42 const AMDGPUTargetMachine &TM)
3543 : InstructionSelector(), TII(*STI.getInstrInfo()),
36 TRI(*STI.getRegisterInfo()), RBI(RBI), AMDGPUASI(STI.getAMDGPUAS()) {}
44 TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM),
45 STI(STI),
46 EnableLateStructurizeCFG(AMDGPUTargetMachine::EnableLateStructurizeCFG),
47 #define GET_GLOBALISEL_PREDICATES_INIT
48 #include "AMDGPUGenGlobalISel.inc"
49 #undef GET_GLOBALISEL_PREDICATES_INIT
50 #define GET_GLOBALISEL_TEMPORARIES_INIT
51 #include "AMDGPUGenGlobalISel.inc"
52 #undef GET_GLOBALISEL_TEMPORARIES_INIT
53 ,AMDGPUASI(STI.getAMDGPUAS())
54 {
55 }
56
57 const char *AMDGPUInstructionSelector::getName() { return DEBUG_TYPE; }
3758
3859 MachineOperand
3960 AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO,
415436 switch (I.getOpcode()) {
416437 default:
417438 break;
439 case TargetOpcode::G_OR:
440 return selectImpl(I, CoverageInfo);
418441 case TargetOpcode::G_ADD:
419442 return selectG_ADD(I);
420443 case TargetOpcode::G_CONSTANT:
428451 }
429452 return false;
430453 }
454
455 ///
456 /// This will select either an SGPR or VGPR operand and will save us from
457 /// having to write an extra tablegen pattern.
458 InstructionSelector::ComplexRendererFns
459 AMDGPUInstructionSelector::selectVSRC0(MachineOperand &Root) const {
460 return {{
461 [=](MachineInstrBuilder &MIB) { MIB.add(Root); }
462 }};
463 }
1818 #include "llvm/ADT/SmallVector.h"
1919 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
2020
21 namespace {
22 #define GET_GLOBALISEL_PREDICATE_BITSET
23 #include "AMDGPUGenGlobalISel.inc"
24 #undef GET_GLOBALISEL_PREDICATE_BITSET
25 }
26
2127 namespace llvm {
2228
2329 class AMDGPUInstrInfo;
2430 class AMDGPURegisterBankInfo;
31 class AMDGPUSubtarget;
2532 class MachineInstr;
2633 class MachineOperand;
2734 class MachineRegisterInfo;
3239 class AMDGPUInstructionSelector : public InstructionSelector {
3340 public:
3441 AMDGPUInstructionSelector(const SISubtarget &STI,
35 const AMDGPURegisterBankInfo &RBI);
42 const AMDGPURegisterBankInfo &RBI,
43 const AMDGPUTargetMachine &TM);
3644
3745 bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
46 static const char *getName();
3847
3948 private:
4049 struct GEPInfo {
4453 int64_t Imm;
4554 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
4655 };
56
57 /// tblgen-erated 'select' implementation.
58 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
4759
4860 MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
4961 bool selectG_CONSTANT(MachineInstr &I) const;
5668 bool selectG_LOAD(MachineInstr &I) const;
5769 bool selectG_STORE(MachineInstr &I) const;
5870
71 InstructionSelector::ComplexRendererFns
72 selectVSRC0(MachineOperand &Root) const;
73
5974 const SIInstrInfo &TII;
6075 const SIRegisterInfo &TRI;
6176 const AMDGPURegisterBankInfo &RBI;
77 const AMDGPUTargetMachine &TM;
78 const SISubtarget &STI;
79 bool EnableLateStructurizeCFG;
80 #define GET_GLOBALISEL_PREDICATES_DECL
81 #include "AMDGPUGenGlobalISel.inc"
82 #undef GET_GLOBALISEL_PREDICATES_DECL
83
84 #define GET_GLOBALISEL_TEMPORARIES_DECL
85 #include "AMDGPUGenGlobalISel.inc"
86 #undef GET_GLOBALISEL_TEMPORARIES_DECL
87
6288 protected:
6389 AMDGPUAS AMDGPUASI;
6490 };
380380
381381 RegBankInfo.reset(new AMDGPURegisterBankInfo(*getRegisterInfo()));
382382 InstSelector.reset(new AMDGPUInstructionSelector(
383 *this, *static_cast(RegBankInfo.get())));
383 *this, *static_cast(RegBankInfo.get()), TM));
384384 }
385385
386386 void SISubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
1313 tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
1414 tablegen(LLVM AMDGPUGenSearchableTables.inc -gen-searchable-tables)
1515 tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
16
17 set(LLVM_TARGET_DEFINITIONS AMDGPUGISel.td)
18 tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel)
1619
1720 add_public_tablegen_target(AMDGPUCommonTableGen)
1821
1212 //===----------------------------------------------------------------------===//
1313
1414 #include "SIRegisterInfo.h"
15 #include "AMDGPURegisterBankInfo.h"
1516 #include "AMDGPUSubtarget.h"
1617 #include "SIInstrInfo.h"
1718 #include "SIMachineFunctionInfo.h"
15611562 return Empty;
15621563 return AMDGPURegisterInfo::getRegUnitPressureSets(RegUnit);
15631564 }
1565
1566 const TargetRegisterClass *
1567 SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
1568 const MachineRegisterInfo &MRI) const {
1569 unsigned Size = getRegSizeInBits(MO.getReg(), MRI);
1570 const RegisterBank *RB = MRI.getRegBankOrNull(MO.getReg());
1571 if (!RB)
1572 return nullptr;
1573
1574 switch (Size) {
1575 case 32:
1576 return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass :
1577 &AMDGPU::SReg_32_XM0RegClass;
1578 case 64:
1579 return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_64RegClass :
1580 &AMDGPU::SReg_64_XEXECRegClass;
1581 default:
1582 llvm_unreachable("not implemented");
1583 }
1584 }
226226 // Not a callee saved register.
227227 return AMDGPU::SGPR30_SGPR31;
228228 }
229 const TargetRegisterClass *
230 getConstrainedRegClassForOperand(const MachineOperand &MO,
231 const MachineRegisterInfo &MRI) const override;
229232
230233 private:
231234 void buildSpillLoadStore(MachineBasicBlock::iterator MI,
0 # RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
1
2 --- |
3 define void @or(i32 addrspace(1)* %global0) {ret void}
4 ...
5 ---
6
7 name: or
8 legalized: true
9 regBankSelected: true
10
11 # GCN-LABEL: name: or
12 body: |
13 bb.0:
14 liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
15 ; GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
16 ; GCN: [[SGPR1:%[0-9]+]]:sreg_32 = COPY $sgpr1
17 ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
18 %0:sgpr(s32) = COPY $sgpr0
19 %1:sgpr(s32) = COPY $sgpr1
20 %2:vgpr(s32) = COPY $vgpr0
21 %3:vgpr(s64) = COPY $vgpr3_vgpr4
22 %4:sgpr(s32) = G_CONSTANT i32 1
23 %5:sgpr(s32) = G_CONSTANT i32 4096
24
25 ; or ss
26 ; GCN: [[SS:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[SGPR0]], [[SGPR1]]
27 %6:sgpr(s32) = G_OR %0, %1
28
29 ; or vs
30 ; GCN: [[VS:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SS]], [[VGPR0]]
31 %7:vgpr(s32) = G_OR %2, %6
32
33 ; or sv
34 ; GCN: [[SV:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SS]], [[VS]]
35 %8:vgpr(s32) = G_OR %6, %7
36
37 ; or vv
38 ; GCN: [[VV:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SV]], [[VGPR0]]
39 %9:vgpr(s32) = G_OR %8, %2
40
41 G_STORE %9, %3 :: (store 4 into %ir.global0)
42
43 ...
44 ---