llvm.org GIT mirror llvm / 702c4f0
[DAGCombiner] Support (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C)) non-uniform folds. Use matchBinaryPredicate instead of isConstOrConstSplat to let us handle non-uniform shift cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363929 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 2 months ago
2 changed file(s) with 32 addition(s) and 44 deletion(s). Raw diff Collapse all Expand all
72587258 // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
72597259 // Only fold this if the inner zext has no other uses to avoid increasing
72607260 // the total number of instructions.
7261 // TODO - support non-uniform vector shift amounts.
7262 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
7261 if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
72637262 N0.getOperand(0).getOpcode() == ISD::SRL) {
72647263 SDValue N0Op0 = N0.getOperand(0);
7265 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
7266 if (N0Op0C1->getAPIntValue().ult(VT.getScalarSizeInBits())) {
7267 uint64_t c1 = N0Op0C1->getZExtValue();
7268 uint64_t c2 = N1C->getZExtValue();
7269 if (c1 == c2) {
7270 SDValue NewOp0 = N0.getOperand(0);
7271 EVT CountVT = NewOp0.getOperand(1).getValueType();
7272 SDLoc DL(N);
7273 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, NewOp0.getValueType(),
7274 NewOp0,
7275 DAG.getConstant(c2, DL, CountVT));
7276 AddToWorklist(NewSHL.getNode());
7277 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
7278 }
7279 }
7264 SDValue InnerShiftAmt = N0Op0.getOperand(1);
7265 EVT InnerShiftAmtVT = N0Op0.getOperand(1).getValueType();
7266
7267 auto MatchEqual = [VT](ConstantSDNode *LHS, ConstantSDNode *RHS) {
7268 APInt c1 = LHS->getAPIntValue();
7269 APInt c2 = RHS->getAPIntValue();
7270 zeroExtendToMatch(c1, c2);
7271 return c1.ult(VT.getScalarSizeInBits()) && (c1 == c2);
7272 };
7273 if (ISD::matchBinaryPredicate(InnerShiftAmt, N1, MatchEqual,
7274 /*AllowUndefs*/ false,
7275 /*AllowTypeMismatch*/ true)) {
7276 SDLoc DL(N);
7277 EVT InnerShiftAmtVT = N0Op0.getOperand(1).getValueType();
7278 SDValue NewSHL = DAG.getZExtOrTrunc(N1, DL, InnerShiftAmtVT);
7279 NewSHL = DAG.getNode(ISD::SHL, DL, N0Op0.getValueType(), N0Op0, NewSHL);
7280 AddToWorklist(NewSHL.getNode());
7281 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
72807282 }
72817283 }
72827284
362362 define <8 x i32> @combine_vec_shl_zext_lshr1(<8 x i16> %x) {
363363 ; SSE2-LABEL: combine_vec_shl_zext_lshr1:
364364 ; SSE2: # %bb.0:
365 ; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm0
366 ; SSE2-NEXT: pxor %xmm1, %xmm1
367 ; SSE2-NEXT: movdqa %xmm0, %xmm2
368 ; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
369 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
370 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2,4,8,16]
371 ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
372 ; SSE2-NEXT: pmuludq %xmm1, %xmm0
373 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
374 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
375 ; SSE2-NEXT: pmuludq %xmm3, %xmm1
376 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
377 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
378 ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [32,64,128,256]
379 ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3]
380 ; SSE2-NEXT: pmuludq %xmm3, %xmm2
381 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
382 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3]
383 ; SSE2-NEXT: pmuludq %xmm4, %xmm2
384 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
385 ; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
365 ; SSE2-NEXT: movdqa %xmm0, %xmm1
366 ; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm1
367 ; SSE2-NEXT: pxor %xmm2, %xmm2
368 ; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm1
369 ; SSE2-NEXT: movdqa %xmm1, %xmm0
370 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
371 ; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
386372 ; SSE2-NEXT: retq
387373 ;
388374 ; SSE41-LABEL: combine_vec_shl_zext_lshr1:
389375 ; SSE41: # %bb.0:
390376 ; SSE41-NEXT: pmulhuw {{.*}}(%rip), %xmm0
391 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
392 ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
393 ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
394 ; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
395 ; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm1
377 ; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm0
378 ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
379 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
380 ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
381 ; SSE41-NEXT: movdqa %xmm2, %xmm0
396382 ; SSE41-NEXT: retq
397383 ;
398384 ; AVX-LABEL: combine_vec_shl_zext_lshr1:
399385 ; AVX: # %bb.0:
400386 ; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
387 ; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
401388 ; AVX-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
402 ; AVX-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0
403389 ; AVX-NEXT: retq
404390 %1 = lshr <8 x i16> %x,
405391 %2 = zext <8 x i16> %1 to <8 x i32>