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[WebAssembly] Bitselect intrinsic and instruction Summary: Depends on D52755. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52805 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343739 91177308-0d34-0410-b5e6-96231b3b80d8 Thomas Lively 1 year, 6 months ago
7 changed file(s) with 209 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
9090 // SIMD intrinsics
9191 //===----------------------------------------------------------------------===//
9292
93 def int_wasm_bitselect :
94 Intrinsic<[llvm_anyvector_ty],
95 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
96 [IntrNoMem, IntrSpeculatable]>;
9397 def int_wasm_anytrue :
9498 Intrinsic<[llvm_i32_ty],
9599 [llvm_anyvector_ty],
2323 HANDLE_NODETYPE(SHUFFLE)
2424 HANDLE_NODETYPE(ANYTRUE)
2525 HANDLE_NODETYPE(ALLTRUE)
26 HANDLE_NODETYPE(BITSELECT)
2627
2728 // add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...
964964 switch (IntNo) {
965965 default:
966966 return {}; // Don't custom lower most intrinsics.
967
968 case Intrinsic::wasm_bitselect:
969 return DAG.getNode(WebAssemblyISD::BITSELECT, DL, Op.getValueType(),
970 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
971
967972 case Intrinsic::wasm_anytrue:
968973 case Intrinsic::wasm_alltrue: {
969974 unsigned OpCode = IntNo == Intrinsic::wasm_anytrue
971976 : WebAssemblyISD::ALLTRUE;
972977 return DAG.getNode(OpCode, DL, Op.getValueType(), Op.getOperand(1));
973978 }
979
974980 case Intrinsic::wasm_lsda:
975981 // TODO For now, just return 0 not to crash
976982 return DAG.getConstant(0, DL, Op.getValueType());
1919
2020 // Custom nodes for custom operations
2121 def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
22 def wasm_bitselect_t : SDTypeProfile<1, 3,
23 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]
24 >;
2225 def wasm_reduce_t : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>;
2326 def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
27 def wasm_bitselect : SDNode<"WebAssemblyISD::BITSELECT", wasm_bitselect_t>;
2428 def wasm_anytrue : SDNode<"WebAssemblyISD::ANYTRUE", wasm_reduce_t>;
2529 def wasm_alltrue : SDNode<"WebAssemblyISD::ALLTRUE", wasm_reduce_t>;
2630
191195 ))
192196 )],
193197 "v128.not\t$dst, $vec", "v128.not", 63>;
198 }
199 multiclass Bitselect {
200 defm BITSELECT_#vec_t :
201 SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
202 [(set (vec_t V128:$dst),
203 (vec_t (wasm_bitselect
204 (vec_t V128:$c), (vec_t V128:$v1), (vec_t V128:$v2)
205 ))
206 )],
207 "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 64>;
194208 }
195209 multiclass SIMDReduceVec
196210 bits<32> simdop> {
379393 defm "" : SIMDNot;
380394 defm "" : SIMDNot;
381395
396 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
397 defm "" : Bitselect;
398
382399 defm ANYTRUE : SIMDReduce<"any_true", wasm_anytrue, 65>;
383400 defm ALLTRUE : SIMDReduce<"all_true", wasm_alltrue, 69>;
384401
441458 def : StorePatExternSymOffOnly("STORE_"#vec_t)>;
442459
443460 }
461
462 // Bitselect is equivalent to (c & v1) | (~c & v2)
463 foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
464 def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)),
465 (and (vnot V128:$c), (vec_t V128:$v2)))),
466 (!cast("BITSELECT_"#vec_t)
467 V128:$v1, V128:$v2, V128:$c)>;
444468
445469 // Lower float comparisons that don't care about NaN to standard
446470 // WebAssembly float comparisons. These instructions are generated in
None ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
1 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
2 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
3 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM
4 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
5 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
0 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW
1 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST
2 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM,SIMD128-VM-SLOW
3 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM,SIMD128-VM-FAST
4 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128,NO-SIMD128-SLOW
5 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128,NO-SIMD128-FAST
66
77 ; Test that basic SIMD128 arithmetic operations assemble as expected.
88
164164 ret <16 x i8> %a
165165 }
166166
167 ; CHECK-LABEL: bitselect_v16i8:
168 ; NO-SIMD128-NOT: v128
169 ; SIMD128-NEXT: .param v128, v128, v128{{$}}
170 ; SIMD128-NEXT: .result v128{{$}}
171 ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
172 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
173 ; SIMD128-FAST-NEXT: v128.and
174 ; SIMD128-FAST-NEXT: v128.not
175 ; SIMD128-FAST-NEXT: v128.and
176 ; SIMD128-FAST-NEXT: v128.or
177 ; SIMD128-FAST-NEXT: return
178 define <16 x i8> @bitselect_v16i8(<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2) {
179 %masked_v1 = and <16 x i8> %c, %v1
180 %inv_mask = xor <16 x i8> %c,
181
182 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
183 %masked_v2 = and <16 x i8> %inv_mask, %v2
184 %a = or <16 x i8> %masked_v1, %masked_v2
185 ret <16 x i8> %a
186 }
187
167188 ; ==============================================================================
168189 ; 8 x i16
169190 ; ==============================================================================
312333 ret <8 x i16> %a
313334 }
314335
336 ; CHECK-LABEL: bitselect_v8i16:
337 ; NO-SIMD128-NOT: v128
338 ; SIMD128-NEXT: .param v128, v128, v128{{$}}
339 ; SIMD128-NEXT: .result v128{{$}}
340 ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
341 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
342 ; SIMD128-FAST-NEXT: v128.and
343 ; SIMD128-FAST-NEXT: v128.not
344 ; SIMD128-FAST-NEXT: v128.and
345 ; SIMD128-FAST-NEXT: v128.or
346 ; SIMD128-FAST-NEXT: return
347 define <8 x i16> @bitselect_v8i16(<8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2) {
348 %masked_v1 = and <8 x i16> %v1, %c
349 %inv_mask = xor <8 x i16>
350 ,
351 %c
352 %masked_v2 = and <8 x i16> %v2, %inv_mask
353 %a = or <8 x i16> %masked_v1, %masked_v2
354 ret <8 x i16> %a
355 }
356
315357 ; ==============================================================================
316358 ; 4 x i32
317359 ; ==============================================================================
454496 ; SIMD128-NEXT: return $pop[[R]]{{$}}
455497 define <4 x i32> @not_v4i32(<4 x i32> %x) {
456498 %a = xor <4 x i32> %x,
499 ret <4 x i32> %a
500 }
501
502 ; CHECK-LABEL: bitselect_v4i32:
503 ; NO-SIMD128-NOT: v128
504 ; SIMD128-NEXT: .param v128, v128, v128{{$}}
505 ; SIMD128-NEXT: .result v128{{$}}
506 ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
507 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
508 ; SIMD128-FAST-NEXT: v128.not
509 ; SIMD128-FAST-NEXT: v128.and
510 ; SIMD128-FAST-NEXT: v128.and
511 ; SIMD128-FAST-NEXT: v128.or
512 ; SIMD128-FAST-NEXT: return
513 define <4 x i32> @bitselect_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) {
514 %masked_v1 = and <4 x i32> %c, %v1
515 %inv_mask = xor <4 x i32> , %c
516 %masked_v2 = and <4 x i32> %inv_mask, %v2
517 %a = or <4 x i32> %masked_v2, %masked_v1
457518 ret <4 x i32> %a
458519 }
459520
652713 ret <2 x i64> %a
653714 }
654715
716 ; CHECK-LABEL: bitselect_v2i64:
717 ; NO-SIMD128-NOT: v128
718 ; SIMD128-VM-NOT: v128
719 ; SIMD128-NEXT: .param v128, v128, v128{{$}}
720 ; SIMD128-NEXT: .result v128{{$}}
721 ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
722 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
723 ; SIMD128-FAST-NEXT: v128.not
724 ; SIMD128-FAST-NEXT: v128.and
725 ; SIMD128-FAST-NEXT: v128.and
726 ; SIMD128-FAST-NEXT: v128.or
727 ; SIMD128-FAST-NEXT: return
728 define <2 x i64> @bitselect_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) {
729 %masked_v1 = and <2 x i64> %v1, %c
730 %inv_mask = xor <2 x i64> , %c
731 %masked_v2 = and <2 x i64> %v2, %inv_mask
732 %a = or <2 x i64> %masked_v2, %masked_v1
733 ret <2 x i64> %a
734 }
735
655736 ; ==============================================================================
656737 ; 4 x float
657738 ; ==============================================================================
760841 ret <2 x double> %a
761842 }
762843
763
764844 ; CHECK-LABEL: add_v2f64:
765845 ; NO-SIMD128-NOT: f64x2
766846 ; SIMD128-VM-NOT: f62x2
3232 ret i32 %a
3333 }
3434
35 ; CHECK-LABEL: bitselect_v16i8:
36 ; SIMD128-NEXT: .param v128, v128, v128{{$}}
37 ; SIMD128-NEXT: .result v128{{$}}
38 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
39 ; SIMD128-NEXT: return $pop[[R]]{{$}}
40 declare <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
41 define <16 x i8> @bitselect_v16i8(<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2) {
42 %a = call <16 x i8> @llvm.wasm.bitselect.v16i8(
43 <16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2
44 )
45 ret <16 x i8> %a
46 }
47
3548 ; ==============================================================================
3649 ; 8 x i16
3750 ; ==============================================================================
5568 define i32 @all_v8i16(<8 x i16> %x) {
5669 %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x)
5770 ret i32 %a
71 }
72
73 ; CHECK-LABEL: bitselect_v8i16:
74 ; SIMD128-NEXT: .param v128, v128, v128{{$}}
75 ; SIMD128-NEXT: .result v128{{$}}
76 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
77 ; SIMD128-NEXT: return $pop[[R]]{{$}}
78 declare <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
79 define <8 x i16> @bitselect_v8i16(<8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2) {
80 %a = call <8 x i16> @llvm.wasm.bitselect.v8i16(
81 <8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2
82 )
83 ret <8 x i16> %a
5884 }
5985
6086 ; ==============================================================================
82108 ret i32 %a
83109 }
84110
111 ; CHECK-LABEL: bitselect_v4i32:
112 ; SIMD128-NEXT: .param v128, v128, v128{{$}}
113 ; SIMD128-NEXT: .result v128{{$}}
114 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
115 ; SIMD128-NEXT: return $pop[[R]]{{$}}
116 declare <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
117 define <4 x i32> @bitselect_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) {
118 %a = call <4 x i32> @llvm.wasm.bitselect.v4i32(
119 <4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2
120 )
121 ret <4 x i32> %a
122 }
123
85124 ; ==============================================================================
86125 ; 2 x i64
87126 ; ==============================================================================
106145 %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x)
107146 ret i32 %a
108147 }
148
149 ; CHECK-LABEL: bitselect_v2i64:
150 ; SIMD128-NEXT: .param v128, v128, v128{{$}}
151 ; SIMD128-NEXT: .result v128{{$}}
152 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
153 ; SIMD128-NEXT: return $pop[[R]]{{$}}
154 declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
155 define <2 x i64> @bitselect_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) {
156 %a = call <2 x i64> @llvm.wasm.bitselect.v2i64(
157 <2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2
158 )
159 ret <2 x i64> %a
160 }
161
162 ; ==============================================================================
163 ; 4 x f32
164 ; ==============================================================================
165 ; CHECK-LABEL: bitselect_v4f32:
166 ; SIMD128-NEXT: .param v128, v128, v128{{$}}
167 ; SIMD128-NEXT: .result v128{{$}}
168 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
169 ; SIMD128-NEXT: return $pop[[R]]{{$}}
170 declare <4 x float> @llvm.wasm.bitselect.v4f32(<4 x float>, <4 x float>, <4 x float>)
171 define <4 x float> @bitselect_v4f32(<4 x float> %c, <4 x float> %v1, <4 x float> %v2) {
172 %a = call <4 x float> @llvm.wasm.bitselect.v4f32(
173 <4 x float> %c, <4 x float> %v1, <4 x float> %v2
174 )
175 ret <4 x float> %a
176 }
177
178 ; ==============================================================================
179 ; 2 x f64
180 ; ==============================================================================
181 ; CHECK-LABEL: bitselect_v2f64:
182 ; SIMD128-NEXT: .param v128, v128, v128{{$}}
183 ; SIMD128-NEXT: .result v128{{$}}
184 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
185 ; SIMD128-NEXT: return $pop[[R]]{{$}}
186 declare <2 x double> @llvm.wasm.bitselect.v2f64(<2 x double>, <2 x double>, <2 x double>)
187 define <2 x double> @bitselect_v2f64(<2 x double> %c, <2 x double> %v1, <2 x double> %v2) {
188 %a = call <2 x double> @llvm.wasm.bitselect.v2f64(
189 <2 x double> %c, <2 x double> %v1, <2 x double> %v2
190 )
191 ret <2 x double> %a
192 }
192192 # CHECK: v128.not # encoding: [0xfd,0x3f]
193193 v128.not
194194
195 # CHECK: v128.bitselect # encoding: [0xfd,0x40]
196 v128.bitselect
197
195198 # CHECK: i8x16.any_true # encoding: [0xfd,0x41]
196199 i8x16.any_true
197200