llvm.org GIT mirror llvm / 6f0d024
Rename MRegisterInfo to TargetRegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 11 years ago
109 changed file(s) with 1300 addition(s) and 1282 deletion(s). Raw diff Collapse all Expand all
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17641764 DE66EF1108ABEE5E00323D32 /* PowerPC */,
17651765 DE66EF7008ABEE5F00323D32 /* Sparc */,
17661766 DE66F09308ABEE6000323D32 /* X86 */,
1767 DE66EF1008ABEE5E00323D32 /* MRegisterInfo.cpp */,
1767 DE66EF1008ABEE5E00323D32 /* TargetRegisterInfo.cpp */,
17681768 CF9BCD1508C75070001E7011 /* SubtargetFeature.cpp */,
17691769 DE66F08A08ABEE6000323D32 /* Target.td */,
17701770 CF47BD860AAF487E00A8B13E /* TargetAsmInfo.cpp */,
24442444 DE66F29F08ABF03200323D32 /* Target */ = {
24452445 isa = PBXGroup;
24462446 children = (
2447 DE66F2A008ABF03200323D32 /* MRegisterInfo.h */,
2447 DE66F2A008ABF03200323D32 /* TargetRegisterInfo.h */,
24482448 CF9BCD0808C74DE0001E7011 /* SubtargetFeature.h */,
24492449 CF47BD380AAF40BC00A8B13E /* TargetAsmInfo.h */,
24502450 DE66F2A108ABF03200323D32 /* TargetData.h */,
2525
  • The TargetMachine class
  • 2626
  • The TargetData class
  • 2727
  • The TargetLowering class
  • 28
  • The MRegisterInfo class
  • 28
  • The TargetRegisterInfo class
  • 2929
  • The TargetInstrInfo class
  • 3030
  • The TargetFrameInfo class
  • 3131
  • The TargetSubtarget class
  • 387387
    388388
    389389
    390 The MRegisterInfo class
    391
    392
    393
    394
    395

    The MRegisterInfo class (which will eventually be renamed to

    396 TargetRegisterInfo) is used to describe the register file of the
    397 target and any interactions between the registers.>
    390 The TargetRegisterInfo class>
    391
    392
    393
    394
    395

    The TargetRegisterInfo class is used to describe the register

    396 file of the target and any interactions between the registers.

    398397
    399398

    Registers in the code generator are represented in the code generator by

    400399 unsigned integers. Physical registers (those that actually exist in the target
    407406 (used to indicate whether one register overlaps with another).
    408407

    409408
    410

    In addition to the per-register description, the MRegisterInfo class

    411 exposes a set of processor specific register classes (instances of the
    409

    In addition to the per-register description, the TargetRegisterInfo

    410 class exposes a set of processor specific register classes (instances of the
    412411 TargetRegisterClass class). Each register class contains sets of
    413412 registers that have the same properties (for example, they are all 32-bit
    414413 integer registers). Each SSA virtual register created by the instruction
    12911290 marked as aliased in LLVM. Given a particular architecture, you
    12921291 can check which registers are aliased by inspecting its
    12931292 RegisterInfo.td file. Moreover, the method
    1294 MRegisterInfo::getAliasSet(p_reg) returns an array containing
    1293 TargetRegisterInfo::getAliasSet(p_reg) returns an array containing
    12951294 all the physical registers aliased to the register p_reg.

    12961295
    12971296

    Physical registers, in LLVM, are grouped in Register Classes.

    13091308 bool RegMapping_Fer::compatible_class(MachineFunction &mf,
    13101309 unsigned v_reg,
    13111310 unsigned p_reg) {
    1312 assert(MRegisterInfo::isPhysicalRegister(p_reg) &&
    1311 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &&
    13131312 "Target register must be physical");
    13141313 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
    13151314 return trc->contains(p_reg);
    13341333 number. The smallest virtual register is normally assigned the number
    13351334 1024. This may change, so, in order to know which is the first virtual
    13361335 register, you should access
    1337 MRegisterInfo::FirstVirtualRegister. Any register whose
    1336 TargetRegisterInfo::FirstVirtualRegister. Any register whose
    13381337 number is greater than or equal to
    1339 MRegisterInfo::FirstVirtualRegister is considered a virtual
    1338 TargetRegisterInfo::FirstVirtualRegister is considered a virtual
    13401339 register. Whereas physical registers are statically defined in a
    13411340 TargetRegisterInfo.td file and cannot be created by the
    13421341 application developer, that is not the case with virtual registers.
    13931392
    13941393

    There are two ways to map virtual registers to physical registers (or to

    13951394 memory slots). The first way, that we will call direct mapping,
    1396 is based on the use of methods of the classes MRegisterInfo,
    1395 is based on the use of methods of the classes TargetRegisterInfo,
    13971396 and MachineOperand. The second way, that we will call
    13981397 indirect mapping, relies on the VirtRegMap class in
    13991398 order to insert loads and stores sending and getting values to and from
    14071406 memory. To assign a physical register to a virtual register present in
    14081407 a given operand, use MachineOperand::setReg(p_reg). To insert
    14091408 a store instruction, use
    1410 MRegisterInfo::storeRegToStackSlot(...), and to insert a load
    1411 instruction, use MRegisterInfo::loadRegFromStackSlot.

    1409 TargetRegisterInfo::storeRegToStackSlot(...), and to insert a load
    1410 instruction, use TargetRegisterInfo::loadRegFromStackSlot.

    14121411
    14131412

    The indirect mapping shields the application developer from the

    14141413 complexities of inserting load and store instructions. In order to map
    15281527
    15291528
    15301529

    Instructions can be folded with the

    1531 MRegisterInfo::foldMemoryOperand(...) method. Care must be
    1530 TargetRegisterInfo::foldMemoryOperand(...) method. Care must be
    15321531 taken when folding instructions; a folded instruction can be quite
    15331532 different from the original instruction. See
    15341533 LiveIntervals::addIntervalsForSpills in
    7373
  • Create a TableGen description of
  • 7474 the register set and register classes
    7575
  • Implement a subclass of
  • 76 href="CodeGenerator.html#mregisterinfo">MRegisterInfo
    76 href="CodeGenerator.html#targetregisterinfo">TargetRegisterInfo
    7777
    7878
  • Describe the instruction set.
  • 7979
    1818 #include "llvm/CodeGen/ValueTypes.h"
    1919
    2020 namespace llvm {
    21 class MRegisterInfo;
    21 class TargetRegisterInfo;
    2222 class TargetMachine;
    2323 class CCState;
    2424 class SDNode;
    106106 unsigned CallingConv;
    107107 bool IsVarArg;
    108108 const TargetMachine &TM;
    109 const MRegisterInfo &MRI;
    109 const TargetRegisterInfo &TRI;
    110110 SmallVector &Locs;
    111111
    112112 unsigned StackOffset;
    2929
    3030 namespace llvm {
    3131 class MachineInstr;
    32 class MRegisterInfo;
    32 class TargetRegisterInfo;
    3333 struct LiveInterval;
    3434
    3535 /// VNInfo - If the value number definition is undefined (e.g. phi
    345345 return beginNumber() < other.beginNumber();
    346346 }
    347347
    348 void print(std::ostream &OS, const MRegisterInfo *MRI = 0) const;
    349 void print(std::ostream *OS, const MRegisterInfo *MRI = 0) const {
    350 if (OS) print(*OS, MRI);
    348 void print(std::ostream &OS, const TargetRegisterInfo *TRI = 0) const;
    349 void print(std::ostream *OS, const TargetRegisterInfo *TRI = 0) const {
    350 if (OS) print(*OS, TRI);
    351351 }
    352352 void dump() const;
    353353
    3232
    3333 class LiveVariables;
    3434 class MachineLoopInfo;
    35 class MRegisterInfo;
    35 class TargetRegisterInfo;
    3636 class MachineRegisterInfo;
    3737 class TargetInstrInfo;
    3838 class TargetRegisterClass;
    4242 class LiveIntervals : public MachineFunctionPass {
    4343 MachineFunction* mf_;
    4444 const TargetMachine* tm_;
    45 const MRegisterInfo* mri_;
    45 const TargetRegisterInfo* tri_;
    4646 const TargetInstrInfo* tii_;
    4747 LiveVariables* lv_;
    4848
    3636
    3737 namespace llvm {
    3838
    39 class MRegisterInfo;
    39 class TargetRegisterInfo;
    4040
    4141 class LiveVariables : public MachineFunctionPass {
    4242 public:
    129129 private: // Intermediate data structures
    130130 MachineFunction *MF;
    131131
    132 const MRegisterInfo *RegInfo;
    132 const TargetRegisterInfo *RegInfo;
    133133
    134134 // PhysRegInfo - Keep track of which instruction was the last def/use of a
    135135 // physical register. This is a purely local property, because all physical
    158158 /// MMI - This field is set (via setMachineModuleInfo) by a module info
    159159 /// consumer (ex. DwarfWriter) to indicate that frame layout information
    160160 /// should be acquired. Typically, it's the responsibility of the target's
    161 /// MRegisterInfo prologue/epilogue emitting code to inform MachineModuleInfo
    162 /// of frame layouts.
    161 /// TargetRegisterInfo prologue/epilogue emitting code to inform
    162 /// MachineModuleInfo of frame layouts.
    163163 MachineModuleInfo *MMI;
    164164
    165165 /// TargetFrameInfo - Target information about frame layout.
    327327 CSInfo = CSI;
    328328 }
    329329
    330 /// getMachineModuleInfo - Used by a prologue/epilogue emitter (MRegisterInfo)
    331 /// to provide frame layout information.
    330 /// getMachineModuleInfo - Used by a prologue/epilogue
    331 /// emitter (TargetRegisterInfo) to provide frame layout information.
    332332 MachineModuleInfo *getMachineModuleInfo() const { return MMI; }
    333333
    334334 /// setMachineModuleInfo - Used by a meta info consumer (DwarfWriter) to
    2121 namespace llvm {
    2222
    2323 class TargetInstrDesc;
    24 class MRegisterInfo;
    24 class TargetRegisterInfo;
    2525
    2626 template struct ilist_traits;
    2727 template struct ilist;
    166166 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
    167167 /// add a implicit operand if it's not found. Returns true if the operand
    168168 /// exists / is added.
    169 bool addRegisterKilled(unsigned IncomingReg, const MRegisterInfo *RegInfo,
    169 bool addRegisterKilled(unsigned IncomingReg,
    170 const TargetRegisterInfo *RegInfo,
    170171 bool AddIfNotFound = false);
    171172
    172173 /// addRegisterDead - We have determined MI defined a register without a use.
    173174 /// Look for the operand that defines it and mark it as IsDead. If
    174175 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
    175176 /// true if the operand exists / is added.
    176 bool addRegisterDead(unsigned IncomingReg, const MRegisterInfo *RegInfo,
    177 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
    177178 bool AddIfNotFound = false);
    178179
    179180 /// copyKillDeadInfo - copies killed/dead information from one instr to another
    180181 void copyKillDeadInfo(MachineInstr *OldMI,
    181 const MRegisterInfo *RegInfo);
    182 const TargetRegisterInfo *RegInfo);
    182183
    183184 //
    184185 // Debugging support
    3131 public:
    3232 enum {
    3333 // The target register number for an abstract frame pointer. The value is
    34 // an arbitrary value greater than MRegisterInfo::FirstVirtualRegister.
    34 // an arbitrary value greater than TargetRegisterInfo::FirstVirtualRegister.
    3535 VirtualFP = ~0U
    3636 };
    3737 MachineLocation()
    1313 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
    1414 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
    1515
    16 #include "llvm/Target/MRegisterInfo.h"
    16 #include "llvm/Target/TargetRegisterInfo.h"
    1717 #include "llvm/ADT/BitVector.h"
    1818 #include "llvm/ADT/iterator"
    1919 #include
    2525 class MachineRegisterInfo {
    2626 /// VRegInfo - Information we keep for each virtual register. The entries in
    2727 /// this vector are actually converted to vreg numbers by adding the
    28 /// MRegisterInfo::FirstVirtualRegister delta to their index.
    28 /// TargetRegisterInfo::FirstVirtualRegister delta to their index.
    2929 ///
    3030 /// Each element in this list contains the register class of the vreg and the
    3131 /// start of the use/def list for the register.
    5353 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
    5454 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
    5555 public:
    56 explicit MachineRegisterInfo(const MRegisterInfo &MRI);
    56 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
    5757 ~MachineRegisterInfo();
    5858
    5959 //===--------------------------------------------------------------------===//
    9797 /// getRegUseDefListHead - Return the head pointer for the register use/def
    9898 /// list for the specified virtual or physical register.
    9999 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
    100 if (RegNo < MRegisterInfo::FirstVirtualRegister)
    100 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
    101101 return PhysRegUseDefLists[RegNo];
    102 RegNo -= MRegisterInfo::FirstVirtualRegister;
    102 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
    103103 return VRegInfo[RegNo].second;
    104104 }
    105105
    106106 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
    107 if (RegNo < MRegisterInfo::FirstVirtualRegister)
    107 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
    108108 return PhysRegUseDefLists[RegNo];
    109 RegNo -= MRegisterInfo::FirstVirtualRegister;
    109 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
    110110 return VRegInfo[RegNo].second;
    111111 }
    112112
    116116
    117117 /// getRegClass - Return the register class of the specified virtual register.
    118118 const TargetRegisterClass *getRegClass(unsigned Reg) {
    119 Reg -= MRegisterInfo::FirstVirtualRegister;
    119 Reg -= TargetRegisterInfo::FirstVirtualRegister;
    120120 assert(Reg < VRegInfo.size() && "Invalid vreg!");
    121121 return VRegInfo[Reg].first;
    122122 }
    141141 /// getLastVirtReg - Return the highest currently assigned virtual register.
    142142 ///
    143143 unsigned getLastVirtReg() const {
    144 return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1;
    144 return VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
    145145 }
    146146
    147147 /// getVRegDef - Return the machine instr that defines the specified virtual
    1515 #include "llvm/CodeGen/MachineInstr.h"
    1616 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
    1717 #include "llvm/CodeGen/LiveVariables.h"
    18 #include "llvm/Target/MRegisterInfo.h"
    18 #include "llvm/Target/TargetRegisterInfo.h"
    1919 #include "llvm/Support/Debug.h"
    2020
    2121 #ifndef LLVM_CODEGEN_REGISTER_COALESCER_H
    2828 class AnalysisUsage;
    2929 class LiveIntervals;
    3030 class MachineInstr;
    31 class MRegisterInfo;
    31 class TargetRegisterInfo;
    3232
    3333 /// An abstract interface for register coalescers. Coalescers must
    3434 /// implement this interface to be part of the coalescer analysis
    2121
    2222 namespace llvm {
    2323
    24 class MRegisterInfo;
    24 class TargetRegisterInfo;
    2525 class TargetInstrInfo;
    2626 class TargetRegisterClass;
    2727
    126126 }
    127127
    128128 private:
    129 const MRegisterInfo *RegInfo;
    129 const TargetRegisterInfo *RegInfo;
    130130 const TargetInstrInfo *TII;
    131131
    132132 /// CalleeSavedrRegs - A bitvector of callee saved registers for the target.
    2727 class MachineModuleInfo;
    2828 class MachineRegisterInfo;
    2929 class MachineInstr;
    30 class MRegisterInfo;
    30 class TargetRegisterInfo;
    3131 class SelectionDAG;
    3232 class SelectionDAGISel;
    3333 class TargetInstrInfo;
    242242 MachineBasicBlock *BB; // Current basic block
    243243 const TargetMachine &TM; // Target processor
    244244 const TargetInstrInfo *TII; // Target instruction information
    245 const MRegisterInfo *MRI; // Target processor register info
    245 const TargetRegisterInfo *TRI; // Target processor register info
    246246 MachineFunction *MF; // Machine function
    247247 MachineRegisterInfo &RegInfo; // Virtual/real register map
    248248 MachineConstantPool *ConstPool; // Target constant pool
    +0
    -612
    include/llvm/Target/MRegisterInfo.h less more
    None //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
    1 //
    2 // The LLVM Compiler Infrastructure
    3 //
    4 // This file is distributed under the University of Illinois Open Source
    5 // License. See LICENSE.TXT for details.
    6 //
    7 //===----------------------------------------------------------------------===//
    8 //
    9 // This file describes an abstract interface used to get information about a
    10 // target machines register file. This information is used for a variety of
    11 // purposed, especially register allocation.
    12 //
    13 //===----------------------------------------------------------------------===//
    14
    15 #ifndef LLVM_TARGET_MREGISTERINFO_H
    16 #define LLVM_TARGET_MREGISTERINFO_H
    17
    18 #include "llvm/ADT/SmallVector.h"
    19 #include "llvm/CodeGen/MachineBasicBlock.h"
    20 #include "llvm/CodeGen/ValueTypes.h"
    21 #include
    22 #include
    23
    24 namespace llvm {
    25
    26 class BitVector;
    27 class MachineFunction;
    28 class MachineInstr;
    29 class MachineMove;
    30 class RegScavenger;
    31 class SDNode;
    32 class SelectionDAG;
    33 class TargetRegisterClass;
    34 class Type;
    35
    36 /// TargetRegisterDesc - This record contains all of the information known about
    37 /// a particular register. The AliasSet field (if not null) contains a pointer
    38 /// to a Zero terminated array of registers that this register aliases. This is
    39 /// needed for architectures like X86 which have AL alias AX alias EAX.
    40 /// Registers that this does not apply to simply should set this to null.
    41 /// The SubRegs field is a zero terminated array of registers that are
    42 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
    43 /// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate
    44 /// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH,
    45 /// AL which are immediate sub-registers of AX. The SuperRegs field is a zero
    46 /// terminated array of registers that are super-registers of the specific
    47 /// register, e.g. RAX, EAX, are super-registers of AX.
    48 ///
    49 struct TargetRegisterDesc {
    50 const char *Name; // Assembly language name for the register
    51 const unsigned *AliasSet; // Register Alias Set, described above
    52 const unsigned *SubRegs; // Sub-register set, described above
    53 const unsigned *ImmSubRegs; // Immediate sub-register set, described above
    54 const unsigned *SuperRegs; // Super-register set, described above
    55 };
    56
    57 class TargetRegisterClass {
    58 public:
    59 typedef const unsigned* iterator;
    60 typedef const unsigned* const_iterator;
    61
    62 typedef const MVT::ValueType* vt_iterator;
    63 typedef const TargetRegisterClass* const * sc_iterator;
    64 private:
    65 unsigned ID;
    66 bool isSubClass;
    67 const vt_iterator VTs;
    68 const sc_iterator SubClasses;
    69 const sc_iterator SuperClasses;
    70 const sc_iterator SubRegClasses;
    71 const sc_iterator SuperRegClasses;
    72 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
    73 const int CopyCost;
    74 const iterator RegsBegin, RegsEnd;
    75 public:
    76 TargetRegisterClass(unsigned id,
    77 const MVT::ValueType *vts,
    78 const TargetRegisterClass * const *subcs,
    79 const TargetRegisterClass * const *supcs,
    80 const TargetRegisterClass * const *subregcs,
    81 const TargetRegisterClass * const *superregcs,
    82 unsigned RS, unsigned Al, int CC,
    83 iterator RB, iterator RE)
    84 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
    85 SubRegClasses(subregcs), SuperRegClasses(superregcs),
    86 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
    87 virtual ~TargetRegisterClass() {} // Allow subclasses
    88
    89 /// getID() - Return the register class ID number.
    90 ///
    91 unsigned getID() const { return ID; }
    92
    93 /// begin/end - Return all of the registers in this class.
    94 ///
    95 iterator begin() const { return RegsBegin; }
    96 iterator end() const { return RegsEnd; }
    97
    98 /// getNumRegs - Return the number of registers in this class.
    99 ///
    100 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
    101
    102 /// getRegister - Return the specified register in the class.
    103 ///
    104 unsigned getRegister(unsigned i) const {
    105 assert(i < getNumRegs() && "Register number out of range!");
    106 return RegsBegin[i];
    107 }
    108
    109 /// contains - Return true if the specified register is included in this
    110 /// register class.
    111 bool contains(unsigned Reg) const {
    112 for (iterator I = begin(), E = end(); I != E; ++I)
    113 if (*I == Reg) return true;
    114 return false;
    115 }
    116
    117 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
    118 ///
    119 bool hasType(MVT::ValueType vt) const {
    120 for(int i = 0; VTs[i] != MVT::Other; ++i)
    121 if (VTs[i] == vt)
    122 return true;
    123 return false;
    124 }
    125
    126 /// vt_begin / vt_end - Loop over all of the value types that can be
    127 /// represented by values in this register class.
    128 vt_iterator vt_begin() const {
    129 return VTs;
    130 }
    131
    132 vt_iterator vt_end() const {
    133 vt_iterator I = VTs;
    134 while (*I != MVT::Other) ++I;
    135 return I;
    136 }
    137
    138 /// hasSubClass - return true if the specified TargetRegisterClass is a
    139 /// sub-register class of this TargetRegisterClass.
    140 bool hasSubClass(const TargetRegisterClass *cs) const {
    141 for (int i = 0; SubClasses[i] != NULL; ++i)
    142 if (SubClasses[i] == cs)
    143 return true;
    144 return false;
    145 }
    146
    147 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
    148 /// this register class.
    149 sc_iterator subclasses_begin() const {
    150 return SubClasses;
    151 }
    152
    153 sc_iterator subclasses_end() const {
    154 sc_iterator I = SubClasses;
    155 while (*I != NULL) ++I;
    156 return I;
    157 }
    158
    159 /// hasSuperClass - return true if the specified TargetRegisterClass is a
    160 /// super-register class of this TargetRegisterClass.
    161 bool hasSuperClass(const TargetRegisterClass *cs) const {
    162 for (int i = 0; SuperClasses[i] != NULL; ++i)
    163 if (SuperClasses[i] == cs)
    164 return true;
    165 return false;
    166 }
    167
    168 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
    169 /// of this register class.
    170 sc_iterator superclasses_begin() const {
    171 return SuperClasses;
    172 }
    173
    174 sc_iterator superclasses_end() const {
    175 sc_iterator I = SuperClasses;
    176 while (*I != NULL) ++I;
    177 return I;
    178 }
    179
    180 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
    181 /// class of a sub-register class for this TargetRegisterClass.
    182 bool hasSubRegClass(const TargetRegisterClass *cs) const {
    183 for (int i = 0; SubRegClasses[i] != NULL; ++i)
    184 if (SubRegClasses[i] == cs)
    185 return true;
    186 return false;
    187 }
    188
    189 /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
    190 /// class of a sub-register class for this TargetRegisterClass.
    191 bool hasClassForSubReg(unsigned SubReg) const {
    192 --SubReg;
    193 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
    194 if (i == SubReg)
    195 return true;
    196 return false;
    197 }
    198
    199 /// getClassForSubReg - return theTargetRegisterClass for the sub-register
    200 /// at idx for this TargetRegisterClass.
    201 sc_iterator getClassForSubReg(unsigned SubReg) const {
    202 --SubReg;
    203 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
    204 if (i == SubReg)
    205 return &SubRegClasses[i];
    206 assert(0 && "Invalid subregister index for register class");
    207 return NULL;
    208 }
    209
    210 /// subregclasses_begin / subregclasses_end - Loop over all of
    211 /// the subregister classes of this register class.
    212 sc_iterator subregclasses_begin() const {
    213 return SubRegClasses;
    214 }
    215
    216 sc_iterator subregclasses_end() const {
    217 sc_iterator I = SubRegClasses;
    218 while (*I != NULL) ++I;
    219 return I;
    220 }
    221
    222 /// superregclasses_begin / superregclasses_end - Loop over all of
    223 /// the superregister classes of this register class.
    224 sc_iterator superregclasses_begin() const {
    225 return SuperRegClasses;
    226 }
    227
    228 sc_iterator superregclasses_end() const {
    229 sc_iterator I = SuperRegClasses;
    230 while (*I != NULL) ++I;
    231 return I;
    232 }
    233
    234 /// allocation_order_begin/end - These methods define a range of registers
    235 /// which specify the registers in this class that are valid to register
    236 /// allocate, and the preferred order to allocate them in. For example,
    237 /// callee saved registers should be at the end of the list, because it is
    238 /// cheaper to allocate caller saved registers.
    239 ///
    240 /// These methods take a MachineFunction argument, which can be used to tune
    241 /// the allocatable registers based on the characteristics of the function.
    242 /// One simple example is that the frame pointer register can be used if
    243 /// frame-pointer-elimination is performed.
    244 ///
    245 /// By default, these methods return all registers in the class.
    246 ///
    247 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
    248 return begin();
    249 }
    250 virtual iterator allocation_order_end(const MachineFunction &MF) const {
    251 return end();
    252 }
    253
    254
    255
    256 /// getSize - Return the size of the register in bytes, which is also the size
    257 /// of a stack slot allocated to hold a spilled copy of this register.
    258 unsigned getSize() const { return RegSize; }
    259
    260 /// getAlignment - Return the minimum required alignment for a register of
    261 /// this class.
    262 unsigned getAlignment() const { return Alignment; }
    263
    264 /// getCopyCost - Return the cost of copying a value between two registers in
    265 /// this class.
    266 int getCopyCost() const { return CopyCost; }
    267 };
    268
    269
    270 /// MRegisterInfo base class - We assume that the target defines a static array
    271 /// of TargetRegisterDesc objects that represent all of the machine registers
    272 /// that the target has. As such, we simply have to track a pointer to this
    273 /// array so that we can turn register number into a register descriptor.
    274 ///
    275 class MRegisterInfo {
    276 public:
    277 typedef const TargetRegisterClass * const * regclass_iterator;
    278 private:
    279 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
    280 unsigned NumRegs; // Number of entries in the array
    281
    282 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
    283
    284 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
    285 protected:
    286 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
    287 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
    288 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
    289 virtual ~MRegisterInfo();
    290 public:
    291
    292 enum { // Define some target independent constants
    293 /// NoRegister - This physical register is not a real target register. It
    294 /// is useful as a sentinal.
    295 NoRegister = 0,
    296
    297 /// FirstVirtualRegister - This is the first register number that is
    298 /// considered to be a 'virtual' register, which is part of the SSA
    299 /// namespace. This must be the same for all targets, which means that each
    300 /// target is limited to 1024 registers.
    301 FirstVirtualRegister = 1024
    302 };
    303
    304 /// isPhysicalRegister - Return true if the specified register number is in
    305 /// the physical register namespace.
    306 static bool isPhysicalRegister(unsigned Reg) {
    307 assert(Reg && "this is not a register!");
    308 return Reg < FirstVirtualRegister;
    309 }
    310
    311 /// isVirtualRegister - Return true if the specified register number is in
    312 /// the virtual register namespace.
    313 static bool isVirtualRegister(unsigned Reg) {
    314 assert(Reg && "this is not a register!");
    315 return Reg >= FirstVirtualRegister;
    316 }
    317
    318 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
    319 /// register of the given type.
    320 const TargetRegisterClass *getPhysicalRegisterRegClass(MVT::ValueType VT,
    321 unsigned Reg) const;
    322
    323 /// getAllocatableSet - Returns a bitset indexed by register number
    324 /// indicating if a register is allocatable or not. If a register class is
    325 /// specified, returns the subset for the class.
    326 BitVector getAllocatableSet(MachineFunction &MF,
    327 const TargetRegisterClass *RC = NULL) const;
    328
    329 const TargetRegisterDesc &operator[](unsigned RegNo) const {
    330 assert(RegNo < NumRegs &&
    331 "Attempting to access record for invalid register number!");
    332 return Desc[RegNo];
    333 }
    334
    335 /// Provide a get method, equivalent to [], but more useful if we have a
    336 /// pointer to this object.
    337 ///
    338 const TargetRegisterDesc &get(unsigned RegNo) const {
    339 return operator[](RegNo);
    340 }
    341
    342 /// getAliasSet - Return the set of registers aliased by the specified
    343 /// register, or a null list of there are none. The list returned is zero
    344 /// terminated.
    345 ///
    346 const unsigned *getAliasSet(unsigned RegNo) const {
    347 return get(RegNo).AliasSet;
    348 }
    349
    350 /// getSubRegisters - Return the set of registers that are sub-registers of
    351 /// the specified register, or a null list of there are none. The list
    352 /// returned is zero terminated.
    353 ///
    354 const unsigned *getSubRegisters(unsigned RegNo) const {
    355 return get(RegNo).SubRegs;
    356 }
    357
    358 /// getImmediateSubRegisters - Return the set of registers that are immediate
    359 /// sub-registers of the specified register, or a null list of there are none.
    360 /// The list returned is zero terminated.
    361 ///
    362 const unsigned *getImmediateSubRegisters(unsigned RegNo) const {
    363 return get(RegNo).ImmSubRegs;
    364 }
    365
    366 /// getSuperRegisters - Return the set of registers that are super-registers
    367 /// of the specified register, or a null list of there are none. The list
    368 /// returned is zero terminated.
    369 ///
    370 const unsigned *getSuperRegisters(unsigned RegNo) const {
    371 return get(RegNo).SuperRegs;
    372 }
    373
    374 /// getName - Return the symbolic target specific name for the specified
    375 /// physical register.
    376 const char *getName(unsigned RegNo) const {
    377 return get(RegNo).Name;
    378 }
    379
    380 /// getNumRegs - Return the number of registers this target has (useful for
    381 /// sizing arrays holding per register information)
    382 unsigned getNumRegs() const {
    383 return NumRegs;
    384 }
    385
    386 /// areAliases - Returns true if the two registers alias each other, false
    387 /// otherwise
    388 bool areAliases(unsigned regA, unsigned regB) const {
    389 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
    390 if (*Alias == regB) return true;
    391 return false;
    392 }
    393
    394 /// regsOverlap - Returns true if the two registers are equal or alias each
    395 /// other. The registers may be virtual register.
    396 bool regsOverlap(unsigned regA, unsigned regB) const {
    397 if (regA == regB)
    398 return true;
    399
    400 if (isVirtualRegister(regA) || isVirtualRegister(regB))
    401 return false;
    402 return areAliases(regA, regB);
    403 }
    404
    405 /// isSubRegister - Returns true if regB is a sub-register of regA.
    406 ///
    407 bool isSubRegister(unsigned regA, unsigned regB) const {
    408 for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR)
    409 if (*SR == regB) return true;
    410 return false;
    411 }
    412
    413 /// isSuperRegister - Returns true if regB is a super-register of regA.
    414 ///
    415 bool isSuperRegister(unsigned regA, unsigned regB) const {
    416 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
    417 if (*SR == regB) return true;
    418 return false;
    419 }
    420
    421 /// getCalleeSavedRegs - Return a null-terminated list of all of the
    422 /// callee saved registers on this target. The register should be in the
    423 /// order of desired callee-save stack frame offset. The first register is
    424 /// closed to the incoming stack pointer if stack grows down, and vice versa.
    425 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
    426 const = 0;
    427
    428 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
    429 /// register classes to spill each callee saved register with. The order and
    430 /// length of this list match the getCalleeSaveRegs() list.
    431 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
    432 const MachineFunction *MF) const =0;
    433
    434 /// getReservedRegs - Returns a bitset indexed by physical register number
    435 /// indicating if a register is a special register that has particular uses
    436 /// and should be considered unavailable at all times, e.g. SP, RA. This is
    437 /// used by register scavenger to determine what registers are free.
    438 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
    439
    440 /// getSubReg - Returns the physical register number of sub-register "Index"
    441 /// for physical register RegNo.
    442 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
    443
    444 //===--------------------------------------------------------------------===//
    445 // Register Class Information
    446 //
    447
    448 /// Register class iterators
    449 ///
    450 regclass_iterator regclass_begin() const { return RegClassBegin; }
    451 regclass_iterator regclass_end() const { return RegClassEnd; }
    452
    453 unsigned getNumRegClasses() const {
    454 return regclass_end()-regclass_begin();
    455 }
    456
    457 /// getRegClass - Returns the register class associated with the enumeration
    458 /// value. See class TargetOperandInfo.
    459 const TargetRegisterClass *getRegClass(unsigned i) const {
    460 assert(i <= getNumRegClasses() && "Register Class ID out of range");
    461 return i ? RegClassBegin[i - 1] : NULL;
    462 }
    463
    464 //===--------------------------------------------------------------------===//
    465 // Interfaces used by the register allocator and stack frame
    466 // manipulation passes to move data around between registers,
    467 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
    468 //
    469
    470 /// getCrossCopyRegClass - Returns a legal register class to copy a register
    471 /// in the specified class to or from. Returns NULL if it is possible to copy
    472 /// between a two registers of the specified class.
    473 virtual const TargetRegisterClass *
    474 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
    475 return NULL;
    476 }
    477
    478 /// reMaterialize - Re-issue the specified 'original' instruction at the
    479 /// specific location targeting a new destination register.
    480 virtual void reMaterialize(MachineBasicBlock &MBB,
    481 MachineBasicBlock::iterator MI,
    482 unsigned DestReg,
    483 const MachineInstr *Orig) const = 0;
    484
    485 /// targetHandlesStackFrameRounding - Returns true if the target is
    486 /// responsible for rounding up the stack frame (probably at emitPrologue
    487 /// time).
    488 virtual bool targetHandlesStackFrameRounding() const {
    489 return false;
    490 }
    491
    492 /// requiresRegisterScavenging - returns true if the target requires (and can
    493 /// make use of) the register scavenger.
    494 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
    495 return false;
    496 }
    497
    498 /// hasFP - Return true if the specified function should have a dedicated
    499 /// frame pointer register. For most targets this is true only if the function
    500 /// has variable sized allocas or if frame pointer elimination is disabled.
    501 virtual bool hasFP(const MachineFunction &MF) const = 0;
    502
    503 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
    504 // not required, we reserve argument space for call sites in the function
    505 // immediately on entry to the current function. This eliminates the need for
    506 // add/sub sp brackets around call sites. Returns true if the call frame is
    507 // included as part of the stack frame.
    508 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
    509 return !hasFP(MF);
    510 }
    511
    512 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
    513 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
    514 /// targets use pseudo instructions in order to abstract away the difference
    515 /// between operating with a frame pointer and operating without, through the
    516 /// use of these two instructions.
    517 ///
    518 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
    519 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
    520
    521
    522 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
    523 /// code insertion to eliminate call frame setup and destroy pseudo
    524 /// instructions (but only if the Target is using them). It is responsible
    525 /// for eliminating these instructions, replacing them with concrete
    526 /// instructions. This method need only be implemented if using call frame
    527 /// setup/destroy pseudo instructions.
    528 ///
    529 virtual void
    530 eliminateCallFramePseudoInstr(MachineFunction &MF,
    531 MachineBasicBlock &MBB,
    532 MachineBasicBlock::iterator MI) const {
    533 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
    534 "eliminateCallFramePseudoInstr must be implemented if using"
    535 " call frame setup/destroy pseudo instructions!");
    536 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
    537 }
    538
    539 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
    540 /// before PrologEpilogInserter scans the physical registers used to determine
    541 /// what callee saved registers should be spilled. This method is optional.
    542 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
    543 RegScavenger *RS = NULL) const {
    544
    545 }
    546
    547 /// processFunctionBeforeFrameFinalized - This method is called immediately
    548 /// before the specified functions frame layout (MF.getFrameInfo()) is
    549 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
    550 /// replaced with direct constants. This method is optional.
    551 ///
    552 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
    553 }
    554
    555 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
    556 /// frame indices from instructions which may use them. The instruction
    557 /// referenced by the iterator contains an MO_FrameIndex operand which must be
    558 /// eliminated by this method. This method may modify or replace the
    559 /// specified instruction, as long as it keeps the iterator pointing the the
    560 /// finished product. SPAdj is the SP adjustment due to call frame setup
    561 /// instruction. The return value is the number of instructions added to
    562 /// (negative if removed from) the basic block.
    563 ///
    564 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
    565 int SPAdj, RegScavenger *RS=NULL) const = 0;
    566
    567 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
    568 /// the function. The return value is the number of instructions
    569 /// added to (negative if removed from) the basic block (entry for prologue).
    570 ///
    571 virtual void emitPrologue(MachineFunction &MF) const = 0;
    572 virtual void emitEpilogue(MachineFunction &MF,
    573 MachineBasicBlock &MBB) const = 0;
    574
    575 //===--------------------------------------------------------------------===//
    576 /// Debug information queries.
    577
    578 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
    579 /// number. Returns -1 if there is no equivalent value. The second
    580 /// parameter allows targets to use different numberings for EH info and
    581 /// deubgging info.
    582 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
    583
    584 /// getFrameRegister - This method should return the register used as a base
    585 /// for values allocated in the current stack frame.
    586 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
    587
    588 /// getFrameIndexOffset - Returns the displacement from the frame register to
    589 /// the stack frame of the specified index.
    590 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
    591
    592 /// getRARegister - This method should return the register where the return
    593 /// address can be found.
    594 virtual unsigned getRARegister() const = 0;
    595
    596 /// getInitialFrameState - Returns a list of machine moves that are assumed
    597 /// on entry to all functions. Note that LabelID is ignored (assumed to be
    598 /// the beginning of the function.)
    599 virtual void getInitialFrameState(std::vector &Moves) const;
    600 };
    601
    602 // This is useful when building IndexedMaps keyed on virtual registers
    603 struct VirtReg2IndexFunctor : std::unary_function {
    604 unsigned operator()(unsigned Reg) const {
    605 return Reg - MRegisterInfo::FirstVirtualRegister;
    606 }
    607 };
    608
    609 } // End llvm namespace
    610
    611 #endif
    2727 class TargetLowering;
    2828 class TargetFrameInfo;
    2929 class MachineCodeEmitter;
    30 class MRegisterInfo;
    30 class TargetRegisterInfo;
    3131 class Module;
    3232 class FunctionPassManager;
    3333 class PassManager;
    139139 /// not, return null. This is kept separate from RegInfo until RegInfo has
    140140 /// details of graph coloring register allocation removed from it.
    141141 ///
    142 virtual const MRegisterInfo *getRegisterInfo() const { return 0; }
    142 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
    143143
    144144 /// getJITInfo - If this target supports a JIT, return information for it,
    145145 /// otherwise return null.
    0 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
    1 //
    2 // The LLVM Compiler Infrastructure
    3 //
    4 // This file is distributed under the University of Illinois Open Source
    5 // License. See LICENSE.TXT for details.
    6 //
    7 //===----------------------------------------------------------------------===//
    8 //
    9 // This file describes an abstract interface used to get information about a
    10 // target machines register file. This information is used for a variety of
    11 // purposed, especially register allocation.
    12 //
    13 //===----------------------------------------------------------------------===//
    14
    15 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
    16 #define LLVM_TARGET_TARGETREGISTERINFO_H
    17
    18 #include "llvm/ADT/SmallVector.h"
    19 #include "llvm/CodeGen/MachineBasicBlock.h"
    20 #include "llvm/CodeGen/ValueTypes.h"
    21 #include
    22 #include
    23
    24 namespace llvm {
    25
    26 class BitVector;
    27 class MachineFunction;
    28 class MachineInstr;
    29 class MachineMove;
    30 class RegScavenger;
    31 class SDNode;
    32 class SelectionDAG;
    33 class TargetRegisterClass;
    34 class Type;
    35
    36 /// TargetRegisterDesc - This record contains all of the information known about
    37 /// a particular register. The AliasSet field (if not null) contains a pointer
    38 /// to a Zero terminated array of registers that this register aliases. This is
    39 /// needed for architectures like X86 which have AL alias AX alias EAX.
    40 /// Registers that this does not apply to simply should set this to null.
    41 /// The SubRegs field is a zero terminated array of registers that are
    42 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
    43 /// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate
    44 /// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH,
    45 /// AL which are immediate sub-registers of AX. The SuperRegs field is a zero
    46 /// terminated array of registers that are super-registers of the specific
    47 /// register, e.g. RAX, EAX, are super-registers of AX.
    48 ///
    49 struct TargetRegisterDesc {
    50 const char *Name; // Assembly language name for the register
    51 const unsigned *AliasSet; // Register Alias Set, described above
    52 const unsigned *SubRegs; // Sub-register set, described above
    53 const unsigned *ImmSubRegs; // Immediate sub-register set, described above
    54 const unsigned *SuperRegs; // Super-register set, described above
    55 };
    56
    57 class TargetRegisterClass {
    58 public:
    59 typedef const unsigned* iterator;
    60 typedef const unsigned* const_iterator;
    61
    62 typedef const MVT::ValueType* vt_iterator;
    63 typedef const TargetRegisterClass* const * sc_iterator;
    64 private:
    65 unsigned ID;
    66 bool isSubClass;
    67 const vt_iterator VTs;
    68 const sc_iterator SubClasses;
    69 const sc_iterator SuperClasses;
    70 const sc_iterator SubRegClasses;
    71 const sc_iterator SuperRegClasses;
    72 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
    73 const int CopyCost;
    74 const iterator RegsBegin, RegsEnd;
    75 public:
    76 TargetRegisterClass(unsigned id,
    77 const MVT::ValueType *vts,
    78 const TargetRegisterClass * const *subcs,
    79 const TargetRegisterClass * const *supcs,
    80 const TargetRegisterClass * const *subregcs,
    81 const TargetRegisterClass * const *superregcs,
    82 unsigned RS, unsigned Al, int CC,
    83 iterator RB, iterator RE)
    84 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
    85 SubRegClasses(subregcs), SuperRegClasses(superregcs),
    86 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
    87 virtual ~TargetRegisterClass() {} // Allow subclasses
    88
    89 /// getID() - Return the register class ID number.
    90 ///
    91 unsigned getID() const { return ID; }
    92
    93 /// begin/end - Return all of the registers in this class.
    94 ///
    95 iterator begin() const { return RegsBegin; }
    96 iterator end() const { return RegsEnd; }
    97
    98 /// getNumRegs - Return the number of registers in this class.
    99 ///
    100 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
    101
    102 /// getRegister - Return the specified register in the class.
    103 ///
    104 unsigned getRegister(unsigned i) const {
    105 assert(i < getNumRegs() && "Register number out of range!");
    106 return RegsBegin[i];
    107 }
    108
    109 /// contains - Return true if the specified register is included in this
    110 /// register class.
    111 bool contains(unsigned Reg) const {
    112 for (iterator I = begin(), E = end(); I != E; ++I)
    113 if (*I == Reg) return true;
    114 return false;
    115 }
    116
    117 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
    118 ///
    119 bool hasType(MVT::ValueType vt) const {
    120 for(int i = 0; VTs[i] != MVT::Other; ++i)
    121 if (VTs[i] == vt)
    122 return true;
    123 return false;
    124 }
    125
    126 /// vt_begin / vt_end - Loop over all of the value types that can be
    127 /// represented by values in this register class.
    128 vt_iterator vt_begin() const {
    129 return VTs;
    130 }
    131
    132 vt_iterator vt_end() const {
    133 vt_iterator I = VTs;
    134 while (*I != MVT::Other) ++I;
    135 return I;
    136 }
    137
    138 /// hasSubClass - return true if the specified TargetRegisterClass is a
    139 /// sub-register class of this TargetRegisterClass.
    140 bool hasSubClass(const TargetRegisterClass *cs) const {
    141 for (int i = 0; SubClasses[i] != NULL; ++i)
    142 if (SubClasses[i] == cs)
    143 return true;
    144 return false;
    145 }
    146
    147 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
    148 /// this register class.
    149 sc_iterator subclasses_begin() const {
    150 return SubClasses;
    151 }
    152
    153 sc_iterator subclasses_end() const {
    154 sc_iterator I = SubClasses;
    155 while (*I != NULL) ++I;
    156 return I;
    157 }
    158
    159 /// hasSuperClass - return true if the specified TargetRegisterClass is a
    160 /// super-register class of this TargetRegisterClass.
    161 bool hasSuperClass(const TargetRegisterClass *cs) const {
    162 for (int i = 0; SuperClasses[i] != NULL; ++i)
    163 if (SuperClasses[i] == cs)
    164 return true;
    165 return false;
    166 }
    167
    168 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
    169 /// of this register class.
    170 sc_iterator superclasses_begin() const {
    171 return SuperClasses;
    172 }
    173
    174 sc_iterator superclasses_end() const {
    175 sc_iterator I = SuperClasses;
    176 while (*I != NULL) ++I;
    177 return I;
    178 }
    179
    180 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
    181 /// class of a sub-register class for this TargetRegisterClass.
    182 bool hasSubRegClass(const TargetRegisterClass *cs) const {
    183 for (int i = 0; SubRegClasses[i] != NULL; ++i)
    184 if (SubRegClasses[i] == cs)
    185 return true;
    186 return false;
    187 }
    188
    189 /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
    190 /// class of a sub-register class for this TargetRegisterClass.
    191 bool hasClassForSubReg(unsigned SubReg) const {
    192 --SubReg;
    193 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
    194 if (i == SubReg)
    195 return true;
    196 return false;
    197 }
    198
    199 /// getClassForSubReg - return theTargetRegisterClass for the sub-register
    200 /// at idx for this TargetRegisterClass.
    201 sc_iterator getClassForSubReg(unsigned SubReg) const {
    202 --SubReg;
    203 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
    204 if (i == SubReg)
    205 return &SubRegClasses[i];
    206 assert(0 && "Invalid subregister index for register class");
    207 return NULL;
    208 }
    209
    210 /// subregclasses_begin / subregclasses_end - Loop over all of
    211 /// the subregister classes of this register class.
    212 sc_iterator subregclasses_begin() const {
    213 return SubRegClasses;
    214 }
    215
    216 sc_iterator subregclasses_end() const {
    217 sc_iterator I = SubRegClasses;
    218 while (*I != NULL) ++I;
    219 return I;
    220 }
    221
    222 /// superregclasses_begin / superregclasses_end - Loop over all of
    223 /// the superregister classes of this register class.
    224 sc_iterator superregclasses_begin() const {
    225 return SuperRegClasses;
    226 }
    227
    228 sc_iterator superregclasses_end() const {
    229 sc_iterator I = SuperRegClasses;
    230 while (*I != NULL) ++I;
    231 return I;
    232 }
    233
    234 /// allocation_order_begin/end - These methods define a range of registers
    235 /// which specify the registers in this class that are valid to register
    236 /// allocate, and the preferred order to allocate them in. For example,
    237 /// callee saved registers should be at the end of the list, because it is
    238 /// cheaper to allocate caller saved registers.
    239 ///
    240 /// These methods take a MachineFunction argument, which can be used to tune
    241 /// the allocatable registers based on the characteristics of the function.
    242 /// One simple example is that the frame pointer register can be used if
    243 /// frame-pointer-elimination is performed.
    244 ///
    245 /// By default, these methods return all registers in the class.
    246 ///
    247 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
    248 return begin();
    249 }
    250 virtual iterator allocation_order_end(const MachineFunction &MF) const {
    251 return end();
    252 }
    253
    254
    255
    256 /// getSize - Return the size of the register in bytes, which is also the size
    257 /// of a stack slot allocated to hold a spilled copy of this register.
    258 unsigned getSize() const { return RegSize; }
    259
    260 /// getAlignment - Return the minimum required alignment for a register of
    261 /// this class.
    262 unsigned getAlignment() const { return Alignment; }
    263
    264 /// getCopyCost - Return the cost of copying a value between two registers in
    265 /// this class.
    266 int getCopyCost() const { return CopyCost; }
    267 };
    268
    269
    270 /// TargetRegisterInfo base class - We assume that the target defines a static
    271 /// array of TargetRegisterDesc objects that represent all of the machine
    272 /// registers that the target has. As such, we simply have to track a pointer
    273 /// to this array so that we can turn register number into a register
    274 /// descriptor.
    275 ///
    276 class TargetRegisterInfo {
    277 public:
    278 typedef const TargetRegisterClass * const * regclass_iterator;
    279 private:
    280 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
    281 unsigned NumRegs; // Number of entries in the array
    282
    283 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
    284
    285 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
    286 protected:
    287 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
    288 regclass_iterator RegClassBegin,
    289 regclass_iterator RegClassEnd,
    290 int CallFrameSetupOpcode = -1,
    291 int CallFrameDestroyOpcode = -1);
    292 virtual ~TargetRegisterInfo();
    293 public:
    294
    295 enum { // Define some target independent constants
    296 /// NoRegister - This physical register is not a real target register. It
    297 /// is useful as a sentinal.
    298 NoRegister = 0,
    299
    300 /// FirstVirtualRegister - This is the first register number that is
    301 /// considered to be a 'virtual' register, which is part of the SSA
    302 /// namespace. This must be the same for all targets, which means that each
    303 /// target is limited to 1024 registers.
    304 FirstVirtualRegister = 1024
    305 };
    306
    307 /// isPhysicalRegister - Return true if the specified register number is in
    308 /// the physical register namespace.
    309 static bool isPhysicalRegister(unsigned Reg) {
    310 assert(Reg && "this is not a register!");
    311 return Reg < FirstVirtualRegister;
    312 }
    313
    314 /// isVirtualRegister - Return true if the specified register number is in
    315 /// the virtual register namespace.
    316 static bool isVirtualRegister(unsigned Reg) {
    317 assert(Reg && "this is not a register!");
    318 return Reg >= FirstVirtualRegister;
    319 }
    320
    321 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
    322 /// register of the given type.
    323 const TargetRegisterClass *getPhysicalRegisterRegClass(MVT::ValueType VT,
    324 unsigned Reg) const;
    325
    326 /// getAllocatableSet - Returns a bitset indexed by register number
    327 /// indicating if a register is allocatable or not. If a register class is
    328 /// specified, returns the subset for the class.
    329 BitVector getAllocatableSet(MachineFunction &MF,
    330 const TargetRegisterClass *RC = NULL) const;
    331
    332 const TargetRegisterDesc &operator[](unsigned RegNo) const {
    333 assert(RegNo < NumRegs &&
    334 "Attempting to access record for invalid register number!");
    335 return Desc[RegNo];
    336 }
    337
    338 /// Provide a get method, equivalent to [], but more useful if we have a
    339 /// pointer to this object.
    340 ///
    341 const TargetRegisterDesc &get(unsigned RegNo) const {
    342 return operator[](RegNo);
    343 }
    344
    345 /// getAliasSet - Return the set of registers aliased by the specified
    346 /// register, or a null list of there are none. The list returned is zero
    347 /// terminated.
    348 ///
    349 const unsigned *getAliasSet(unsigned RegNo) const {
    350 return get(RegNo).AliasSet;
    351 }
    352
    353 /// getSubRegisters - Return the set of registers that are sub-registers of
    354 /// the specified register, or a null list of there are none. The list
    355 /// returned is zero terminated.
    356 ///
    357 const unsigned *getSubRegisters(unsigned RegNo) const {
    358 return get(RegNo).SubRegs;
    359 }
    360
    361 /// getImmediateSubRegisters - Return the set of registers that are immediate
    362 /// sub-registers of the specified register, or a null list of there are none.
    363 /// The list returned is zero terminated.
    364 ///
    365 const unsigned *getImmediateSubRegisters(unsigned RegNo) const {
    366 return get(RegNo).ImmSubRegs;
    367 }
    368
    369 /// getSuperRegisters - Return the set of registers that are super-registers
    370 /// of the specified register, or a null list of there are none. The list
    371 /// returned is zero terminated.
    372 ///
    373 const unsigned *getSuperRegisters(unsigned RegNo) const {
    374 return get(RegNo).SuperRegs;
    375 }
    376
    377 /// getName - Return the symbolic target specific name for the specified
    378 /// physical register.
    379 const char *getName(unsigned RegNo) const {
    380 return get(RegNo).Name;
    381 }
    382
    383 /// getNumRegs - Return the number of registers this target has (useful for
    384 /// sizing arrays holding per register information)
    385 unsigned getNumRegs() const {
    386 return NumRegs;
    387 }
    388
    389 /// areAliases - Returns true if the two registers alias each other, false
    390 /// otherwise
    391 bool areAliases(unsigned regA, unsigned regB) const {
    392 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
    393 if (*Alias == regB) return true;
    394 return false;
    395 }
    396
    397 /// regsOverlap - Returns true if the two registers are equal or alias each
    398 /// other. The registers may be virtual register.
    399 bool regsOverlap(unsigned regA, unsigned regB) const {
    400 if (regA == regB)
    401 return true;
    402
    403 if (isVirtualRegister(regA) || isVirtualRegister(regB))
    404 return false;
    405 return areAliases(regA, regB);
    406 }
    407
    408 /// isSubRegister - Returns true if regB is a sub-register of regA.
    409 ///
    410 bool isSubRegister(unsigned regA, unsigned regB) const {
    411 for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR)
    412 if (*SR == regB) return true;
    413 return false;
    414 }
    415
    416 /// isSuperRegister - Returns true if regB is a super-register of regA.
    417 ///
    418 bool isSuperRegister(unsigned regA, unsigned regB) const {
    419 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
    420 if (*SR == regB) return true;
    421 return false;
    422 }
    423
    424 /// getCalleeSavedRegs - Return a null-terminated list of all of the
    425 /// callee saved registers on this target. The register should be in the
    426 /// order of desired callee-save stack frame offset. The first register is
    427 /// closed to the incoming stack pointer if stack grows down, and vice versa.
    428 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
    429 const = 0;
    430
    431 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
    432 /// register classes to spill each callee saved register with. The order and
    433 /// length of this list match the getCalleeSaveRegs() list.
    434 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
    435 const MachineFunction *MF) const =0;
    436
    437 /// getReservedRegs - Returns a bitset indexed by physical register number
    438 /// indicating if a register is a special register that has particular uses
    439 /// and should be considered unavailable at all times, e.g. SP, RA. This is
    440 /// used by register scavenger to determine what registers are free.
    441 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
    442
    443 /// getSubReg - Returns the physical register number of sub-register "Index"
    444 /// for physical register RegNo.
    445 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
    446
    447 //===--------------------------------------------------------------------===//
    448 // Register Class Information
    449 //
    450
    451 /// Register class iterators
    452 ///
    453 regclass_iterator regclass_begin() const { return RegClassBegin; }
    454 regclass_iterator regclass_end() const { return RegClassEnd; }
    455
    456 unsigned getNumRegClasses() const {
    457 return regclass_end()-regclass_begin();
    458 }
    459
    460 /// getRegClass - Returns the register class associated with the enumeration
    461 /// value. See class TargetOperandInfo.
    462 const TargetRegisterClass *getRegClass(unsigned i) const {
    463 assert(i <= getNumRegClasses() && "Register Class ID out of range");
    464 return i ? RegClassBegin[i - 1] : NULL;
    465 }
    466
    467 //===--------------------------------------------------------------------===//
    468 // Interfaces used by the register allocator and stack frame
    469 // manipulation passes to move data around between registers,
    470 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
    471 //
    472
    473 /// getCrossCopyRegClass - Returns a legal register class to copy a register
    474 /// in the specified class to or from. Returns NULL if it is possible to copy
    475 /// between a two registers of the specified class.
    476 virtual const TargetRegisterClass *
    477 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
    478 return NULL;
    479 }
    480
    481 /// reMaterialize - Re-issue the specified 'original' instruction at the
    482 /// specific location targeting a new destination register.
    483 virtual void reMaterialize(MachineBasicBlock &MBB,
    484 MachineBasicBlock::iterator MI,
    485 unsigned DestReg,
    486 const MachineInstr *Orig) const = 0;
    487
    488 /// targetHandlesStackFrameRounding - Returns true if the target is
    489 /// responsible for rounding up the stack frame (probably at emitPrologue
    490 /// time).
    491 virtual bool targetHandlesStackFrameRounding() const {
    492 return false;
    493 }
    494
    495 /// requiresRegisterScavenging - returns true if the target requires (and can
    496 /// make use of) the register scavenger.
    497 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
    498 return false;
    499 }
    500
    501 /// hasFP - Return true if the specified function should have a dedicated
    502 /// frame pointer register. For most targets this is true only if the function
    503 /// has variable sized allocas or if frame pointer elimination is disabled.
    504 virtual bool hasFP(const MachineFunction &MF) const = 0;
    505
    506 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
    507 // not required, we reserve argument space for call sites in the function
    508 // immediately on entry to the current function. This eliminates the need for
    509 // add/sub sp brackets around call sites. Returns true if the call frame is
    510 // included as part of the stack frame.
    511 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
    512 return !hasFP(MF);
    513 }
    514
    515 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
    516 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
    517 /// targets use pseudo instructions in order to abstract away the difference
    518 /// between operating with a frame pointer and operating without, through the
    519 /// use of these two instructions.
    520 ///
    521 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
    522 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
    523
    524
    525 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
    526 /// code insertion to eliminate call frame setup and destroy pseudo
    527 /// instructions (but only if the Target is using them). It is responsible
    528 /// for eliminating these instructions, replacing them with concrete
    529 /// instructions. This method need only be implemented if using call frame
    530 /// setup/destroy pseudo instructions.
    531 ///
    532 virtual void
    533 eliminateCallFramePseudoInstr(MachineFunction &MF,
    534 MachineBasicBlock &MBB,
    535 MachineBasicBlock::iterator MI) const {
    536 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
    537 "eliminateCallFramePseudoInstr must be implemented if using"
    538 " call frame setup/destroy pseudo instructions!");
    539 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
    540 }
    541
    542 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
    543 /// before PrologEpilogInserter scans the physical registers used to determine
    544 /// what callee saved registers should be spilled. This method is optional.
    545 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
    546 RegScavenger *RS = NULL) const {
    547
    548 }
    549
    550 /// processFunctionBeforeFrameFinalized - This method is called immediately
    551 /// before the specified functions frame layout (MF.getFrameInfo()) is
    552 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
    553 /// replaced with direct constants. This method is optional.
    554 ///
    555 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
    556 }
    557
    558 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
    559 /// frame indices from instructions which may use them. The instruction
    560 /// referenced by the iterator contains an MO_FrameIndex operand which must be
    561 /// eliminated by this method. This method may modify or replace the
    562 /// specified instruction, as long as it keeps the iterator pointing the the
    563 /// finished product. SPAdj is the SP adjustment due to call frame setup
    564 /// instruction. The return value is the number of instructions added to
    565 /// (negative if removed from) the basic block.
    566 ///
    567 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
    568 int SPAdj, RegScavenger *RS=NULL) const = 0;
    569
    570 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
    571 /// the function. The return value is the number of instructions
    572 /// added to (negative if removed from) the basic block (entry for prologue).
    573 ///
    574 virtual void emitPrologue(MachineFunction &MF) const = 0;
    575 virtual void emitEpilogue(MachineFunction &MF,
    576 MachineBasicBlock &MBB) const = 0;
    577
    578 //===--------------------------------------------------------------------===//
    579 /// Debug information queries.
    580
    581 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
    582 /// number. Returns -1 if there is no equivalent value. The second
    583 /// parameter allows targets to use different numberings for EH info and
    584 /// deubgging info.
    585 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
    586
    587 /// getFrameRegister - This method should return the register used as a base
    588 /// for values allocated in the current stack frame.
    589 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
    590
    591 /// getFrameIndexOffset - Returns the displacement from the frame register to
    592 /// the stack frame of the specified index.
    593 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
    594
    595 /// getRARegister - This method should return the register where the return
    596 /// address can be found.
    597 virtual unsigned getRARegister() const = 0;
    598
    599 /// getInitialFrameState - Returns a list of machine moves that are assumed
    600 /// on entry to all functions. Note that LabelID is ignored (assumed to be
    601 /// the beginning of the function.)
    602 virtual void getInitialFrameState(std::vector &Moves) const;
    603 };
    604
    605 // This is useful when building IndexedMaps keyed on virtual registers
    606 struct VirtReg2IndexFunctor : std::unary_function {
    607 unsigned operator()(unsigned Reg) const {
    608 return Reg - TargetRegisterInfo::FirstVirtualRegister;
    609 }
    610 };
    611
    612 } // End llvm namespace
    613
    614 #endif
    2323 #include "llvm/CodeGen/RegisterScavenging.h"
    2424 #include "llvm/Target/TargetInstrInfo.h"
    2525 #include "llvm/Target/TargetMachine.h"
    26 #include "llvm/Target/MRegisterInfo.h"
    26 #include "llvm/Target/TargetRegisterInfo.h"
    2727 #include "llvm/Support/CommandLine.h"
    2828 #include "llvm/Support/Debug.h"
    2929 #include "llvm/ADT/Statistic.h"
    7171 MachineBasicBlock::iterator BBI1);
    7272
    7373 std::vector > MergePotentials;
    74 const MRegisterInfo *RegInfo;
    74 const TargetRegisterInfo *RegInfo;
    7575 RegScavenger *RS;
    7676 // Branch optzn.
    7777 bool OptimizeBranches(MachineFunction &MF);
    2929 #include "llvm/Support/Mangler.h"
    3030 #include "llvm/System/Path.h"
    3131 #include "llvm/Target/TargetAsmInfo.h"
    32 #include "llvm/Target/MRegisterInfo.h"
    32 #include "llvm/Target/TargetRegisterInfo.h"
    3333 #include "llvm/Target/TargetData.h"
    3434 #include "llvm/Target/TargetFrameInfo.h"
    3535 #include "llvm/Target/TargetInstrInfo.h"
    781781 const TargetData *TD;
    782782
    783783 /// RI - Register Information.
    784 const MRegisterInfo *RI;
    784 const TargetRegisterInfo *RI;
    785785
    786786 /// M - Current module.
    787787 ///
    2121 #include "llvm/ADT/SmallSet.h"
    2222 #include "llvm/ADT/STLExtras.h"
    2323 #include "llvm/Support/Streams.h"
    24 #include "llvm/Target/MRegisterInfo.h"
    24 #include "llvm/Target/TargetRegisterInfo.h"
    2525 #include
    2626 #include
    2727 using namespace llvm;
    588588 cerr << *this << "\n";
    589589 }
    590590
    591 void LiveInterval::print(std::ostream &OS, const MRegisterInfo *MRI) const {
    592 if (MRI && MRegisterInfo::isPhysicalRegister(reg))
    593 OS << MRI->getName(reg);
    591 void LiveInterval::print(std::ostream &OS,
    592 const TargetRegisterInfo *TRI) const {
    593 if (TRI && TargetRegisterInfo::isPhysicalRegister(reg))
    594 OS << TRI->getName(reg);
    594595 else
    595596 OS << "%reg" << reg;
    596597
    2424 #include "llvm/CodeGen/MachineLoopInfo.h"
    2525 #include "llvm/CodeGen/MachineRegisterInfo.h"
    2626 #include "llvm/CodeGen/Passes.h"
    27 #include "llvm/Target/MRegisterInfo.h"
    27 #include "llvm/Target/TargetRegisterInfo.h"
    2828 #include "llvm/Target/TargetInstrInfo.h"
    2929 #include "llvm/Target/TargetMachine.h"
    3030 #include "llvm/Support/CommandLine.h"
    9999 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
    100100 mf_ = &fn;
    101101 tm_ = &fn.getTarget();
    102 mri_ = tm_->getRegisterInfo();
    102 tri_ = tm_->getRegisterInfo();
    103103 tii_ = tm_->getInstrInfo();
    104104 lv_ = &getAnalysis();
    105 allocatableRegs_ = mri_->getAllocatableSet(fn);
    105 allocatableRegs_ = tri_->getAllocatableSet(fn);
    106106
    107107 // Number MachineInstrs and MachineBasicBlocks.
    108108 // Initialize MBB indexes to a sentinal.
    133133
    134134 DOUT << "********** INTERVALS **********\n";
    135135 for (iterator I = begin(), E = end(); I != E; ++I) {
    136 I->second.print(DOUT, mri_);
    136 I->second.print(DOUT, tri_);
    137137 DOUT << "\n";
    138138 }
    139139
    146146 void LiveIntervals::print(std::ostream &O, const Module* ) const {
    147147 O << "********** INTERVALS **********\n";
    148148 for (const_iterator I = begin(), E = end(); I != E; ++I) {
    149 I->second.print(DOUT, mri_);
    149 I->second.print(DOUT, tri_);
    150150 DOUT << "\n";
    151151 }
    152152
    187187 unsigned PhysReg = mop.getReg();
    188188 if (PhysReg == 0 || PhysReg == li.reg)
    189189 continue;
    190 if (MRegisterInfo::isVirtualRegister(PhysReg)) {
    190 if (TargetRegisterInfo::isVirtualRegister(PhysReg)) {
    191191 if (!vrm.hasPhys(PhysReg))
    192192 continue;
    193193 PhysReg = vrm.getPhys(PhysReg);
    194194 }
    195 if (PhysReg && mri_->regsOverlap(PhysReg, reg))
    195 if (PhysReg && tri_->regsOverlap(PhysReg, reg))
    196196 return true;
    197197 }
    198198 }
    202202 }
    203203
    204204 void LiveIntervals::printRegName(unsigned reg) const {
    205 if (MRegisterInfo::isPhysicalRegister(reg))
    206 cerr << mri_->getName(reg);
    205 if (TargetRegisterInfo::isPhysicalRegister(reg))
    206 cerr << tri_->getName(reg);
    207207 else
    208208 cerr << "%reg" << reg;
    209209 }
    346346 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, OldValNo));
    347347
    348348 DOUT << " RESULT: ";
    349 interval.print(DOUT, mri_);
    349 interval.print(DOUT, tri_);
    350350
    351351 } else {
    352352 // Otherwise, this must be because of phi elimination. If this is the
    362362 unsigned Start = getMBBStartIdx(Killer->getParent());
    363363 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
    364364 DOUT << " Removing [" << Start << "," << End << "] from: ";
    365 interval.print(DOUT, mri_); DOUT << "\n";
    365 interval.print(DOUT, tri_); DOUT << "\n";
    366366 interval.removeRange(Start, End);
    367367 interval.addKill(VNI, Start);
    368368 VNI->hasPHIKill = true;
    369 DOUT << " RESULT: "; interval.print(DOUT, mri_);
    369 DOUT << " RESULT: "; interval.print(DOUT, tri_);
    370370
    371371 // Replace the interval with one of a NEW value number. Note that this
    372372 // value number isn't actually defined by an instruction, weird huh? :)
    374374 DOUT << " replace range with " << LR;
    375375 interval.addRange(LR);
    376376 interval.addKill(LR.valno, End);
    377 DOUT << " RESULT: "; interval.print(DOUT, mri_);
    377 DOUT << " RESULT: "; interval.print(DOUT, tri_);
    378378 }
    379379
    380380 // In the case of PHI elimination, each variable definition is only
    469469 MachineBasicBlock::iterator MI,
    470470 unsigned MIIdx,
    471471 unsigned reg) {
    472 if (MRegisterInfo::isVirtualRegister(reg))
    472 if (TargetRegisterInfo::isVirtualRegister(reg))
    473473 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
    474474 else if (allocatableRegs_[reg]) {
    475475 unsigned SrcReg, DstReg;
    479479 SrcReg = 0;
    480480 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
    481481 // Def of a register also defines its sub-registers.
    482 for (const unsigned* AS = mri_->getSubRegisters(reg); *AS; ++AS)
    482 for (const unsigned* AS = tri_->getSubRegisters(reg); *AS; ++AS)
    483483 // Avoid processing some defs more than once.
    484484 if (!MI->findRegisterDefOperand(*AS))
    485485 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
    556556 LE = MBB->livein_end(); LI != LE; ++LI) {
    557557 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
    558558 // Multiple live-ins can alias the same register.
    559 for (const unsigned* AS = mri_->getSubRegisters(*LI); *AS; ++AS)
    559 for (const unsigned* AS = tri_->getSubRegisters(*LI); *AS; ++AS)
    560560 if (!hasInterval(*AS))
    561561 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS),
    562562 true);
    596596
    597597
    598598 LiveInterval LiveIntervals::createInterval(unsigned reg) {
    599 float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
    599 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
    600600 HUGE_VALF : 0.0F;
    601601 return LiveInterval(reg, Weight);
    602602 }
    716716 if (lv_)
    717717 lv_->instructionChanged(MI, fmi);
    718718 else
    719 fmi->copyKillDeadInfo(MI, mri_);
    719 fmi->copyKillDeadInfo(MI, tri_);
    720720 MachineBasicBlock &MBB = *MI->getParent();
    721721 if (isSS && !mf_->getFrameInfo()->isImmutableObjectIndex(Slot))
    722722 vrm.virtFolded(Reg, MI, fmi, (VirtRegMap::ModRef)MRInfo);
    788788 continue;
    789789 unsigned Reg = mop.getReg();
    790790 unsigned RegI = Reg;
    791 if (Reg == 0 || MRegisterInfo::isPhysicalRegister(Reg))
    791 if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg))
    792792 continue;
    793793 if (Reg != li.reg)
    794794 continue;
    839839 if (!MOj.isRegister())
    840840 continue;
    841841 unsigned RegJ = MOj.getReg();
    842 if (RegJ == 0 || MRegisterInfo::isPhysicalRegister(RegJ))
    842 if (RegJ == 0 || TargetRegisterInfo::isPhysicalRegister(RegJ))
    843843 continue;
    844844 if (RegJ == RegI) {
    845845 Ops.push_back(j);
    938938 }
    939939
    940940 DOUT << "\t\t\t\tAdded new interval: ";
    941 nI.print(DOUT, mri_);
    941 nI.print(DOUT, tri_);
    942942 DOUT << '\n';
    943943 }
    944944 return CanFold;
    11801180 "attempt to spill already spilled interval!");
    11811181
    11821182 DOUT << "\t\t\t\tadding intervals for spills for interval: ";
    1183 li.print(DOUT, mri_);
    1183 li.print(DOUT, tri_);
    11841184 DOUT << '\n';
    11851185
    11861186 // Each bit specify whether it a spill is required in the MBB.
    2828 #include "llvm/CodeGen/LiveVariables.h"
    2929 #include "llvm/CodeGen/MachineInstr.h"
    3030 #include "llvm/CodeGen/MachineRegisterInfo.h"
    31 #include "llvm/Target/MRegisterInfo.h"
    31 #include "llvm/Target/TargetRegisterInfo.h"
    3232 #include "llvm/Target/TargetInstrInfo.h"
    3333 #include "llvm/Target/TargetMachine.h"
    3434 #include "llvm/ADT/DepthFirstIterator.h"
    5959 }
    6060
    6161 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
    62 assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
    62 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
    6363 "getVarInfo: not a virtual register!");
    64 RegIdx -= MRegisterInfo::FirstVirtualRegister;
    64 RegIdx -= TargetRegisterInfo::FirstVirtualRegister;
    6565 if (RegIdx >= VirtRegInfo.size()) {
    6666 if (RegIdx >= 2*VirtRegInfo.size())
    6767 VirtRegInfo.resize(RegIdx*2);
    7979 MachineOperand &MO = MI->getOperand(i);
    8080 if (MO.isRegister() && MO.isKill()) {
    8181 if ((MO.getReg() == Reg) ||
    82 (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
    83 MRegisterInfo::isPhysicalRegister(Reg) &&
    82 (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
    83 TargetRegisterInfo::isPhysicalRegister(Reg) &&
    8484 RegInfo->isSubRegister(MO.getReg(), Reg)))
    8585 return true;
    8686 }
    9393 MachineOperand &MO = MI->getOperand(i);
    9494 if (MO.isRegister() && MO.isDead()) {
    9595 if ((MO.getReg() == Reg) ||
    96 (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
    97 MRegisterInfo::isPhysicalRegister(Reg) &&
    96 (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
    97 TargetRegisterInfo::isPhysicalRegister(Reg) &&
    9898 RegInfo->isSubRegister(MO.getReg(), Reg)))
    9999 return true;
    100100 }
    398398 // Mark live-in registers as live-in.
    399399 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
    400400 EE = MBB->livein_end(); II != EE; ++II) {
    401 assert(MRegisterInfo::isPhysicalRegister(*II) &&
    401 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
    402402 "Cannot have a live-in virtual register!");
    403403 HandlePhysRegDef(*II, 0);
    404404 }
    420420 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
    421421 MachineOperand &MO = MI->getOperand(i);
    422422 if (MO.isRegister() && MO.isUse() && MO.getReg()) {
    423 if (MRegisterInfo::isVirtualRegister(MO.getReg())){
    423 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())){
    424424 HandleVirtRegUse(MO.getReg(), MBB, MI);
    425 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
    425 } else if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
    426426 !ReservedRegisters[MO.getReg()]) {
    427427 HandlePhysRegUse(MO.getReg(), MI);
    428428 }
    433433 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
    434434 MachineOperand &MO = MI->getOperand(i);
    435435 if (MO.isRegister() && MO.isDef() && MO.getReg()) {
    436 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
    436 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
    437437 VarInfo &VRInfo = getVarInfo(MO.getReg());
    438438 if (VRInfo.AliveBlocks.none())
    439439 // If vr is not alive in any block, then defaults to dead.
    440440 VRInfo.Kills.push_back(MI);
    441 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
    441 } else if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
    442442 !ReservedRegisters[MO.getReg()]) {
    443443 HandlePhysRegDef(MO.getReg(), MI);
    444444 }
    468468 for (MachineRegisterInfo::liveout_iterator
    469469 I = MF->getRegInfo().liveout_begin(),
    470470 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
    471 assert(MRegisterInfo::isPhysicalRegister(*I) &&
    471 assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
    472472 "Cannot have a live-in virtual register!");
    473473 HandlePhysRegUse(*I, Ret);
    474474 // Add live-out registers as implicit uses.
    497497 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
    498498 for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) {
    499499 if (VirtRegInfo[i].Kills[j] == MRI.getVRegDef(i +
    500 MRegisterInfo::FirstVirtualRegister))
    500 TargetRegisterInfo::FirstVirtualRegister))
    501501 VirtRegInfo[i].Kills[j]->addRegisterDead(i +
    502 MRegisterInfo::FirstVirtualRegister,
    502 TargetRegisterInfo::FirstVirtualRegister,
    503503 RegInfo);
    504504 else
    505505 VirtRegInfo[i].Kills[j]->addRegisterKilled(i +
    506 MRegisterInfo::FirstVirtualRegister,
    506 TargetRegisterInfo::FirstVirtualRegister,
    507507 RegInfo);
    508508 }
    509509
    535535 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
    536536 MachineOperand &MO = OldMI->getOperand(i);
    537537 if (MO.isRegister() && MO.getReg() &&
    538 MRegisterInfo::isVirtualRegister(MO.getReg())) {
    538 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
    539539 unsigned Reg = MO.getReg();
    540540 VarInfo &VI = getVarInfo(Reg);
    541541 if (MO.isDef()) {
    563563 if (MO.isRegister() && MO.isKill()) {
    564564 MO.setIsKill(false);
    565565 unsigned Reg = MO.getReg();
    566 if (MRegisterInfo::isVirtualRegister(Reg)) {
    566 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
    567567 bool removed = getVarInfo(Reg).removeKill(MI);
    568568 assert(removed && "kill not in register's VarInfo?");
    569569 }
    579579 if (MO.isRegister() && MO.isDead()) {
    580580 MO.setIsDead(false);
    581581 unsigned Reg = MO.getReg();
    582 if (MRegisterInfo::isVirtualRegister(Reg)) {
    582 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
    583583 bool removed = getVarInfo(Reg).removeKill(MI);
    584584 assert(removed && "kill not in register's VarInfo?");
    585585 }
    1212 #include "llvm/CodeGen/MachineFunctionPass.h"
    1313 #include "llvm/CodeGen/MachineInstr.h"
    1414 #include "llvm/CodeGen/MachineRegisterInfo.h"
    15 #include "llvm/Target/MRegisterInfo.h"
    15 #include "llvm/Target/TargetRegisterInfo.h"
    1616 #include "llvm/Target/TargetInstrInfo.h"
    1717 #include "llvm/Target/TargetMachine.h"
    1818 #include "llvm/Support/Debug.h"
    4545
    4646 // Returns the Register Class of a physical register.
    4747 static const TargetRegisterClass *getPhysicalRegisterRegClass(
    48 const MRegisterInfo &MRI,
    48 const TargetRegisterInfo &TRI,
    4949 unsigned reg) {
    50 assert(MRegisterInfo::isPhysicalRegister(reg) &&
    50 assert(TargetRegisterInfo::isPhysicalRegister(reg) &&
    5151 "reg must be a physical register");
    5252 // Pick the register class of the right type that contains this physreg.
    53 for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
    54 E = MRI.regclass_end(); I != E; ++I)
    53 for (TargetRegisterInfo::regclass_iterator I = TRI.regclass_begin(),
    54 E = TRI.regclass_end(); I != E; ++I)
    5555 if ((*I)->contains(reg))
    5656 return *I;
    5757 assert(false && "Couldn't find the register class");
    6161 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
    6262 MachineBasicBlock *MBB = MI->getParent();
    6363 MachineFunction &MF = *MBB->getParent();
    64 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
    64 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
    6565 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
    6666
    6767 assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
    7171 unsigned SuperReg = MI->getOperand(1).getReg();
    7272 unsigned SubIdx = MI->getOperand(2).getImm();
    7373
    74 assert(MRegisterInfo::isPhysicalRegister(SuperReg) &&
    74 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
    7575 "Extract supperg source must be a physical register");
    76 unsigned SrcReg = MRI.getSubReg(SuperReg, SubIdx);
    76 unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
    7777 unsigned DstReg = MI->getOperand(0).getReg();
    7878
    7979 DOUT << "subreg: CONVERTING: " << *MI;
    8080
    8181 if (SrcReg != DstReg) {
    8282 const TargetRegisterClass *TRC = 0;
    83 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
    84 TRC = getPhysicalRegisterRegClass(MRI, DstReg);
    83 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
    84 TRC = getPhysicalRegisterRegClass(TRI, DstReg);
    8585 } else {
    8686 TRC = MF.getRegInfo().getRegClass(DstReg);
    8787 }
    88 assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
    88 assert(TRC == getPhysicalRegisterRegClass(TRI, SrcReg) &&
    8989 "Extract subreg and Dst must be of same register class");
    9090
    9191 TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
    102102 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
    103103 MachineBasicBlock *MBB = MI->getParent();
    104104 MachineFunction &MF = *MBB->getParent();
    105 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
    105 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
    106106 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
    107107 unsigned DstReg = 0;
    108108 unsigned SrcReg = 0;
    132132 assert(0 && "Malformed extract_subreg");
    133133
    134134 assert(SubIdx != 0 && "Invalid index for extract_subreg");
    135 unsigned DstSubReg = MRI.getSubReg(DstReg, SubIdx);
    136
    137 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
    135 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
    136
    137 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
    138138 "Insert superreg source must be in a physical register");
    139 assert(MRegisterInfo::isPhysicalRegister(DstReg) &&
    139 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
    140140 "Insert destination must be in a physical register");
    141 assert(MRegisterInfo::isPhysicalRegister(InsReg) &&
    141 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
    142142 "Inserted value must be in a physical register");
    143143
    144144 DOUT << "subreg: CONVERTING: " << *MI;
    147147 // of the destination, we copy the subreg into the source
    148148 // However, this is only safe if the insert instruction is the kill
    149149 // of the source register
    150 bool revCopyOrder = MRI.isSubRegister(DstReg, InsReg);
    150 bool revCopyOrder = TRI.isSubRegister(DstReg, InsReg);
    151151 if (revCopyOrder && InsReg != DstSubReg) {
    152152 if (MI->getOperand(1).isKill()) {
    153 DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
    153 DstSubReg = TRI.getSubReg(SrcReg, SubIdx);
    154154 // Insert sub-register copy
    155155 const TargetRegisterClass *TRC1 = 0;
    156 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
    157 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
    156 if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
    157 TRC1 = getPhysicalRegisterRegClass(TRI, InsReg);
    158158 } else {
    159159 TRC1 = MF.getRegInfo().getRegClass(InsReg);
    160160 }
    177177 if (SrcReg != DstReg) {
    178178 // Insert super-register copy
    179179 const TargetRegisterClass *TRC0 = 0;
    180 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
    181 TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
    180 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
    181 TRC0 = getPhysicalRegisterRegClass(TRI, DstReg);
    182182 } else {
    183183 TRC0 = MF.getRegInfo().getRegClass(DstReg);
    184184 }
    185 assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
    185 assert(TRC0 == getPhysicalRegisterRegClass(TRI, SrcReg) &&
    186186 "Insert superreg and Dst must be of same register class");
    187187
    188188 TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
    202202 if (!revCopyOrder && InsReg != DstSubReg) {
    203203 // Insert sub-register copy
    204204 const TargetRegisterClass *TRC1 = 0;
    205 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
    206 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
    205 if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
    206 TRC1 = getPhysicalRegisterRegClass(TRI, InsReg);
    207207 } else {
    208208 TRC1 = MF.getRegInfo().getRegClass(InsReg);
    209209 }
    1313 #include "llvm/CodeGen/MachineBasicBlock.h"
    1414 #include "llvm/BasicBlock.h"
    1515 #include "llvm/CodeGen/MachineFunction.h"
    16 #include "llvm/Target/MRegisterInfo.h"
    16 #include "llvm/Target/TargetRegisterInfo.h"
    1717 #include "llvm/Target/TargetData.h"
    1818 #include "llvm/Target/TargetInstrDesc.h"
    1919 #include "llvm/Target/TargetMachine.h"
    142142 }
    143143
    144144 static inline void OutputReg(std::ostream &os, unsigned RegNo,
    145 const MRegisterInfo *MRI = 0) {
    146 if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
    147 if (MRI)
    148 os << " %" << MRI->get(RegNo).Name;
    145 const TargetRegisterInfo *TRI = 0) {
    146 if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo)) {
    147 if (TRI)
    148 os << " %" << TRI->get(RegNo).Name;
    149149 else
    150150 os << " %mreg(" << RegNo << ")";
    151151 } else
    168168 if (isLandingPad()) OS << ", EH LANDING PAD";
    169169 OS << ":\n";
    170170
    171 const MRegisterInfo *MRI = MF->getTarget().getRegisterInfo();
    171 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
    172172 if (!livein_empty()) {
    173173 OS << "Live Ins:";
    174174 for (const_livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
    175 OutputReg(OS, *I, MRI);
    175 OutputReg(OS, *I, TRI);
    176176 OS << "\n";
    177177 }
    178178 // Print the preds of this block according to the CFG.
    206206 // Print Constant Pool
    207207 getConstantPool()->print(OS);
    208208
    209 const MRegisterInfo *MRI = getTarget().getRegisterInfo();
    209 const TargetRegisterInfo *TRI = getTarget().getRegisterInfo();
    210210
    211211 if (!RegInfo->livein_empty()) {
    212212 OS << "Live Ins:";
    213213 for (MachineRegisterInfo::livein_iterator
    214214 I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) {
    215 if (MRI)
    216 OS << " " << MRI->getName(I->first);
    215 if (TRI)
    216 OS << " " << TRI->getName(I->first);
    217217 else
    218218 OS << " Reg #" << I->first;
    219219
    226226 OS << "Live Outs:";
    227227 for (MachineRegisterInfo::liveout_iterator
    228228 I = RegInfo->liveout_begin(), E = RegInfo->liveout_end(); I != E; ++I)
    229 if (MRI)
    230 OS << " " << MRI->getName(*I);
    229 if (TRI)
    230 OS << " " << TRI->getName(*I);
    231231 else
    232232 OS << " Reg #" << *I;
    233233 OS << "\n";
    1919 #include "llvm/Target/TargetMachine.h"
    2020 #include "llvm/Target/TargetInstrInfo.h"
    2121 #include "llvm/Target/TargetInstrDesc.h"
    22 #include "llvm/Target/MRegisterInfo.h"
    22 #include "llvm/Target/TargetRegisterInfo.h"
    2323 #include "llvm/Support/LeakDetector.h"
    2424 #include "llvm/Support/Streams.h"
    2525 #include
    158158 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
    159159 switch (getType()) {
    160160 case MachineOperand::MO_Register:
    161 if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) {
    161 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
    162162 OS << "%reg" << getReg();
    163163 } else {
    164164 // If the instruction is embedded into a basic block, we can find the
    665665 }
    666666
    667667 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
    668 const MRegisterInfo *RegInfo,
    668 const TargetRegisterInfo *RegInfo,
    669669 bool AddIfNotFound) {
    670670 bool Found = false;
    671671 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
    678678 MO.setIsKill();
    679679 Found = true;
    680680 break;
    681 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
    682 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
    681 } else if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
    682 TargetRegisterInfo::isPhysicalRegister(IncomingReg) &&
    683683 RegInfo->isSuperRegister(IncomingReg, Reg) &&
    684684 MO.isKill())
    685685 // A super-register kill already exists.
    698698 }
    699699
    700700 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
    701 const MRegisterInfo *RegInfo,
    701 const TargetRegisterInfo *RegInfo,
    702702 bool AddIfNotFound) {
    703703 bool Found = false;
    704704 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
    711711 MO.setIsDead();
    712712 Found = true;
    713713 break;
    714 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
    715 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
    714 } else if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
    715 TargetRegisterInfo::isPhysicalRegister(IncomingReg) &&
    716716 RegInfo->isSuperRegister(IncomingReg, Reg) &&
    717717 MO.isDead())
    718718 // There exists a super-register that's marked dead.
    733733
    734734 /// copyKillDeadInfo - copies killed/dead information from one instr to another
    735735 void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI,
    736 const MRegisterInfo *RegInfo) {
    736 const TargetRegisterInfo *RegInfo) {
    737737 // If the instruction defines any virtual registers, update the VarInfo,
    738738 // kill and dead information for the instruction.
    739739 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
    740740 MachineOperand &MO = OldMI->getOperand(i);
    741741 if (MO.isRegister() && MO.getReg() &&
    742 MRegisterInfo::isVirtualRegister(MO.getReg())) {
    742 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
    743743 unsigned Reg = MO.getReg();
    744744 if (MO.isDef()) {
    745745 if (MO.isDead()) {
    1616 #include "llvm/CodeGen/MachineDominators.h"
    1717 #include "llvm/CodeGen/MachineLoopInfo.h"
    1818 #include "llvm/CodeGen/MachineRegisterInfo.h"
    19 #include "llvm/Target/MRegisterInfo.h"
    19 #include "llvm/Target/TargetRegisterInfo.h"
    2020 #include "llvm/Target/TargetInstrInfo.h"
    2121 #include "llvm/Target/TargetMachine.h"
    2222 #include "llvm/ADT/SmallVector.h"
    247247 if (I.getDesc().getImplicitUses()) {
    248248 DOUT << " * Instruction has implicit uses:\n";
    249249
    250 const MRegisterInfo *MRI = TM->getRegisterInfo();
    250 const TargetRegisterInfo *TRI = TM->getRegisterInfo();
    251251 for (const unsigned *ImpUses = I.getDesc().getImplicitUses();
    252252 *ImpUses; ++ImpUses)
    253 DOUT << " -> " << MRI->getName(*ImpUses) << "\n";
    253 DOUT << " -> " << TRI->getName(*ImpUses) << "\n";
    254254 }
    255255
    256256 if (I.getDesc().getImplicitDefs()) {
    257257 DOUT << " * Instruction has implicit defines:\n";
    258258
    259 const MRegisterInfo *MRI = TM->getRegisterInfo();
    259 const TargetRegisterInfo *TRI = TM->getRegisterInfo();
    260260 for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs();
    261261 *ImpDefs; ++ImpDefs)
    262 DOUT << " -> " << MRI->getName(*ImpDefs) << "\n";
    262 DOUT << " -> " << TRI->getName(*ImpDefs) << "\n";
    263263 }
    264264
    265265 //if (TII->hasUnmodelledSideEffects(&I))
    276276 unsigned Reg = MO.getReg();
    277277
    278278 // Don't hoist instructions that access physical registers.
    279 if (!MRegisterInfo::isVirtualRegister(Reg))
    279 if (!TargetRegisterInfo::isVirtualRegister(Reg))
    280280 return false;
    281281
    282282 assert(RegInfo->getVRegDef(Reg)&&"Machine instr not mapped for this vreg?");
    1313 #include "llvm/CodeGen/MachineRegisterInfo.h"
    1414 using namespace llvm;
    1515
    16 MachineRegisterInfo::MachineRegisterInfo(const MRegisterInfo &MRI) {
    16 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
    1717 VRegInfo.reserve(256);
    18 UsedPhysRegs.resize(MRI.getNumRegs());
    18 UsedPhysRegs.resize(TRI.getNumRegs());
    1919
    2020 // Create the physreg use/def lists.
    21 PhysRegUseDefLists = new MachineOperand*[MRI.getNumRegs()];
    22 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*MRI.getNumRegs());
    21 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
    22 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
    2323 }
    2424
    2525 MachineRegisterInfo::~MachineRegisterInfo() {
    6363 /// register or null if none is found. This assumes that the code is in SSA
    6464 /// form, so there should only be one definition.
    6565 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
    66 assert(Reg-MRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
    66 assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
    6767 "Invalid vreg!");
    6868 for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
    6969 // Since we are in SSA form, we can stop at the first definition.
    1414 #include "llvm/CodeGen/Passes.h"
    1515 #include "llvm/CodeGen/MachineRegisterInfo.h"
    1616 #include "llvm/CodeGen/MachineDominators.h"
    17 #include "llvm/Target/MRegisterInfo.h"
    17 #include "llvm/Target/TargetRegisterInfo.h"
    1818 #include "llvm/Target/TargetInstrInfo.h"
    1919 #include "llvm/Target/TargetMachine.h"
    2020 #include "llvm/ADT/SmallVector.h"
    6060 /// occur in blocks dominated by the specified block.
    6161 bool MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
    6262 MachineBasicBlock *MBB) const {
    63 assert(MRegisterInfo::isVirtualRegister(Reg) && "Only makes sense for vregs");
    63 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
    64 "Only makes sense for vregs");
    6465 for (MachineRegisterInfo::reg_iterator I = RegInfo->reg_begin(Reg),
    6566 E = RegInfo->reg_end(); I != E; ++I) {
    6667 if (I.getOperand().isDef()) continue; // ignore def.
    178179 unsigned Reg = MO.getReg();
    179180 if (Reg == 0) continue;
    180181
    181 if (MRegisterInfo::isPhysicalRegister(Reg)) {
    182 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
    182183 // If this is a physical register use, we can't move it. If it is a def,
    183184 // we can move it, but only if the def is dead.
    184185 if (MO.isUse() || !MO.isDead())
    180180 std::set MBBsInsertedInto;
    181181 for (int i = MPhi->getNumOperands() - 1; i >= 2; i-=2) {
    182182 unsigned SrcReg = MPhi->getOperand(i-1).getReg();
    183 assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
    183 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
    184184 "Machine PHI Operands must all be virtual registers!");
    185185
    186186 // Get the MachineBasicBlock equivalent of the BasicBlock that is the
    1616 #ifndef LLVM_CODEGEN_PHYSREGTRACKER_H
    1717 #define LLVM_CODEGEN_PHYSREGTRACKER_H
    1818
    19 #include "llvm/Target/MRegisterInfo.h"
    19 #include "llvm/Target/TargetRegisterInfo.h"
    2020
    2121 namespace llvm {
    2222
    2323 class PhysRegTracker {
    24 const MRegisterInfo* mri_;
    24 const TargetRegisterInfo* tri_;
    2525 std::vector regUse_;
    2626
    2727 public:
    28 explicit PhysRegTracker(const MRegisterInfo& mri)
    29 : mri_(&mri),
    30 regUse_(mri_->getNumRegs(), 0) {
    28 explicit PhysRegTracker(const TargetRegisterInfo& tri)
    29 : tri_(&tri),
    30 regUse_(tri_->getNumRegs(), 0) {
    3131 }
    3232
    3333 PhysRegTracker(const PhysRegTracker& rhs)
    34 : mri_(rhs.mri_),
    34 : tri_(rhs.tri_),
    3535 regUse_(rhs.regUse_) {
    3636 }
    3737
    3838 const PhysRegTracker& operator=(const PhysRegTracker& rhs) {
    39 mri_ = rhs.mri_;
    39 tri_ = rhs.tri_;
    4040 regUse_ = rhs.regUse_;
    4141 return *this;
    4242 }
    4343
    4444 void addRegUse(unsigned physReg) {
    45 assert(MRegisterInfo::isPhysicalRegister(physReg) &&
    45 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
    4646 "should be physical register!");
    4747 ++regUse_[physReg];
    48 for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as)
    48 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
    4949 ++regUse_[*as];
    5050 }
    5151
    5252 void delRegUse(unsigned physReg) {
    53 assert(MRegisterInfo::isPhysicalRegister(physReg) &&
    53 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
    5454 "should be physical register!");
    5555 assert(regUse_[physReg] != 0);
    5656 --regUse_[physReg];
    57 for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) {
    57 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
    5858 assert(regUse_[*as] != 0);
    5959 --regUse_[*as];
    6060 }
    6161 }
    6262
    6363 bool isRegAvail(unsigned physReg) const {
    64 assert(MRegisterInfo::isPhysicalRegister(physReg) &&
    64 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
    6565 "should be physical register!");
    6666 return regUse_[physReg] == 0;
    6767 }
    2323 #include "llvm/CodeGen/MachineRegisterInfo.h"
    2424 #include "llvm/CodeGen/RegisterScavenging.h"
    2525 #include "llvm/Target/TargetMachine.h"
    26 #include "llvm/Target/MRegisterInfo.h"
    26 #include "llvm/Target/TargetRegisterInfo.h"
    2727 #include "llvm/Target/TargetFrameInfo.h"
    2828 #include "llvm/Target/TargetInstrInfo.h"
    2929 #include "llvm/Support/Compiler.h"
    4444 /// frame indexes with appropriate references.
    4545 ///
    4646 bool runOnMachineFunction(MachineFunction &Fn) {
    47 const MRegisterInfo *MRI = Fn.getTarget().getRegisterInfo();
    48 RS = MRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL;
    47 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
    48 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL;
    4949
    5050 // Get MachineModuleInfo so that we can track the construction of the
    5151 // frame.
    5454
    5555 // Allow the target machine to make some adjustments to the function
    5656 // e.g. UsedPhysRegs before calculateCalleeSavedRegisters.
    57 MRI->processFunctionBeforeCalleeSavedScan(Fn, RS);
    57 TRI->processFunctionBeforeCalleeSavedScan(Fn, RS);
    5858
    5959 // Scan the function for modified callee saved registers and insert spill
    6060 // code for any callee saved registers that are modified. Also calculate
    117117 /// instructions.
    118118 ///
    119119 void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
    120 const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
    120 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
    121121 const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
    122122
    123123 // Get the callee saved register list...
    376376
    377377 // Make sure the special register scavenging spill slot is closest to the
    378378 // frame pointer if a frame pointer is required.
    379 const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
    379 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
    380380 if (RS && RegInfo->hasFP(Fn)) {
    381381 int SFI = RS->getScavengingFrameIndex();
    382382 if (SFI >= 0) {
    499499
    500500 const TargetMachine &TM = Fn.getTarget();
    501501 assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
    502 const MRegisterInfo &MRI = *TM.getRegisterInfo();
    502 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
    503503 const TargetFrameInfo *TFI = TM.getFrameInfo();
    504504 bool StackGrowsDown =
    505505 TFI->getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
    506 int FrameSetupOpcode = MRI.getCallFrameSetupOpcode();
    507 int FrameDestroyOpcode = MRI.getCallFrameDestroyOpcode();
    506 int FrameSetupOpcode = TRI.getCallFrameSetupOpcode();
    507 int FrameDestroyOpcode = TRI.getCallFrameDestroyOpcode();
    508508
    509509 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
    510510 int SPAdj = 0; // SP offset due to call frame setup / destroy.
    521521 Size = -Size;
    522522 SPAdj += Size;
    523523 MachineBasicBlock::iterator PrevI = prior(I);
    524 MRI.eliminateCallFramePseudoInstr(Fn, *BB, I);
    524 TRI.eliminateCallFramePseudoInstr(Fn, *BB, I);
    525525 // Visit the instructions created by eliminateCallFramePseudoInstr().
    526526 I = next(PrevI);
    527527 MI = NULL;
    534534 if (MI->getOperand(i).isFrameIndex()) {
    535535 // If this instruction has a FrameIndex operand, we need to use that
    536536 // target machine register info object to eliminate it.
    537 MRI.eliminateFrameIndex(MI, SPAdj, RS);
    537 TRI.eliminateFrameIndex(MI, SPAdj, RS);
    538538
    539539 // Revisit the instruction in full. Some instructions (e.g. inline
    540540 // asm instructions) can have multiple frame indices.
    9494
    9595 /// RegInfo - For dealing with machine register info (aliases, folds
    9696 /// etc)
    97 const MRegisterInfo *RegInfo;
    97 const TargetRegisterInfo *RegInfo;
    9898
    9999 typedef SmallVector VRegTimes;
    100100
    151151 /// markVirtRegModified - Lets us flip bits in the VirtRegModified bitset
    152152 ///
    153153 void markVirtRegModified(unsigned Reg, bool Val = true) {
    154 assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
    155 Reg -= MRegisterInfo::FirstVirtualRegister;
    154 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
    155 Reg -= TargetRegisterInfo::FirstVirtualRegister;
    156156 if (VirtRegModified.size() <= Reg)
    157157 VirtRegModified.resize(Reg+1);
    158158 VirtRegModified[Reg] = Val;
    161161 /// isVirtRegModified - Lets us query the VirtRegModified bitset
    162162 ///
    163163 bool isVirtRegModified(unsigned Reg) const {
    164 assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
    165 assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
    164 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
    165 assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
    166166 && "Illegal virtual register!");
    167 return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister];
    167 return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
    168168 }
    169169
    170170 public:
    561561 MachineOperand& MO = MI->getOperand(i);
    562562 // look for vreg reads..
    563563 if (MO.isRegister() && !MO.isDef() && MO.getReg() &&
    564 MRegisterInfo::isVirtualRegister(MO.getReg())) {
    564 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
    565565 // ..and add them to the read table.
    566566 VRegTimes* &Times = VRegReadTable[MO.getReg()];
    567567 if(!VRegReadTable[MO.getReg()]) {
    674674 MachineOperand& MO = MI->getOperand(i);
    675675 // here we are looking for only used operands (never def&use)
    676676 if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
    677 MRegisterInfo::isVirtualRegister(MO.getReg()))
    677 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
    678678 MI = reloadVirtReg(MBB, MI, i);
    679679 }
    680680
    685685 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
    686686 unsigned VirtReg = Kills[i];
    687687 unsigned PhysReg = VirtReg;
    688 if (MRegisterInfo::isVirtualRegister(VirtReg)) {
    688 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
    689689 // If the virtual register was never materialized into a register, it
    690690 // might not be in the map, but it won't hurt to zero it out anyway.
    691691 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
    720720 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    721721 MachineOperand& MO = MI->getOperand(i);
    722722 if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
    723 MRegisterInfo::isPhysicalRegister(MO.getReg())) {
    723 TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
    724724 unsigned Reg = MO.getReg();
    725725 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
    726726 // These are extra physical register defs when a sub-register
    776776 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    777777 MachineOperand& MO = MI->getOperand(i);
    778778 if (MO.isRegister() && MO.isDef() && MO.getReg() &&
    779 MRegisterInfo::isVirtualRegister(MO.getReg())) {
    779 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
    780780 unsigned DestVirtReg = MO.getReg();
    781781 unsigned DestPhysReg;
    782782
    795795 for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
    796796 unsigned VirtReg = DeadDefs[i];
    797797 unsigned PhysReg = VirtReg;
    798 if (MRegisterInfo::isVirtualRegister(VirtReg)) {
    798 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
    799799 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
    800800 PhysReg = PhysRegSlot;
    801801 assert(PhysReg != 0);
    864864 Virt2PhysRegMap.grow(MF->getRegInfo().getLastVirtReg());
    865865 StackSlotForVirtReg.grow(MF->getRegInfo().getLastVirtReg());
    866866 VirtRegModified.resize(MF->getRegInfo().getLastVirtReg() -
    867 MRegisterInfo::FirstVirtualRegister + 1, 0);
    867 TargetRegisterInfo::FirstVirtualRegister + 1, 0);
    868868
    869869 // Loop over all of the basic blocks, eliminating virtual register references
    870870 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
    2222 #include "llvm/CodeGen/Passes.h"
    2323 #include "llvm/CodeGen/RegAllocRegistry.h"
    2424 #include "llvm/CodeGen/RegisterCoalescer.h"
    25 #include "llvm/Target/MRegisterInfo.h"
    25 #include "llvm/Target/TargetRegisterInfo.h"
    2626 #include "llvm/Target/TargetMachine.h"
    2727 #include "llvm/Target/TargetInstrInfo.h"
    2828 #include "llvm/ADT/EquivalenceClasses.h"
    6161
    6262 MachineFunction* mf_;
    6363 const TargetMachine* tm_;
    64 const MRegisterInfo* mri_;
    64 const TargetRegisterInfo* tri_;
    6565 const TargetInstrInfo* tii_;
    6666 MachineRegisterInfo *reginfo_;
    6767 BitVector allocatableRegs_;
    160160 for (; i != e; ++i) {
    161161 DOUT << "\t" << *i->first << " -> ";
    162162 unsigned reg = i->first->reg;
    163 if (MRegisterInfo::isVirtualRegister(reg)) {
    163 if (TargetRegisterInfo::isVirtualRegister(reg)) {
    164164 reg = vrm_->getPhys(reg);
    165165 }
    166 DOUT << mri_->getName(reg) << '\n';
    166 DOUT << tri_->getName(reg) << '\n';
    167167 }
    168168 }
    169169 };
    171171 }
    172172
    173173 void RALinScan::ComputeRelatedRegClasses() {
    174 const MRegisterInfo &MRI = *mri_;
    174 const TargetRegisterInfo &TRI = *tri_;
    175175
    176176 // First pass, add all reg classes to the union, and determine at least one
    177177 // reg class that each register is in.
    178178 bool HasAliases = false;
    179 for (MRegisterInfo::regclass_iterator RCI = MRI.regclass_begin(),
    180 E = MRI.regclass_end(); RCI != E; ++RCI) {
    179 for (TargetRegisterInfo::regclass_iterator RCI = TRI.regclass_begin(),
    180 E = TRI.regclass_end(); RCI != E; ++RCI) {
    181181 RelatedRegClasses.insert(*RCI);
    182182 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
    183183 I != E; ++I) {
    184 HasAliases = HasAliases || *MRI.getAliasSet(*I) != 0;
    184 HasAliases = HasAliases || *TRI.getAliasSet(*I) != 0;
    185185
    186186 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
    187187 if (PRC) {
    201201 for (std::map::iterator
    202202 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
    203203 I != E; ++I)
    204 for (const unsigned *AS = MRI.getAliasSet(I->first); *AS; ++AS)
    204 for (const unsigned *AS = TRI.getAliasSet(I->first); *AS; ++AS)
    205205 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
    206206 }
    207207
    223223 unsigned SrcReg, DstReg;
    224224 if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg))
    225225 return Reg;
    226 if (MRegisterInfo::isVirtualRegister(SrcReg))
    226 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
    227227 if (!vrm_->isAssignedReg(SrcReg))
    228228 return Reg;
    229229 else
    237237
    238238 // Try to coalesce.
    239239 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) {
    240 DOUT << "Coalescing: " << cur << " -> " << mri_->getName(SrcReg) << '\n';
    240 DOUT << "Coalescing: " << cur << " -> " << tri_->getName(SrcReg) << '\n';
    241241 vrm_->clearVirt(cur.reg);
    242242 vrm_->assignVirt2Phys(cur.reg, SrcReg);
    243243 ++NumCoalesce;
    250250 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
    251251 mf_ = &fn;
    252252 tm_ = &fn.getTarget();
    253 mri_ = tm_->getRegisterInfo();
    253 tri_ = tm_->getRegisterInfo();
    254254 tii_ = tm_->getInstrInfo();
    255255 reginfo_ = &mf_->getRegInfo();
    256 allocatableRegs_ = mri_->getAllocatableSet(fn);
    256 allocatableRegs_ = tri_->getAllocatableSet(fn);
    257257 li_ = &getAnalysis();
    258258 loopInfo = &getAnalysis();
    259259
    266266 if (RelatedRegClasses.empty())
    267267 ComputeRelatedRegClasses();
    268268
    269 if (!prt_.get()) prt_.reset(new PhysRegTracker(*mri_));
    269 if (!prt_.get()) prt_.reset(new PhysRegTracker(*tri_));
    270270 vrm_.reset(new VirtRegMap(*mf_));
    271271 if (!spiller_.get()) spiller_.reset(createSpiller());
    272272
    296296 "interval sets should be empty on initialization");
    297297
    298298 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
    299 if (MRegisterInfo::isPhysicalRegister(i->second.reg)) {
    299 if (TargetRegisterInfo::isPhysicalRegister(i->second.reg)) {
    300300 reginfo_->setPhysRegUsed(i->second.reg);
    301301 fixed_.push_back(std::make_pair(&i->second, i->second.begin()));
    302302 } else
    322322 processActiveIntervals(cur->beginNumber());
    323323 processInactiveIntervals(cur->beginNumber());
    324324
    325 assert(MRegisterInfo::isVirtualRegister(cur->reg) &&
    325 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
    326326 "Can only allocate virtual registers!");
    327327
    328328 // Allocating a virtual register. try to find a free
    339339 IntervalPtr &IP = active_.back();
    340340 unsigned reg = IP.first->reg;
    341341 DOUT << "\tinterval " << *IP.first << " expired\n";
    342 assert(MRegisterInfo::isVirtualRegister(reg) &&
    342 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
    343343 "Can only allocate virtual registers!");
    344344 reg = vrm_->getPhys(reg);
    345345 prt_->delRegUse(reg);
    358358 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
    359359 LiveInterval &cur = i->second;
    360360 unsigned Reg = 0;
    361 bool isPhys = MRegisterInfo::isPhysicalRegister(cur.reg);
    361 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
    362362 if (isPhys)
    363363 Reg = i->second.reg;
    364364 else if (vrm_->isAssignedReg(cur.reg))
    398398
    399399 if (IntervalPos == Interval->end()) { // Remove expired intervals.
    400400 DOUT << "\t\tinterval " << *Interval << " expired\n";
    401 assert(MRegisterInfo::isVirtualRegister(reg) &&
    401 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
    402402 "Can only allocate virtual registers!");
    403403 reg = vrm_->getPhys(reg);
    404404 prt_->delRegUse(reg);
    411411 } else if (IntervalPos->start > CurPoint) {
    412412 // Move inactive intervals to inactive list.
    413413 DOUT << "\t\tinterval " << *Interval << " inactive\n";
    414 assert(MRegisterInfo::isVirtualRegister(reg) &&
    414 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
    415415 "Can only allocate virtual registers!");
    416416 reg = vrm_->getPhys(reg);
    417417 prt_->delRegUse(reg);
    452452 } else if (IntervalPos->start <= CurPoint) {
    453453 // move re-activated intervals in active list
    454454 DOUT << "\t\tinterval " << *Interval << " active\n";
    455 assert(MRegisterInfo::isVirtualRegister(reg) &&
    455 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
    456456 "Can only allocate virtual registers!");
    457457 reg = vrm_->getPhys(reg);
    458458 prt_->addRegUse(reg);
    474474 /// register and its weight.
    475475 static void updateSpillWeights(std::vector &Weights,
    476476 unsigned reg, float weight,
    477 const MRegisterInfo *MRI) {
    477 const TargetRegisterInfo *TRI) {
    478478 Weights[reg] += weight;
    479 for (const unsigned* as = MRI->getAliasSet(reg); *as; ++as)
    479 for (const unsigned* as = TRI->getAliasSet(reg); *as; ++as)
    480480 Weights[*as] += weight;
    481481 }
    482482
    524524 unsigned SrcReg, DstReg;
    525525 if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
    526526 unsigned Reg = 0;
    527 if (MRegisterInfo::isPhysicalRegister(SrcReg))
    527 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
    528528 Reg = SrcReg;
    529529 else if (vrm_->isAssignedReg(SrcReg))
    530530 Reg = vrm_->getPhys(SrcReg);
    539539 for (IntervalPtrs::const_iterator i = inactive_.begin(),
    540540 e = inactive_.end(); i != e; ++i) {
    541541 unsigned Reg = i->first->reg;
    542 assert(MRegisterInfo::isVirtualRegister(Reg) &&
    542 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
    543543 "Can only allocate virtual registers!");
    544544 const TargetRegisterClass *RegRC = reginfo_->getRegClass(Reg);
    545545 // If this is not in a related reg class to the register we're allocating,
    563563 // conflict with it. Check to see if we conflict with it or any of its
    564564 // aliases.
    565565 SmallSet RegAliases;
    566 for (const unsigned *AS = mri_->getAliasSet(physReg); *AS; ++AS)
    566 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
    567567 RegAliases.insert(*AS);
    568568
    569569 bool ConflictsWithFixed = false;
    625625 // the free physical register and add this interval to the active
    626626 // list.
    627627 if (physReg) {
    628 DOUT << mri_->getName(physReg) << '\n';
    628 DOUT << tri_->getName(physReg) << '\n';
    629629 vrm_->assignVirt2Phys(cur->reg, physReg);
    630630 prt_->addRegUse(physReg);
    631631 active_.push_back(std::make_pair(cur, cur->begin()));
    635635 DOUT << "no free registers\n";
    636636
    637637 // Compile the spill weights into an array that is better for scanning.
    638 std::vector SpillWeights(mri_->getNumRegs(), 0.0);
    638 std::vector SpillWeights(tri_->getNumRegs(), 0.0);
    639639 for (std::vector >::iterator
    640640 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
    641 updateSpillWeights(SpillWeights, I->first, I->second, mri_);
    641 updateSpillWeights(SpillWeights, I->first, I->second, tri_);
    642642
    643643 // for each interval in active, update spill weights.
    644644 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
    645645 i != e; ++i) {
    646646 unsigned reg = i->first->reg;
    647 assert(MRegisterInfo::isVirtualRegister(reg) &&
    647 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
    648648 "Can only allocate virtual registers!");
    649649 reg = vrm_->getPhys(reg);
    650 updateSpillWeights(SpillWeights, reg, i->first->weight, mri_);
    650 updateSpillWeights(SpillWeights, reg, i->first->weight, tri_);
    651651 }
    652652
    653653 DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
    673673 unsigned reg = *i;
    674674 // No need to worry about if the alias register size < regsize of RC.
    675675 // We are going to spill all registers that alias it anyway.
    676 for (const unsigned* as = mri_->getAliasSet(reg); *as; ++as) {
    676 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
    677677 if (minWeight > SpillWeights[*as]) {
    678678 minWeight = SpillWeights[*as];
    679679 minReg = *as;
    687687 }
    688688
    689689 DOUT << "\t\tregister with min weight: "
    690 << mri_->getName(minReg) << " (" << minWeight << ")\n";
    690 << tri_->getName(minReg) << " (" << minWeight << ")\n";
    691691
    692692 // if the current has the minimum weight, we need to spill it and
    693693 // add any added intervals back to unhandled, and restart
    718718 // minimum weight, rollback to the interval with the earliest
    719719 // start point and let the linear scan algorithm run again
    720720 std::vector added;
    721 assert(MRegisterInfo::isPhysicalRegister(minReg) &&
    721 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
    722722 "did not choose a register to spill?");
    723 BitVector toSpill(mri_->getNumRegs());
    723 BitVector toSpill(tri_->getNumRegs());
    724724
    725725 // We are going to spill minReg and all its aliases.
    726726 toSpill[minReg] = true;
    727 for (const unsigned* as = mri_->getAliasSet(minReg); *as; ++as)
    727 for (const unsigned* as = tri_->getAliasSet(minReg); *as; ++as)
    728728 toSpill[*as] = true;
    729729
    730730 // the earliest start of a spilled interval indicates up to where
    741741 // mark our rollback point.
    742742 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
    743743 unsigned reg = i->first->reg;
    744 if (//MRegisterInfo::isVirtualRegister(reg) &&
    744 if (//TargetRegisterInfo::isVirtualRegister(reg) &&
    745745 toSpill[vrm_->getPhys(reg)] &&
    746746 cur->overlapsFrom(*i->first, i->second)) {
    747747 DOUT << "\t\t\tspilling(a): " << *i->first << '\n';
    754754 }
    755755 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
    756756 unsigned reg = i->first->reg;
    757 if (//MRegisterInfo::isVirtualRegister(reg) &&
    757 if (//TargetRegisterInfo::isVirtualRegister(reg) &&
    758758 toSpill[vrm_->getPhys(reg)] &&
    759759 cur->overlapsFrom(*i->first, i->second-1)) {
    760760 DOUT << "\t\t\tspilling(i): " << *i->first << '\n';
    784784 IntervalPtrs::iterator it;
    785785 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
    786786 active_.erase(it);
    787 assert(!MRegisterInfo::isPhysicalRegister(i->reg));
    787 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
    788788 if (!spilled.count(i->reg))
    789789 unhandled_.push(i);
    790790 prt_->delRegUse(vrm_->getPhys(i->reg));
    791791 vrm_->clearVirt(i->reg);
    792792 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
    793793 inactive_.erase(it);
    794 assert(!MRegisterInfo::isPhysicalRegister(i->reg));
    794 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
    795795 if (!spilled.count(i->reg))
    796796 unhandled_.push(i);
    797797 vrm_->clearVirt(i->reg);
    798798 } else {
    799 assert(MRegisterInfo::isVirtualRegister(i->reg) &&
    799 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
    800800 "Can only allocate virtual registers!");
    801801 vrm_->clearVirt(i->reg);
    802802 unhandled_.push(i);
    823823 HI->expiredAt(cur->beginNumber())) {
    824824 DOUT << "\t\t\tundo changes for: " << *HI << '\n';
    825825 active_.push_back(std::make_pair(HI, HI->begin()));
    826 assert(!MRegisterInfo::isPhysicalRegister(HI->reg));
    826 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
    827827 prt_->addRegUse(vrm_->getPhys(HI->reg));
    828828 }
    829829 }
    836836 /// getFreePhysReg - return a free physical register for this virtual register
    837837 /// interval if we have one, otherwise return 0.
    838838 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
    839 std::vector inactiveCounts(mri_->getNumRegs(), 0);
    839 std::vector inactiveCounts(tri_->getNumRegs(), 0);
    840840 unsigned MaxInactiveCount = 0;
    841841
    842842 const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg);
    845845 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
    846846 i != e; ++i) {
    847847 unsigned reg = i->first->reg;
    848 assert(MRegisterInfo::isVirtualRegister(reg) &&
    848 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
    849849 "Can only allocate virtual registers!");
    850850
    851851 // If this is not in a related reg class to the register we're allocating,
    866866 if (cur->preference)
    867867 if (prt_->isRegAvail(cur->preference)) {
    868868 DOUT << "\t\tassigned the preferred register: "
    869 << mri_->getName(cur->preference) << "\n";
    869 << tri_->getName(cur->preference) << "\n";
    870870 return cur->preference;
    871871 } else
    872872 DOUT << "\t\tunable to assign the preferred register: "
    873 << mri_->getName(cur->preference) << "\n";
    873 << tri_->getName(cur->preference) << "\n";
    874874
    875875 // Scan for the first available register.
    876876 TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
    4848 private:
    4949 const TargetMachine *TM;
    5050 MachineFunction *MF;
    51 const MRegisterInfo *MRI;
    51 const TargetRegisterInfo *TRI;
    5252 const TargetInstrInfo *TII;
    5353
    5454 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
    9090 Virt2LastUseMap;
    9191
    9292 std::pair& getVirtRegLastUse(unsigned Reg) {
    93 assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
    93 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
    9494 return Virt2LastUseMap[Reg];
    9595 }
    9696
    102102 BitVector VirtRegModified;
    103103
    104104 void markVirtRegModified(unsigned Reg, bool Val = true) {
    105 assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
    106 Reg -= MRegisterInfo::FirstVirtualRegister;
    105 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
    106 Reg -= TargetRegisterInfo::FirstVirtualRegister;
    107107 if (Val)
    108108 VirtRegModified.set(Reg);
    109109 else
    111111 }
    112112
    113113 bool isVirtRegModified(unsigned Reg) const {
    114 assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
    115 assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
    114 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
    115 assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
    116116 && "Illegal virtual register!");
    117 return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister];
    117 return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
    118118 }
    119119
    120120 void AddToPhysRegsUseOrder(unsigned Reg) {
    166166 ///
    167167 bool areRegsEqual(unsigned R1, unsigned R2) const {
    168168 if (R1 == R2) return true;
    169 for (const unsigned *AliasSet = MRI->getAliasSet(R2);
    169 for (const unsigned *AliasSet = TRI->getAliasSet(R2);
    170170 *AliasSet; ++AliasSet) {
    171171 if (*AliasSet == R1) return true;
    172172 }
    285285 assert(VirtReg && "Spilling a physical register is illegal!"
    286286 " Must not have appropriate kill for the register or use exists beyond"
    287287 " the intended one.");
    288 DOUT << " Spilling register " << MRI->getName(PhysReg)
    288 DOUT << " Spilling register " << TRI->getName(PhysReg)
    289289 << " containing %reg" << VirtReg;
    290290
    291291 const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
    337337 } else {
    338338 // If the selected register aliases any other registers, we must make
    339339 // sure that one of the aliases isn't alive.
    340 for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg);
    340 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
    341341 *AliasSet; ++AliasSet)
    342342 if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
    343343 PhysRegsUsed[*AliasSet] != -2) // If allocatable.
    370370
    371371 // If the selected register aliases any other allocated registers, it is
    372372 // not free!
    373 for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg);
    373 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
    374374 *AliasSet; ++AliasSet)
    375375 if (PhysRegsUsed[*AliasSet] != -1) // Aliased register in use?
    376376 return false; // Can't use this reg then.
    433433 } else {
    434434 // If one of the registers aliased to the current register is
    435435 // compatible, use it.
    436 for (const unsigned *AliasIt = MRI->getAliasSet(R);
    436 for (const unsigned *AliasIt = TRI->getAliasSet(R);
    437437 *AliasIt; ++AliasIt) {
    438438 if (RC->contains(*AliasIt) &&
    439439 // If this is pinned down for some reason, don't use it. For
    506506 markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
    507507
    508508 DOUT << " Reloading %reg" << VirtReg << " into "
    509 << MRI->getName(PhysReg) << "\n";
    509 << TRI->getName(PhysReg) << "\n";
    510510
    511511 // Add move instruction(s)
    512512 const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
    560560 MF->getRegInfo().setPhysRegUsed(Reg);
    561561 PhysRegsUsed[Reg] = 0; // It is free and reserved now
    562562 AddToPhysRegsUseOrder(Reg);
    563 for (const unsigned *AliasSet = MRI->getSubRegisters(Reg);
    563 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
    564564 *AliasSet; ++AliasSet) {
    565565 if (PhysRegsUsed[*AliasSet] != -2) {
    566566 AddToPhysRegsUseOrder(*AliasSet);
    577577 const TargetInstrDesc &TID = MI->getDesc();
    578578 DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI;
    579579 DOUT << " Regs have values: ";
    580 for (unsigned i = 0; i != MRI->getNumRegs(); ++i)
    580 for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
    581581 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
    582 DOUT << "[" << MRI->getName(i)
    582 DOUT << "[" << TRI->getName(i)
    583583 << ",%reg" << PhysRegsUsed[i] << "] ";
    584584 DOUT << "\n");
    585585
    615615 MachineOperand& MO = MI->getOperand(i);
    616616 // here we are looking for only used operands (never def&use)
    617617 if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
    618 MRegisterInfo::isVirtualRegister(MO.getReg()))
    618 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
    619619 MI = reloadVirtReg(MBB, MI, i);
    620620 }
    621621
    626626 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
    627627 unsigned VirtReg = Kills[i];
    628628 unsigned PhysReg = VirtReg;
    629 if (MRegisterInfo::isVirtualRegister(VirtReg)) {
    629 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
    630630 // If the virtual register was never materialized into a register, it
    631631 // might not be in the map, but it won't hurt to zero it out anyway.
    632632 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
    641641 }
    642642
    643643 if (PhysReg) {
    644 DOUT << " Last use of " << MRI->getName(PhysReg)
    644 DOUT << " Last use of " << TRI->getName(PhysReg)
    645645 << "[%reg" << VirtReg <<"], removing it from live set\n";
    646646 removePhysReg(PhysReg);
    647 for (const unsigned *AliasSet = MRI->getSubRegisters(PhysReg);
    647 for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg);
    648648 *AliasSet; ++AliasSet) {
    649649 if (PhysRegsUsed[*AliasSet] != -2) {
    650650 DOUT << " Last use of "
    651 << MRI->getName(*AliasSet)
    651 << TRI->getName(*AliasSet)
    652652 << "[%reg" << VirtReg <<"], removing it from live set\n";
    653653 removePhysReg(*AliasSet);
    654654 }
    661661 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    662662 MachineOperand& MO = MI->getOperand(i);
    663663 if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
    664 MRegisterInfo::isPhysicalRegister(MO.getReg())) {
    664 TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
    665665 unsigned Reg = MO.getReg();
    666666 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
    667667 // These are extra physical register defs when a sub-register
    674674 PhysRegsUsed[Reg] = 0; // It is free and reserved now
    675675 AddToPhysRegsUseOrder(Reg);
    676676
    677 for (const unsigned *AliasSet = MRI->getSubRegisters(Reg);
    677 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
    678678 *AliasSet; ++AliasSet) {
    679679 if (PhysRegsUsed[*AliasSet] != -2) {
    680680 MF->getRegInfo().setPhysRegUsed(*AliasSet);
    696696 PhysRegsUsed[Reg] = 0; // It is free and reserved now
    697697 }
    698698 MF->getRegInfo().setPhysRegUsed(Reg);
    699 for (const unsigned *AliasSet = MRI->getSubRegisters(Reg);
    699 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
    700700 *AliasSet; ++AliasSet) {
    701701 if (PhysRegsUsed[*AliasSet] != -2) {
    702702 AddToPhysRegsUseOrder(*AliasSet);
    722722 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    723723 MachineOperand& MO = MI->getOperand(i);
    724724 if (MO.isRegister() && MO.isDef() && MO.getReg() &&
    725 MRegisterInfo::isVirtualRegister(MO.getReg())) {
    725 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
    726726 unsigned DestVirtReg = MO.getReg();
    727727 unsigned DestPhysReg;
    728728
    742742 for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
    743743 unsigned VirtReg = DeadDefs[i];
    744744 unsigned PhysReg = VirtReg;
    745 if (MRegisterInfo::isVirtualRegister(VirtReg)) {
    745 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
    746746 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
    747747 PhysReg = PhysRegSlot;
    748748 assert(PhysReg != 0);
    753753 }
    754754
    755755 if (PhysReg) {
    756 DOUT << " Register " << MRI->getName(PhysReg)
    756 DOUT << " Register " << TRI->getName(PhysReg)
    757757 << " [%reg" << VirtReg
    758758 << "] is never used, removing it frame live list\n";
    759759 removePhysReg(PhysReg);
    760 for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg);
    760 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
    761761 *AliasSet; ++AliasSet) {
    762762 if (PhysRegsUsed[*AliasSet] != -2) {
    763 DOUT << " Register " << MRI->getName(*AliasSet)
    763 DOUT << " Register " << TRI->getName(*AliasSet)
    764764 << " [%reg" << *AliasSet
    765765 << "] is never used, removing it frame live list\n";
    766766 removePhysReg(*AliasSet);
    778778 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
    779779
    780780 // Spill all physical registers holding virtual registers now.
    781 for (unsigned i = 0, e = MRI->getNumRegs(); i != e; ++i)
    781 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
    782782 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
    783783 if (unsigned VirtReg = PhysRegsUsed[i])
    784784 spillVirtReg(MBB, MI, VirtReg, i);
    788788 #if 0
    789789 // This checking code is very expensive.
    790790 bool AllOk = true;
    791 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
    791 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
    792792 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
    793793 if (unsigned PR = Virt2PhysRegMap[i]) {
    794794 cerr << "Register still mapped: " << i << " -> " << PR << "\n";
    810810 DOUT << "Machine Function " << "\n";
    811811 MF = &Fn;
    812812 TM = &Fn.getTarget();
    813 MRI = TM->getRegisterInfo();
    813 TRI = TM->getRegisterInfo();
    814814 TII = TM->getInstrInfo();
    815815
    816 PhysRegsUsed.assign(MRI->getNumRegs(), -1);
    816 PhysRegsUsed.assign(TRI->getNumRegs(), -1);
    817817
    818818 // At various places we want to efficiently check to see whether a register
    819819 // is allocatable. To handle this, we mark all unallocatable registers as
    820820 // being pinned down, permanently.
    821821 {
    822 BitVector Allocable = MRI->getAllocatableSet(Fn);
    822 BitVector Allocable = TRI->getAllocatableSet(Fn);
    823823 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
    824824 if (!Allocable[i])
    825825 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
    830830 unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
    831831 Virt2PhysRegMap.grow(LastVirtReg);
    832832 Virt2LastUseMap.grow(LastVirtReg);
    833 VirtRegModified.resize(LastVirtReg+1-MRegisterInfo::FirstVirtualRegister);
    833 VirtRegModified.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
    834834
    835835 // Loop over all of the basic blocks, eliminating virtual register references
    836836 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
    4343 private:
    4444 MachineFunction *MF;
    4545 const TargetMachine *TM;
    46 const MRegisterInfo *MRI;
    46 const TargetRegisterInfo *TRI;
    4747
    4848 // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
    4949 // these values are spilled
    168168 // Made to combat the incorrect allocation of r2 = add r1, r1
    169169 std::map Virt2PhysRegMap;
    170170