llvm.org GIT mirror llvm / 6e50c92
MIR Serialization: Serialize the machine basic block live in registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242204 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Lorenz 5 years ago
7 changed file(s) with 93 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
101101 unsigned Alignment = 0;
102102 bool IsLandingPad = false;
103103 bool AddressTaken = false;
104 // TODO: Serialize the successor weights and liveins.
104 // TODO: Serialize the successor weights.
105105 std::vector Successors;
106
106 std::vector LiveIns;
107107 std::vector Instructions;
108108 };
109109
116116 YamlIO.mapOptional("isLandingPad", MBB.IsLandingPad);
117117 YamlIO.mapOptional("addressTaken", MBB.AddressTaken);
118118 YamlIO.mapOptional("successors", MBB.Successors);
119 YamlIO.mapOptional("liveins", MBB.LiveIns);
119120 YamlIO.mapOptional("instructions", MBB.Instructions);
120121 }
121122 };
7777
7878 bool parse(MachineInstr *&MI);
7979 bool parseMBB(MachineBasicBlock *&MBB);
80 bool parseNamedRegister(unsigned &Reg);
8081
8182 bool parseRegister(unsigned &Reg);
8283 bool parseRegisterFlag(unsigned &Flags);
211212 if (Token.isNot(MIToken::Eof))
212213 return error(
213214 "expected end of string after the machine basic block reference");
215 return false;
216 }
217
218 bool MIParser::parseNamedRegister(unsigned &Reg) {
219 lex();
220 if (Token.isNot(MIToken::NamedRegister))
221 return error("expected a named register");
222 if (parseRegister(Reg))
223 return 0;
224 lex();
225 if (Token.isNot(MIToken::Eof))
226 return error("expected end of string after the register reference");
214227 return false;
215228 }
216229
582595 const SlotMapping &IRSlots, SMDiagnostic &Error) {
583596 return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseMBB(MBB);
584597 }
598
599 bool llvm::parseNamedRegisterReference(unsigned &Reg, SourceMgr &SM,
600 MachineFunction &MF, StringRef Src,
601 const PerFunctionMIParsingState &PFS,
602 const SlotMapping &IRSlots,
603 SMDiagnostic &Error) {
604 return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseNamedRegister(Reg);
605 }
3939 const PerFunctionMIParsingState &PFS,
4040 const SlotMapping &IRSlots, SMDiagnostic &Error);
4141
42 bool parseNamedRegisterReference(unsigned &Reg, SourceMgr &SM,
43 MachineFunction &MF, StringRef Src,
44 const PerFunctionMIParsingState &PFS,
45 const SlotMapping &IRSlots,
46 SMDiagnostic &Error);
47
4248 } // end namespace llvm
4349
4450 #endif
320320 // TODO: Report an error when adding the same successor more than once.
321321 MBB.addSuccessor(SuccMBB);
322322 }
323 // Parse the liveins.
324 for (const auto &LiveInSource : YamlMBB.LiveIns) {
325 unsigned Reg = 0;
326 if (parseNamedRegisterReference(Reg, SM, MF, LiveInSource.Value, PFS,
327 IRSlots, Error))
328 return error(Error, LiveInSource.SourceRange);
329 MBB.addLiveIn(Reg);
330 }
323331 // Parse the instructions.
324332 for (const auto &MISource : YamlMBB.Instructions) {
325333 MachineInstr *MI = nullptr;
232232 MIPrinter(StrOS, MST, RegisterMaskIds).printMBBReference(*SuccMBB);
233233 YamlMBB.Successors.push_back(StrOS.str());
234234 }
235
235 // Print the live in registers.
236 const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
237 assert(TRI && "Expected target register info");
238 for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
239 std::string Str;
240 raw_string_ostream StrOS(Str);
241 printReg(*I, StrOS, TRI);
242 YamlMBB.LiveIns.push_back(StrOS.str());
243 }
236244 // Print the machine instructions.
237245 YamlMBB.Instructions.reserve(MBB.size());
238246 std::string Str;
0 # RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
1 # This test ensures that the MIR parser parses basic block liveins correctly.
2
3 --- |
4
5 define i32 @test(i32 %a, i32 %b) {
6 body:
7 %c = add i32 %a, %b
8 ret i32 %c
9 }
10
11 ...
12 ---
13 name: test
14 body:
15 # CHECK: name: body
16 # CHECK: liveins: [ '%edi', '%esi' ]
17 # CHECK-NEXT: instructions:
18 - id: 0
19 name: body
20 liveins: [ '%edi', '%esi' ]
21 instructions:
22 - '%eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _'
23 - 'RETQ %eax'
24 ...
0 # RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
1
2 --- |
3
4 define i32 @test(i32 %a) {
5 body:
6 ret i32 %a
7 }
8
9 ...
10 ---
11 name: test
12 body:
13 - id: 0
14 name: body
15 # CHECK: [[@LINE+1]]:21: expected a named register
16 liveins: [ '%0' ]
17 instructions:
18 - '%eax = COPY %edi'
19 - 'RETQ %eax'
20 ...