llvm.org GIT mirror llvm / 6e3c4da
Reduce global namespace pollution. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284521 91177308-0d34-0410-b5e6-96231b3b80d8 Benjamin Kramer 3 years ago
7 changed file(s) with 15 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
4040 using namespace llvm;
4141 using namespace lto;
4242
43 LLVM_ATTRIBUTE_NORETURN void reportOpenError(StringRef Path, Twine Msg) {
43 LLVM_ATTRIBUTE_NORETURN static void reportOpenError(StringRef Path, Twine Msg) {
4444 errs() << "failed to open " << Path << ": " << Msg << '\n';
4545 errs().flush();
4646 exit(1);
11931193 // On Linux, the number of physical cores can be computed from /proc/cpuinfo,
11941194 // using the number of unique physical/core id pairs. The following
11951195 // implementation reads the /proc/cpuinfo format on an x86_64 system.
1196 int computeHostNumPhysicalCores() {
1196 static int computeHostNumPhysicalCores() {
11971197 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
11981198 // mmapped because it appears to have 0 size.
11991199 llvm::ErrorOr> Text =
12351235 }
12361236 #else
12371237 // On other systems, return -1 to indicate unknown.
1238 int computeHostNumPhysicalCores() { return -1; }
1238 static int computeHostNumPhysicalCores() { return -1; }
12391239 #endif
12401240
12411241 int sys::getHostNumPhysicalCores() {
4646
4747 // Forward declare because the autogenerated code will reference this.
4848 // Definition is further down.
49 DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
50 uint64_t Address, const void *Decoder);
49 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
50 uint64_t Address,
51 const void *Decoder);
5152
5253 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
5354 uint64_t Address, const void *Decoder);
7272 return 0;
7373 }
7474
75 MCRelocationInfo *createLanaiElfRelocation(const Triple &TheTriple,
76 MCContext &Ctx) {
75 static MCRelocationInfo *createLanaiElfRelocation(const Triple &TheTriple,
76 MCContext &Ctx) {
7777 return createMCRelocationInfo(TheTriple, Ctx);
7878 }
7979
80 namespace {
8081 class LanaiMCInstrAnalysis : public MCInstrAnalysis {
8182 public:
8283 explicit LanaiMCInstrAnalysis(const MCInstrInfo *Info)
105106 }
106107 }
107108 };
109 } // end anonymous namespace
108110
109111 static MCInstrAnalysis *createLanaiInstrAnalysis(const MCInstrInfo *Info) {
110112 return new LanaiMCInstrAnalysis(Info);
2915029150 // into:
2915129151 // srl(ctlz x), log2(bitsize(x))
2915229152 // Input pattern is checked by caller.
29153 SDValue lowerX86CmpEqZeroToCtlzSrl(SDValue Op, EVT ExtTy, SelectionDAG &DAG) {
29153 static SDValue lowerX86CmpEqZeroToCtlzSrl(SDValue Op, EVT ExtTy,
29154 SelectionDAG &DAG) {
2915429155 SDValue Cmp = Op.getOperand(1);
2915529156 EVT VT = Cmp.getOperand(0).getValueType();
2915629157 unsigned Log2b = Log2_32(VT.getSizeInBits());
1515 #include "X86InstrInfo.h"
1616 #include "llvm/Support/ManagedStatic.h"
1717 #include "llvm/Support/Threading.h"
18 using namespace llvm;
1819
1920 /// This flag is used in the method llvm::call_once() used below to make the
2021 /// initialization of the map 'OpcodeToGroup' thread safe.
1919 #include
2020 #include
2121
22 using namespace llvm;
23
22 namespace llvm {
2423 /// This class is used to group {132, 213, 231} forms of FMA opcodes together.
2524 /// Each of the groups has either 3 register opcodes, 3 memory opcodes,
2625 /// or 6 register and memory opcodes. Also, each group has an attrubutes field
310309 return rm_iterator(getX86InstrFMA3Info()->OpcodeToGroup.end());
311310 }
312311 };
312 } // namespace llvm
313313
314314 #endif