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Use the dwarf->llvm mapping to print register names in the cfi directives. Fixes PR9826. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 8 years ago
40 changed file(s) with 183 addition(s) and 26 deletion(s). Raw diff Collapse all Expand all
9494 return TRI->getDwarfRegNum(RegNum, isEH);
9595 }
9696
97 int getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
98 return TRI->getLLVMRegNum(DwarfRegNum, isEH);
99 }
100
97101 int getSEHRegNum(unsigned RegNum) const {
98102 return TRI->getSEHRegNum(RegNum);
99103 }
801801 /// debugging info.
802802 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
803803
804 virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const = 0;
805
804806 /// getFrameRegister - This method should return the register used as a base
805807 /// for values allocated in the current stack frame.
806808 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
5252 DenseMap FlagMap;
5353
5454 bool needsSet(const MCExpr *Value);
55
56 void EmitRegisterName(int64_t Register);
5557
5658 public:
5759 MCAsmStreamer(MCContext &Context, formatted_raw_ostream &os,
818820 EmitEOL();
819821 }
820822
823 void MCAsmStreamer::EmitRegisterName(int64_t Register) {
824 if (InstPrinter) {
825 const TargetAsmInfo &asmInfo = getContext().getTargetAsmInfo();
826 unsigned LLVMRegister = asmInfo.getLLVMRegNum(Register, true);
827 OS << '%' << InstPrinter->getRegName(LLVMRegister);
828 } else {
829 OS << Register;
830 }
831 }
832
821833 void MCAsmStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) {
822834 MCStreamer::EmitCFIDefCfa(Register, Offset);
823835
824836 if (!UseCFI)
825837 return;
826838
827 OS << "\t.cfi_def_cfa " << Register << ", " << Offset;
839 OS << "\t.cfi_def_cfa ";
840 EmitRegisterName(Register);
841 OS << ", " << Offset;
828842 EmitEOL();
829843 }
830844
844858 if (!UseCFI)
845859 return;
846860
847 OS << "\t.cfi_def_cfa_register " << Register;
861 OS << "\t.cfi_def_cfa_register ";
862 EmitRegisterName(Register);
848863 EmitEOL();
849864 }
850865
854869 if (!UseCFI)
855870 return;
856871
857 OS << "\t.cfi_offset " << Register << ", " << Offset;
872 OS << "\t.cfi_offset ";
873 EmitRegisterName(Register);
874 OS << ", " << Offset;
858875 EmitEOL();
859876 }
860877
905922 if (!UseCFI)
906923 return;
907924
908 OS << "\t.cfi_same_value " << Register;
925 OS << "\t.cfi_same_value ";
926 EmitRegisterName(Register);
909927 EmitEOL();
910928 }
911929
915933 if (!UseCFI)
916934 return;
917935
918 OS << "\t.cfi_rel_offset " << Register << ", " << Offset;
936 OS << "\t.cfi_rel_offset ";
937 EmitRegisterName(Register);
938 OS << ", " << Offset;
919939 EmitEOL();
920940 }
921941
683683 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
684684 }
685685
686 int ARMBaseRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
687 return ARMGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
688 }
689
686690 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
687691 const MachineFunction &MF) const {
688692 switch (Reg) {
171171 unsigned getEHHandlerRegister() const;
172172
173173 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
174 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
174175
175176 bool isLowRegister(unsigned Reg) const;
176177
198198 return -1;
199199 }
200200
201 int AlphaRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
202 llvm_unreachable("What is the dwarf register number");
203 return -1;
204 }
205
201206 #include "AlphaGenRegisterInfo.inc"
202207
203208 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
4747 unsigned getEHHandlerRegister() const;
4848
4949 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
50 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
5051
5152 static std::string getPrettyName(unsigned reg);
5253 };
350350 return -1;
351351 }
352352
353 int BlackfinRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum,
354 bool isEH) const {
355 llvm_unreachable("What is the dwarf register number");
356 return -1;
357 }
358
353359 #include "BlackfinGenRegisterInfo.inc"
354360
5959 unsigned getEHHandlerRegister() const;
6060
6161 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
62 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
6263
6364 // Utility functions
6465 void adjustRegister(MachineBasicBlock &MBB,
327327 return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
328328 }
329329
330 int SPURegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
331 return SPUGenRegisterInfo::getLLVMRegNumFull(RegNum, 0);
332 }
333
330334 int
331335 SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
332336 {
8282
8383 //! Get DWARF debugging register number
8484 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
85 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
8586
8687 //! Convert D-form load/store to X-form load/store
8788 /*!
355355 return MBlazeGenRegisterInfo::getDwarfRegNumFull(RegNo,0);
356356 }
357357
358 int MBlazeRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
359 return MBlazeGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
360 }
361
358362 #include "MBlazeGenRegisterInfo.inc"
359363
7474 unsigned getEHHandlerRegister() const;
7575
7676 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
77 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
7778 };
7879
7980 } // end namespace llvm
241241 return 0;
242242 }
243243
244 int MSP430RegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
245 llvm_unreachable("Not implemented yet!");
246 return 0;
247 }
248
244249 #include "MSP430GenRegisterInfo.inc"
6060
6161 //! Get DWARF debugging register number
6262 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
63 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
6364 };
6465
6566 } // end namespace llvm
277277 return MipsGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
278278 }
279279
280 int MipsRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
281 return MipsGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
282 }
283
280284 #include "MipsGenRegisterInfo.inc"
6262 unsigned getEHHandlerRegister() const;
6363
6464 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
65 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
6566 };
6667
6768 } // end namespace llvm
5656 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const {
5757 return PTXGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
5858 }
59 virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const {
60 return PTXGenRegisterInfo::getLLVMRegNumFull(RegNum, 0);
61 }
5962 }; // struct PTXRegisterInfo
6063 } // namespace llvm
6164
2525 return getInstructionName(Opcode);
2626 }
2727
28 StringRef PPCInstPrinter::getRegName(unsigned RegNo) const {
29 return getRegisterName(RegNo);
30 }
2831
2932 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
3033 // Check for slwi/srwi mnemonics.
3232 return SyntaxVariant == 1;
3333 }
3434
35 StringRef getRegName(unsigned RegNo) const;
3536 virtual void printInst(const MCInst *MI, raw_ostream &O);
3637 virtual StringRef getOpcodeName(unsigned Opcode) const;
3738
486486 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
487487 unsigned Reg = CSI[I].getReg();
488488 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
489
490 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
491 // subregisters of CR2. We just need to emit a move of CR2.
492 if (Reg == PPC::CR2LT || Reg == PPC::CR2GT || Reg == PPC::CR2EQ)
493 continue;
494 if (Reg == PPC::CR2UN)
495 Reg = PPC::CR2;
496
489497 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
490498 MachineLocation CSSrc(Reg);
491499 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
701701 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, Flavour);
702702 }
703703
704 int PPCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
705 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
706 unsigned Flavour = Subtarget.isPPC64() ?
707 DWARFFlavour::PPC64 : DWARFFlavour::PPC32;
708
709 return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour);
710 }
711
704712 #include "PPCGenRegisterInfo.inc"
6767 unsigned getEHHandlerRegister() const;
6868
6969 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
70 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
7071 };
7172
7273 } // end namespace llvm
129129 return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
130130 }
131131
132 int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
133 return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
134 }
135
132136 #include "SparcGenRegisterInfo.inc"
133137
5151 unsigned getEHHandlerRegister() const;
5252
5353 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
54 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
5455 };
5556
5657 } // end namespace llvm
138138 return -1;
139139 }
140140
141 int SystemZRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
142 assert(0 && "What is the dwarf register number");
143 return -1;
144 }
145
146
141147 #include "SystemZGenRegisterInfo.inc"
5353 unsigned getEHHandlerRegister() const;
5454
5555 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
56 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
5657 };
5758
5859 } // end namespace llvm
3838 // Initialize the set of available features.
3939 setAvailableFeatures(ComputeAvailableFeatures(
4040 &TM.getSubtarget()));
41 }
42
43 StringRef X86ATTInstPrinter::getRegName(unsigned RegNo) const {
44 return getRegisterName(RegNo);
4145 }
4246
4347 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
2525 public:
2626 X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI);
2727
28 StringRef getRegName(unsigned RegNo) const;
2829 virtual void printInst(const MCInst *MI, raw_ostream &OS);
2930 virtual StringRef getOpcodeName(unsigned Opcode) const;
3031
2727 // Include the auto-generated portion of the assembly writer.
2828 #define GET_INSTRUCTION_NAME
2929 #include "X86GenAsmWriter1.inc"
30
31 StringRef X86IntelInstPrinter::getRegName(unsigned RegNo) const {
32 return getRegisterName(RegNo);
33 }
3034
3135 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
3236 printInstruction(MI, OS);
2626 X86IntelInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
2727 : MCInstPrinter(MAI) {}
2828
29 StringRef getRegName(unsigned RegNo) const;
2930 virtual void printInst(const MCInst *MI, raw_ostream &OS);
3031 virtual StringRef getOpcodeName(unsigned Opcode) const;
3132
7272 }
7373 }
7474
75 static unsigned getFlavour(const X86Subtarget *Subtarget, bool isEH) {
76 if (!Subtarget->is64Bit()) {
77 if (Subtarget->isTargetDarwin()) {
78 if (isEH)
79 return DWARFFlavour::X86_32_DarwinEH;
80 else
81 return DWARFFlavour::X86_32_Generic;
82 } else if (Subtarget->isTargetCygMing()) {
83 // Unsupported by now, just quick fallback
84 return DWARFFlavour::X86_32_Generic;
85 } else {
86 return DWARFFlavour::X86_32_Generic;
87 }
88 }
89 return DWARFFlavour::X86_64;
90 }
91
7592 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
7693 /// specific numbering, used in debug info and exception tables.
7794 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
7895 const X86Subtarget *Subtarget = &TM.getSubtarget();
79 unsigned Flavour = DWARFFlavour::X86_64;
80
81 if (!Subtarget->is64Bit()) {
82 if (Subtarget->isTargetDarwin()) {
83 if (isEH)
84 Flavour = DWARFFlavour::X86_32_DarwinEH;
85 else
86 Flavour = DWARFFlavour::X86_32_Generic;
87 } else if (Subtarget->isTargetCygMing()) {
88 // Unsupported by now, just quick fallback
89 Flavour = DWARFFlavour::X86_32_Generic;
90 } else {
91 Flavour = DWARFFlavour::X86_32_Generic;
92 }
93 }
96 unsigned Flavour = getFlavour(Subtarget, isEH);
9497
9598 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
99 }
100
101 /// getLLVMRegNum - This function maps DWARF register numbers to LLVM register.
102 int X86RegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
103 const X86Subtarget *Subtarget = &TM.getSubtarget();
104 unsigned Flavour = getFlavour(Subtarget, isEH);
105
106 return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour);
96107 }
97108
98109 int
7979 /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
8080 /// (created by TableGen) for target dependencies.
8181 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
82 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
8283
8384 // FIXME: This should be tablegen'd like getDwarfRegNum is
8485 int getSEHRegNum(unsigned i) const;
314314 return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
315315 }
316316
317 int XCoreRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
318 return XCoreGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
319 }
320
317321 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
318322 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
319323
7474
7575 //! Get DWARF debugging register number
7676 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
77 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
7778 };
7879
7980 } // end namespace llvm
0 ; Check that eh_return & unwind_init were properly lowered
1 ; RUN: llc < %s | grep %ebp | count 7
1 ; RUN: llc < %s | grep %ebp | count 9
22 ; RUN: llc < %s | grep %ecx | count 5
33
44 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
0 ; Check that eh_return & unwind_init were properly lowered
1 ; RUN: llc < %s | grep %rbp | count 5
1 ; RUN: llc < %s | grep %rbp | count 7
22 ; RUN: llc < %s | grep %rcx | count 3
33
44 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
1919 ; CHECK-FP-NEXT: :
2020 ; CHECK-FP-NEXT: .cfi_def_cfa_offset 16
2121 ; CHECK-FP-NEXT: :
22 ; CHECK-FP-NEXT: .cfi_offset 6, -16
22 ; CHECK-FP-NEXT: .cfi_offset %rbp, -16
2323 ; CHECK-FP-NEXT: movq %rsp, %rbp
2424 ; CHECK-FP-NEXT: :
25 ; CHECK-FP-NEXT: .cfi_def_cfa_register 6
25 ; CHECK-FP-NEXT: .cfi_def_cfa_register %rbp
2626 ; CHECK-FP-NEXT: nop
2727 ; CHECK-FP-NEXT: :
2828 ; CHECK-FP-NEXT: .cfi_endproc
88 ; CHECK-NEXT: :
99 ; CHECK-NEXT: .cfi_def_cfa_offset 16
1010 ; CHECK-NEXT: :
11 ; CHECK-NEXT: .cfi_offset 6, -16
11 ; CHECK-NEXT: .cfi_offset %rbp, -16
1212 ; CHECK-NEXT: movq %rsp, %rbp
1313 ; CHECK-NEXT: :
14 ; CHECK-NEXT: .cfi_def_cfa_register 6
14 ; CHECK-NEXT: .cfi_def_cfa_register %rbp
1515 ; CHECK-NEXT: popq %rbp
1616 ; CHECK-NEXT: ret
7878 << " explicit " << ClassName
7979 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
8080 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
81 << "unsigned Flavour) const;\n"
82 << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
8183 << "unsigned Flavour) const;\n"
8284 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
8385 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
988990 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
989991 I->second.push_back(-1);
990992
993 // Emit reverse information about the dwarf register numbers.
994 OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, "
995 << "unsigned Flavour) const {\n"
996 << " switch (Flavour) {\n"
997 << " default:\n"
998 << " assert(0 && \"Unknown DWARF flavour\");\n"
999 << " return -1;\n";
1000
1001 for (unsigned i = 0, e = maxLength; i != e; ++i) {
1002 OS << " case " << i << ":\n"
1003 << " switch (DwarfRegNum) {\n"
1004 << " default:\n"
1005 << " assert(0 && \"Invalid DwarfRegNum\");\n"
1006 << " return -1;\n";
1007
1008 for (DwarfRegNumsMapTy::iterator
1009 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
1010 int DwarfRegNo = I->second[i];
1011 if (DwarfRegNo >= 0)
1012 OS << " case " << DwarfRegNo << ":\n"
1013 << " return " << getQualifiedName(I->first) << ";\n";
1014 }
1015 OS << " };\n";
1016 }
1017
1018 OS << " };\n}\n\n";
1019
9911020 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
9921021 Record *Reg = Regs[i].TheDef;
9931022 const RecordVal *V = Reg->getValue("DwarfAlias");