llvm.org GIT mirror llvm / 6e006d3
[ms-inline asm] Use the new API introduced in r165830 in lieu of the MapAndConstraints vector. Also remove the unused Kind argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165833 91177308-0d34-0410-b5e6-96231b3b80d8 Chad Rosier 7 years ago
6 changed file(s) with 37 addition(s) and 71 deletion(s). Raw diff Collapse all Expand all
4949 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
5050 SMLoc &EndLoc) = 0;
5151
52 /// MapAndConstraints - Map inline assembly operands to MCInst operands
53 /// and an associated constraint.
54 typedef std::pair< unsigned, std::string > MapAndConstraint;
55 typedef SmallVector MatchInstMapAndConstraints;
56 typedef SmallVectorImpl MatchInstMapAndConstraintsImpl;
57
5852 /// ParseInstruction - Parse one assembly instruction.
5953 ///
6054 /// The parser is positioned following the instruction name. The target
9690 virtual bool
9791 MatchInstruction(SMLoc IDLoc,
9892 SmallVectorImpl &Operands,
99 MCStreamer &Out, unsigned &Kind, unsigned &Opcode,
100 MatchInstMapAndConstraintsImpl &MapAndConstraints,
101 unsigned &OrigErrorInfo, bool matchingInlineAsm = false) {
93 MCStreamer &Out, unsigned &Opcode, unsigned &OrigErrorInfo,
94 bool matchingInlineAsm = false) {
10295 OrigErrorInfo = ~0x0;
10396 return true;
10497 }
121114 }
122115
123116 virtual void convertToMapAndConstraints(unsigned Kind,
124 const SmallVectorImpl &Operands,
125 MatchInstMapAndConstraintsImpl &MapAndConstraints) = 0;
117 const SmallVectorImpl &Operands) = 0;
126118 };
127119
128120 } // End llvm namespace
74777477 SmallVectorImpl &Operands,
74787478 MCStreamer &Out) {
74797479 MCInst Inst;
7480 unsigned Kind;
74817480 unsigned ErrorInfo;
74827481 unsigned MatchResult;
7483 MatchInstMapAndConstraints MapAndConstraints;
7484 MatchResult = MatchInstructionImpl(Operands, Kind, Inst,
7485 MapAndConstraints, ErrorInfo,
7482 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
74867483 /*matchingInlineAsm*/ false);
74877484 switch (MatchResult) {
74887485 default: break;
315315 SmallVectorImpl &Operands,
316316 MCStreamer &Out) {
317317 MCInst Inst;
318 unsigned Kind;
319318 unsigned ErrorInfo;
320 MatchInstMapAndConstraints MapAndConstraints;
321 switch (MatchInstructionImpl(Operands, Kind, Inst, MapAndConstraints,
322 ErrorInfo, /*matchingInlineAsm*/ false)) {
319 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo,
320 /*matchingInlineAsm*/ false)) {
323321 default: break;
324322 case Match_Success:
325323 Out.EmitInstruction(Inst);
455455 SmallVectorImpl &Operands,
456456 MCStreamer &Out) {
457457 MCInst Inst;
458 unsigned Kind;
459458 unsigned ErrorInfo;
460 MatchInstMapAndConstraints MapAndConstraints;
461 unsigned MatchResult = MatchInstructionImpl(Operands, Kind, Inst,
462 MapAndConstraints, ErrorInfo,
459 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
463460 /*matchingInlineAsm*/ false);
464461
465462 switch (MatchResult) {
6767 MCStreamer &Out);
6868 bool MatchInstruction(SMLoc IDLoc,
6969 SmallVectorImpl &Operands,
70 MCStreamer &Out, unsigned &Kind, unsigned &Opcode,
71 MatchInstMapAndConstraintsImpl &MapAndConstraints,
72 unsigned &OrigErrorInfo, bool matchingInlineAsm = false);
70 MCStreamer &Out, unsigned &Opcode,
71 unsigned &OrigErrorInfo, bool matchingInlineAsm = false);
7372
7473 /// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi)
7574 /// in 64bit mode or (%esi) or %es:(%esi) in 32bit mode.
15221521 MatchAndEmitInstruction(SMLoc IDLoc,
15231522 SmallVectorImpl &Operands,
15241523 MCStreamer &Out) {
1525 unsigned Kind;
15261524 unsigned Opcode;
15271525 unsigned ErrorInfo;
1528 MatchInstMapAndConstraints MapAndConstraints;
1529 bool Error = MatchInstruction(IDLoc, Operands, Out, Kind, Opcode,
1530 MapAndConstraints, ErrorInfo);
1526 bool Error = MatchInstruction(IDLoc, Operands, Out, Opcode, ErrorInfo);
15311527 return Error;
15321528 }
15331529
15341530 bool X86AsmParser::
15351531 MatchInstruction(SMLoc IDLoc,
15361532 SmallVectorImpl &Operands,
1537 MCStreamer &Out, unsigned &Kind, unsigned &Opcode,
1538 SmallVectorImpl > &MapAndConstraints,
1539 unsigned &OrigErrorInfo, bool matchingInlineAsm) {
1533 MCStreamer &Out, unsigned &Opcode, unsigned &OrigErrorInfo,
1534 bool matchingInlineAsm) {
15401535 assert(!Operands.empty() && "Unexpect empty operand list!");
15411536 X86Operand *Op = static_cast(Operands[0]);
15421537 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
15761571 MCInst Inst;
15771572
15781573 // First, try a direct match.
1579 switch (MatchInstructionImpl(Operands, Kind, Inst, MapAndConstraints,
1574 switch (MatchInstructionImpl(Operands, Inst,
15801575 OrigErrorInfo, matchingInlineAsm,
15811576 isParsingIntelSyntax())) {
15821577 default: break;
16281623 Tmp[Base.size()] = Suffixes[0];
16291624 unsigned ErrorInfoIgnore;
16301625 unsigned Match1, Match2, Match3, Match4;
1631 unsigned tKind;
1632
1633 MatchInstMapAndConstraints tMapAndConstraints[4];
1634 Match1 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[0],
1635 ErrorInfoIgnore, isParsingIntelSyntax());
1636 if (Match1 == Match_Success) Kind = tKind;
1626
1627 Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
1628 isParsingIntelSyntax());
16371629 Tmp[Base.size()] = Suffixes[1];
1638 Match2 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[1],
1639 ErrorInfoIgnore, isParsingIntelSyntax());
1640 if (Match2 == Match_Success) Kind = tKind;
1630 Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
1631 isParsingIntelSyntax());
16411632 Tmp[Base.size()] = Suffixes[2];
1642 Match3 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[2],
1643 ErrorInfoIgnore, isParsingIntelSyntax());
1644 if (Match3 == Match_Success) Kind = tKind;
1633 Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
1634 isParsingIntelSyntax());
16451635 Tmp[Base.size()] = Suffixes[3];
1646 Match4 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[3],
1647 ErrorInfoIgnore, isParsingIntelSyntax());
1648 if (Match4 == Match_Success) Kind = tKind;
1636 Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
1637 isParsingIntelSyntax());
16491638
16501639 // Restore the old token.
16511640 Op->setTokenValue(Base);
17131713 OpOS << "void " << Target.getName() << ClassName << "::\n"
17141714 << "convertToMapAndConstraints(unsigned Kind,\n";
17151715 OpOS.indent(27);
1716 OpOS << "const SmallVectorImpl &Operands,\n";
1717 OpOS.indent(27);
1718 OpOS << "MatchInstMapAndConstraintsImpl &MapAndConstraints) {\n"
1716 OpOS << "const SmallVectorImpl &Operands) {\n"
17191717 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
17201718 << " unsigned NumMCOperands = 0;\n"
17211719 << " const uint8_t *Converter = ConversionTable[Kind];\n"
17231721 << " switch (*p) {\n"
17241722 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
17251723 << " case CVT_Reg:\n"
1724 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1725 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1726 << " ++NumMCOperands;\n"
1727 << " break;\n"
17261728 << " case CVT_Tied:\n"
1727 << " MapAndConstraints.push_back(std::make_pair(NumMCOperands,"
1728 << "\"m\"));\n"
17291729 << " ++NumMCOperands;\n"
17301730 << " break;\n";
17311731
18221822
18231823 // Add a handler for the operand number lookup.
18241824 OpOS << " case " << Name << ":\n"
1825 << " MapAndConstraints.push_back(std::make_pair(NumMCOperands"
1826 << ",\"m\"));\n"
1825 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1826 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
18271827 << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
18281828 << " break;\n";
18291829 break;
18611861 << " break;\n";
18621862
18631863 OpOS << " case " << Name << ":\n"
1864 << " MapAndConstraints.push_back(std::make_pair(NumMCOperands"
1865 << ",\"\"));\n"
1864 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1865 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
18661866 << " ++NumMCOperands;\n"
18671867 << " break;\n";
18681868 break;
18921892 << " break;\n";
18931893
18941894 OpOS << " case " << Name << ":\n"
1895 << " MapAndConstraints.push_back(std::make_pair(NumMCOperands"
1896 << ",\"m\"));\n"
1895 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1896 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
18971897 << " ++NumMCOperands;\n"
18981898 << " break;\n";
18991899 }
26032603 << " const SmallVectorImpl "
26042604 << "&Operands);\n";
26052605 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2606 OS << " const SmallVectorImpl &Operands,\n";
2607 OS.indent(29);
2608 OS << "MatchInstMapAndConstraintsImpl &MapAndConstraints);\n";
2606 OS << " const SmallVectorImpl &Operands);\n";
26092607 OS << " bool mnemonicIsValid(StringRef Mnemonic);\n";
26102608 OS << " unsigned MatchInstructionImpl(\n";
26112609 OS.indent(27);
26122610 OS << "const SmallVectorImpl &Operands,\n"
2613 << " unsigned &Kind, MCInst &Inst,\n";
2614 OS.indent(30);
2615 OS << "MatchInstMapAndConstraintsImpl &MapAndConstraints,\n"
2611 << " MCInst &Inst,\n"
26162612 << " unsigned &ErrorInfo,"
26172613 << " bool matchingInlineAsm,\n"
26182614 << " unsigned VariantID = 0);\n";
28052801 << Target.getName() << ClassName << "::\n"
28062802 << "MatchInstructionImpl(const SmallVectorImpl"
28072803 << " &Operands,\n";
2808 OS << " unsigned &Kind, MCInst &Inst,\n"
2809 << "SmallVectorImpl > &MapAndConstraints,\n"
2804 OS << " MCInst &Inst,\n"
28102805 << "unsigned &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n";
28112806
28122807 OS << " // Eliminate obvious mismatches.\n";
29022897 OS << " }\n";
29032898 OS << "\n";
29042899 OS << " if (matchingInlineAsm) {\n";
2905 OS << " Kind = it->ConvertFn;\n";
29062900 OS << " Inst.setOpcode(it->Opcode);\n";
2907 OS << " convertToMapAndConstraints(it->ConvertFn, Operands, "
2908 << "MapAndConstraints);\n";
2901 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
29092902 OS << " return Match_Success;\n";
29102903 OS << " }\n\n";
29112904 OS << " // We have selected a definite instruction, convert the parsed\n"