llvm.org GIT mirror llvm / 6da8d99
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace hasInFlag, hasOutFlag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25155 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
8 changed file(s) with 23 addition(s) and 39 deletion(s). Raw diff Collapse all Expand all
4646 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
4747
4848 def SDT_PPCRetFlag : SDTypeProfile<0, 0, []>;
49 def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag, [SDNPHasChain]>;
49 def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag,
50 [SDNPHasChain, SDNPOptInFlag]>;
5051
5152 //===----------------------------------------------------------------------===//
5253 // PowerPC specific transformation functions and pattern fragments.
221222 }
222223
223224
224 let isTerminator = 1 in {
225 let isTerminator = 1, noResults = 1 in {
225226 // FIXME: temporary workaround for return without an incoming flag.
226 let isReturn = 1, noResults = 1 in
227 def BLRVOID : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(ret)]>;
228 let isReturn = 1, noResults = 1, hasInFlag = 1 in
229 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, []>;
230 let noResults = 1 in
227 let isReturn = 1 in
228 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
231229 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
232230 }
233231
10711069 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
10721070 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
10731071
1074 def : Pat<(retflag), (BLR)>;
1075
10761072 // Same as above, but using a temporary. FIXME: implement temporaries :)
10771073 /*
10781074 def : Pattern<(xor GPRC:$in, imm:$imm),
372372 const MachineFrameInfo *MFI = MF.getFrameInfo();
373373 MachineBasicBlock::iterator MBBI = prior(MBB.end());
374374 MachineInstr *MI;
375 // FIXME: BLRVOID should be removed. See PPCInstrInfo.td
376 assert((MBBI->getOpcode() == PPC::BLR || MBBI->getOpcode() == PPC::BLRVOID) &&
375 assert(MBBI->getOpcode() == PPC::BLR &&
377376 "Can only insert epilog into returning blocks");
378377
379378 // Get the number of bytes allocated from the FrameInfo...
9393 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
9494
9595 def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
96 def call : SDNode<"ISD::CALL", SDT_V8Call, [SDNPHasChain]>;
96 def call : SDNode<"ISD::CALL", SDT_V8Call,
97 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
9798
9899 def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
99 def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, [SDNPHasChain]>;
100 def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
101 [SDNPHasChain, SDNPOptInFlag]>;
100102
101103 //===----------------------------------------------------------------------===//
102104 // Instructions
172174 // special cases of JMPL:
173175 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
174176 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
175 // FIXME: temporary workaround for return without an incoming flag.
176 def RETVOID: F3_2<2, 0b111000, (ops), "retl", [(ret)]>;
177 let hasInFlag = 1 in
178 def RETL: F3_2<2, 0b111000, (ops), "retl", []>;
177 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>;
179178 }
180179
181180 // Section B.1 - Load Integer Instructions, p. 90
562561 // Section B.24 - Call and Link Instruction, p. 125
563562 // This is the only Format 1 instruction
564563 let Uses = [O0, O1, O2, O3, O4, O5],
565 hasDelaySlot = 1, isCall = 1, hasInFlag = 1, hasOutFlag = 1, noResults = 1,
564 hasDelaySlot = 1, isCall = 1, noResults = 1,
566565 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
567566 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
568567 def CALL : InstV8<(ops calltarget:$dst),
724723 def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
725724 def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
726725
727 // Return of a value, which has an input flag.
728 def : Pat<(retflag), (RETL)>;
729
730
731726 // Calls:
732727 def : Pat<(call tglobaladdr:$dst),
733728 (CALL tglobaladdr:$dst)>;
164164 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
165165 MachineBasicBlock &MBB) const {
166166 MachineBasicBlock::iterator MBBI = prior(MBB.end());
167 // FIXME: RETVOID should be removed. See SparcV8InstrInfo.td
168 assert((MBBI->getOpcode() == V8::RETL || MBBI->getOpcode() == V8::RETVOID) &&
167 assert(MBBI->getOpcode() == V8::RETL &&
169168 "Can only put epilog before 'retl' instruction!");
170169 BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
171170 }
9393 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
9494
9595 def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
96 def call : SDNode<"ISD::CALL", SDT_V8Call, [SDNPHasChain]>;
96 def call : SDNode<"ISD::CALL", SDT_V8Call,
97 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
9798
9899 def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
99 def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, [SDNPHasChain]>;
100 def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
101 [SDNPHasChain, SDNPOptInFlag]>;
100102
101103 //===----------------------------------------------------------------------===//
102104 // Instructions
172174 // special cases of JMPL:
173175 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
174176 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
175 // FIXME: temporary workaround for return without an incoming flag.
176 def RETVOID: F3_2<2, 0b111000, (ops), "retl", [(ret)]>;
177 let hasInFlag = 1 in
178 def RETL: F3_2<2, 0b111000, (ops), "retl", []>;
177 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>;
179178 }
180179
181180 // Section B.1 - Load Integer Instructions, p. 90
562561 // Section B.24 - Call and Link Instruction, p. 125
563562 // This is the only Format 1 instruction
564563 let Uses = [O0, O1, O2, O3, O4, O5],
565 hasDelaySlot = 1, isCall = 1, hasInFlag = 1, hasOutFlag = 1, noResults = 1,
564 hasDelaySlot = 1, isCall = 1, noResults = 1,
566565 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
567566 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
568567 def CALL : InstV8<(ops calltarget:$dst),
724723 def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
725724 def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
726725
727 // Return of a value, which has an input flag.
728 def : Pat<(retflag), (RETL)>;
729
730
731726 // Calls:
732727 def : Pat<(call tglobaladdr:$dst),
733728 (CALL tglobaladdr:$dst)>;
164164 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
165165 MachineBasicBlock &MBB) const {
166166 MachineBasicBlock::iterator MBBI = prior(MBB.end());
167 // FIXME: RETVOID should be removed. See SparcV8InstrInfo.td
168 assert((MBBI->getOpcode() == V8::RETL || MBBI->getOpcode() == V8::RETVOID) &&
167 assert(MBBI->getOpcode() == V8::RETL &&
169168 "Can only put epilog before 'retl' instruction!");
170169 BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
171170 }
168168 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
169169 bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
170170 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
171 bit hasInFlag = 0; // Does this instruction read a flag operand?
172 bit hasOutFlag = 0; // Does this instruction write a flag operand?
173171 bit noResults = 0; // Does this instruction produce no results?
174172
175173 InstrItinClass Itinerary; // Execution steps used for scheduling.
173173 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
174174 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
175175 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
176 def SDNPOutFlag : SDNodeProperty; // Write a flag result
177 def SDNPInFlag : SDNodeProperty; // Read a flag operand
178 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
176179
177180 //===----------------------------------------------------------------------===//
178181 // Selection DAG Node definitions.