llvm.org GIT mirror llvm / 6d6d352
Sometimes a MI can define a register as well as defining a super-register at the same time. Do not mark the "smaller" def as dead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41871 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 12 years ago
2 changed file(s) with 16 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
248248 }
249249
250250 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
251 // There is a now a proper use, forget about the last partial use.
252 PhysRegPartUse[Reg] = NULL;
253
254251 // Turn previous partial def's into read/mod/write.
255252 for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
256253 MachineInstr *Def = PhysRegPartDef[Reg][i];
265262 // A: EAX = ...
266263 // B: = AX
267264 // Add implicit def to A.
268 if (PhysRegInfo[Reg] && !PhysRegUsed[Reg]) {
265 if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] &&
266 !PhysRegUsed[Reg]) {
269267 MachineInstr *Def = PhysRegInfo[Reg];
270268 if (!Def->findRegisterDefOperand(Reg))
271269 Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
272270 }
273271
272 // There is a now a proper use, forget about the last partial use.
273 PhysRegPartUse[Reg] = NULL;
274274 PhysRegInfo[Reg] = MI;
275275 PhysRegUsed[Reg] = true;
276276
372372 } else if (PhysRegPartUse[SubReg])
373373 // Add implicit use / kill to last use of a sub-register.
374374 addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true);
375 else
375 else if (LastRef != MI)
376 // This must be a def of the subreg on the same MI.
376377 addRegisterDead(SubReg, LastRef);
377378 }
378379 }
380381 if (MI) {
381382 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
382383 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
383 if (PhysRegInfo[SuperReg]) {
384 if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) {
384385 // The larger register is previously defined. Now a smaller part is
385386 // being re-defined. Treat it as read/mod/write.
386387 // EAX =
0 ; RUN: llvm-as < %s | llc -march=ppc64
1
2 %struct.TCMalloc_SpinLock = type { i32 }
3
4 define void @_ZN17TCMalloc_SpinLock4LockEv(%struct.TCMalloc_SpinLock* %this) {
5 entry:
6 %tmp3 = call i32 asm sideeffect "1: lwarx $0, 0, $1\0A\09stwcx. $2, 0, $1\0A\09bne- 1b\0A\09isync", "=&r,=*r,r,1,~{dirflag},~{fpsr},~{flags},~{memory}"( i32** null, i32 1, i32* null ) ; [#uses=0]
7 unreachable
8 }