llvm.org GIT mirror llvm / 6d4b052
Split x86's ADJCALLSTACK instructions into 32-bit and 64-bit forms. This allows the 64-bit forms to use+def RSP instead of ESP. This doesn't fix any real bugs today, but it is more precise and it makes the debug dumps on x86-64 look more consistent. Also, add some comments describing the CALL instructions' physreg operand uses and defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56925 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 12 years ago
4 changed file(s) with 45 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
959959 unsigned NumBytes = CCInfo.getNextStackOffset();
960960
961961 // Issue CALLSEQ_START
962 BuildMI(MBB, TII.get(X86::ADJCALLSTACKDOWN)).addImm(NumBytes);
962 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
963 BuildMI(MBB, TII.get(AdjStackDown)).addImm(NumBytes);
963964
964965 // Process argumenet: walk the register/memloc assignments, inserting
965966 // copies / loads.
10501051 }
10511052
10521053 // Issue CALLSEQ_END
1053 BuildMI(MBB, TII.get(X86::ADJCALLSTACKUP)).addImm(NumBytes).addImm(0);
1054 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1055 BuildMI(MBB, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
10541056
10551057 // Now handle call return value (if any).
10561058 if (RetVT.getSimpleVT() != MVT::isVoid) {
8585 // Instruction list...
8686 //
8787
88 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
89 // a stack adjustment and the codegen must know that they may modify the stack
90 // pointer before prolog-epilog rewriting occurs.
91 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
92 // sub / add which can clobber EFLAGS.
93 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
94 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
95 "#ADJCALLSTACKDOWN",
96 [(X86callseq_start imm:$amt)]>,
97 Requires<[In64BitMode]>;
98 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
99 "#ADJCALLSTACKUP",
100 [(X86callseq_end imm:$amt1, imm:$amt2)]>,
101 Requires<[In64BitMode]>;
102 }
103
88104 //===----------------------------------------------------------------------===//
89105 // Call Instructions...
90106 //
91107 let isCall = 1 in
92 // All calls clobber the non-callee saved registers...
108 // All calls clobber the non-callee saved registers. RSP is marked as
109 // a use to prevent stack-pointer assignments that appear immediately
110 // before calls from potentially appearing dead. Uses for argument
111 // registers are added manually.
93112 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
94113 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
95114 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
320320 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
321321 // sub / add which can clobber EFLAGS.
322322 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
323 def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt),
324 "#ADJCALLSTACKDOWN",
325 [(X86callseq_start imm:$amt)]>;
326 def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
327 "#ADJCALLSTACKUP",
328 [(X86callseq_end imm:$amt1, imm:$amt2)]>;
323 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
324 "#ADJCALLSTACKDOWN",
325 [(X86callseq_start imm:$amt)]>,
326 Requires<[In32BitMode]>;
327 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
328 "#ADJCALLSTACKUP",
329 [(X86callseq_end imm:$amt1, imm:$amt2)]>,
330 Requires<[In32BitMode]>;
329331 }
330332
331333 // Nop
410412 // Call Instructions...
411413 //
412414 let isCall = 1 in
413 // All calls clobber the non-callee saved registers...
415 // All calls clobber the non-callee saved registers. ESP is marked as
416 // a use to prevent stack-pointer assignments that appear immediately
417 // before calls from potentially appearing dead. Uses for argument
418 // registers are added manually.
414419 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
415420 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
416421 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS],
4141
4242 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
4343 const TargetInstrInfo &tii)
44 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
44 : X86GenRegisterInfo(tm.getSubtarget().is64Bit() ?
45 X86::ADJCALLSTACKDOWN64 :
46 X86::ADJCALLSTACKDOWN32,
47 tm.getSubtarget().is64Bit() ?
48 X86::ADJCALLSTACKUP64 :
49 X86::ADJCALLSTACKUP32),
4550 TM(tm), TII(tii) {
4651 // Cache some information.
4752 const X86Subtarget *Subtarget = &TM.getSubtarget();
366371 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
367372
368373 MachineInstr *New = 0;
369 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
374 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
370375 New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
371376 StackPtr).addReg(StackPtr).addImm(Amount);
372377 } else {
373 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
378 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
374379 // factor out the amount the callee already popped.
375380 uint64_t CalleeAmt = Old->getOperand(1).getImm();
376381 Amount -= CalleeAmt;
386391 // Replace the pseudo instruction with a new instruction...
387392 if (New) MBB.insert(I, New);
388393 }
389 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
394 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
390395 // If we are performing frame pointer elimination and if the callee pops
391396 // something off the stack pointer, add it back. We do this until we have
392397 // more advanced stack pointer tracking ability.