llvm.org GIT mirror llvm / 6d32ca0
support for Schedule included on Mips.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41159 91177308-0d34-0410-b5e6-96231b3b80d8 Bruno Cardoso Lopes 13 years ago
2 changed file(s) with 15 addition(s) and 28 deletion(s). Raw diff Collapse all Expand all
55 // University of Illinois Open Source License. See LICENSE.TXT for details.
66 //
77 //===----------------------------------------------------------------------===//
8 // This is the top level entry point for the Mips target.
9 //===----------------------------------------------------------------------===//
810
911 //===----------------------------------------------------------------------===//
10 // Target-independent interfaces which we are implementing
12 // Target-independent interfaces
1113 //===----------------------------------------------------------------------===//
1214
1315 include "../Target.td"
1416
1517 //===----------------------------------------------------------------------===//
16 // Register File Description
18 // Descriptions
1719 //===----------------------------------------------------------------------===//
1820
1921 include "MipsRegisterInfo.td"
20
21 //===----------------------------------------------------------------------===//
22 // Subtarget features
23 //===----------------------------------------------------------------------===//
24
25 // TODO: dummy, needed to compile
26 def FeatureCIX : SubtargetFeature<"r3000", "isR3000", "true",
27 "Enable r3000 extentions">;
28
29 //===----------------------------------------------------------------------===//
30 // Instruction Description
31 //===----------------------------------------------------------------------===//
32
22 include "MipsSchedule.td"
3323 include "MipsInstrInfo.td"
24 include "MipsCallingConv.td"
3425
3526 def MipsInstrInfo : InstrInfo {
36 // Define how we want to layout our target-specific information field.
3727 let TSFlagsFields = [];
3828 let TSFlagsShifts = [];
3929 }
30
4031 //===----------------------------------------------------------------------===//
41 // Calling Conventions
32 // CPU Directives //
4233 //===----------------------------------------------------------------------===//
4334
44 include "MipsCallingConv.td"
35 def FeatureMipsIII : SubtargetFeature<"mips3", "IsMipsIII", "true",
36 "MipsIII ISA Support">;
4537
4638 //===----------------------------------------------------------------------===//
4739 // Mips processors supported.
4840 //===----------------------------------------------------------------------===//
4941
50 class Proc Features>
51 : Processor;
52
53 def : Proc<"generic", []>;
54
55 //===----------------------------------------------------------------------===//
56 // Declare the target which we are implementing
57 //===----------------------------------------------------------------------===//
42 def : Processor<"generic", MipsGenericItineraries, []>;
43 //def : Processor<"r4000", MipsR4000Itineraries, [FeatureMipsIII]>;
5844
5945 def Mips : Target {
60 // Pull in Instruction Info:
6146 let InstructionSet = MipsInstrInfo;
6247 }
48
1616 using namespace llvm;
1717
1818 MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M,
19 const std::string &FS) : isR3000(false)
19 const std::string &FS) :
20 IsMipsIII(false)
2021 {
2122 std::string CPU = "generic";
2223