llvm.org GIT mirror llvm / 6d2e516
Merging r246400: ------------------------------------------------------------------------ r246400 | hfinkel | 2015-08-30 18:12:50 -0400 (Sun, 30 Aug 2015) | 20 lines [PowerPC] Fixup SELECT_CC (and SETCC) patterns with i1 comparison operands There were really two problems here. The first was that we had the truth tables for signed i1 comparisons backward. I imagine these are not very common, but if you have: setcc i1 x, y, LT this has the '0 1' and the '1 0' results flipped compared to: setcc i1 x, y, ULT because, in the signed case, '1 0' is really '-1 0', and the answer is not the same as in the unsigned case. The second problem was that we did not have patterns (at all) for the unsigned comparisons select_cc nodes for i1 comparison operands. This was the specific cause of PR24552. These had to be added (and a missing Altivec promotion added as well) to make sure these function for all types. I've added a bunch more test cases for these patterns, and there are a few FIXMEs in the test case regarding code-quality. Fixes PR24552. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@252478 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 years ago
5 changed file(s) with 1853 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
430430 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
431431 setOperationAction(ISD::SELECT, VT, Promote);
432432 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
433 setOperationAction(ISD::SELECT_CC, VT, Promote);
434 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
433435 setOperationAction(ISD::STORE, VT, Promote);
434436 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
435437
28342834 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
28352835
28362836 // match setcc on i1 variables.
2837 // CRANDC is:
2838 // 1 1 : F
2839 // 1 0 : T
2840 // 0 1 : F
2841 // 0 0 : F
2842 //
2843 // LT is:
2844 // -1 -1 : F
2845 // -1 0 : T
2846 // 0 -1 : F
2847 // 0 0 : F
2848 //
2849 // ULT is:
2850 // 1 1 : F
2851 // 1 0 : F
2852 // 0 1 : T
2853 // 0 0 : F
28372854 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2838 (CRANDC $s2, $s1)>;
2855 (CRANDC $s1, $s2)>;
28392856 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
28402857 (CRANDC $s2, $s1)>;
2858 // CRORC is:
2859 // 1 1 : T
2860 // 1 0 : T
2861 // 0 1 : F
2862 // 0 0 : T
2863 //
2864 // LE is:
2865 // -1 -1 : T
2866 // -1 0 : T
2867 // 0 -1 : F
2868 // 0 0 : T
2869 //
2870 // ULE is:
2871 // 1 1 : T
2872 // 1 0 : F
2873 // 0 1 : T
2874 // 0 0 : T
28412875 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2842 (CRORC $s2, $s1)>;
2876 (CRORC $s1, $s2)>;
28432877 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
28442878 (CRORC $s2, $s1)>;
2879
28452880 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
28462881 (CREQV $s1, $s2)>;
2882
2883 // GE is:
2884 // -1 -1 : T
2885 // -1 0 : F
2886 // 0 -1 : T
2887 // 0 0 : T
2888 //
2889 // UGE is:
2890 // 1 1 : T
2891 // 1 0 : T
2892 // 0 1 : F
2893 // 0 0 : T
28472894 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2848 (CRORC $s1, $s2)>;
2895 (CRORC $s2, $s1)>;
28492896 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
28502897 (CRORC $s1, $s2)>;
2898
2899 // GT is:
2900 // -1 -1 : F
2901 // -1 0 : F
2902 // 0 -1 : T
2903 // 0 0 : F
2904 //
2905 // UGT is:
2906 // 1 1 : F
2907 // 1 0 : T
2908 // 0 1 : F
2909 // 0 0 : F
28512910 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2852 (CRANDC $s1, $s2)>;
2911 (CRANDC $s2, $s1)>;
28532912 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
28542913 (CRANDC $s1, $s2)>;
2914
28552915 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
28562916 (CRXOR $s1, $s2)>;
28572917
32023262 // select (lhs == rhs), tval, fval is:
32033263 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
32043264 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3265 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3266 (CRAND (CRORC $rhs, $lhs), $fval))>;
3267 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
32053268 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
32063269 (CRAND (CRORC $lhs, $rhs), $fval))>;
32073270 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3271 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3272 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3273 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),
32083274 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
32093275 (CRAND (CRANDC $lhs, $rhs), $fval))>;
32103276 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
32113277 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
32123278 (CRAND (CRXOR $lhs, $rhs), $fval))>;
32133279 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3280 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3281 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3282 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
32143283 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
32153284 (CRAND (CRANDC $rhs, $lhs), $fval))>;
32163285 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3286 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3287 (CRAND (CRORC $lhs, $rhs), $fval))>;
3288 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
32173289 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
32183290 (CRAND (CRORC $rhs, $lhs), $fval))>;
32193291 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
32223294
32233295 // match selectcc on i1 variables with non-i1 output.
32243296 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3297 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3298 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
32253299 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
32263300 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3301 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3302 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),
32273303 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
32283304 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
32293305 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
32303306 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3307 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3308 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
32313309 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
32323310 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3311 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3312 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
32333313 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
32343314 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
32353315 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
32363316
32373317 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3318 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3319 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
32383320 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
32393321 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3322 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3323 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)),
32403324 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
32413325 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
32423326 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
32433327 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3328 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3329 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)),
32443330 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
32453331 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3332 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3333 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
32463334 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
32473335 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
32483336 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
32493337
32503338 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3339 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3340 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
32513341 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
32523342 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3343 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3344 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
32533345 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
32543346 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
32553347 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
32563348 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3349 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3350 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
32573351 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
32583352 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3353 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3354 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
32593355 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
32603356 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
32613357 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
32623358
32633359 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3360 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3361 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
32643362 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
32653363 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3364 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3365 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
32663366 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
32673367 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
32683368 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
32693369 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3370 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3371 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
32703372 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
32713373 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3374 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3375 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
32723376 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
32733377 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
32743378 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
32753379
32763380 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3381 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3382 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)),
32773383 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
32783384 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3385 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3386 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)),
32793387 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
32803388 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
32813389 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
32823390 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3391 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3392 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)),
32833393 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
32843394 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3395 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3396 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)),
32853397 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
32863398 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
32873399 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
11141114 (COPY_TO_REGCLASS $src, QFRC)>;
11151115
11161116 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETLT)),
1117 (SELECT_QFRC (CRANDC $lhs, $rhs), $tval, $fval)>;
1118 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETULT)),
11171119 (SELECT_QFRC (CRANDC $rhs, $lhs), $tval, $fval)>;
11181120 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETLE)),
1121 (SELECT_QFRC (CRORC $lhs, $rhs), $tval, $fval)>;
1122 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETULE)),
11191123 (SELECT_QFRC (CRORC $rhs, $lhs), $tval, $fval)>;
11201124 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETEQ)),
11211125 (SELECT_QFRC (CREQV $lhs, $rhs), $tval, $fval)>;
11221126 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETGE)),
1127 (SELECT_QFRC (CRORC $rhs, $lhs), $tval, $fval)>;
1128 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETUGE)),
11231129 (SELECT_QFRC (CRORC $lhs, $rhs), $tval, $fval)>;
11241130 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETGT)),
1131 (SELECT_QFRC (CRANDC $rhs, $lhs), $tval, $fval)>;
1132 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETUGT)),
11251133 (SELECT_QFRC (CRANDC $lhs, $rhs), $tval, $fval)>;
11261134 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETNE)),
11271135 (SELECT_QFRC (CRXOR $lhs, $rhs), $tval, $fval)>;
11281136
11291137 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETLT)),
1138 (SELECT_QSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
1139 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETULT)),
11301140 (SELECT_QSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
11311141 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETLE)),
1142 (SELECT_QSRC (CRORC $lhs, $rhs), $tval, $fval)>;
1143 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETULE)),
11321144 (SELECT_QSRC (CRORC $rhs, $lhs), $tval, $fval)>;
11331145 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETEQ)),
11341146 (SELECT_QSRC (CREQV $lhs, $rhs), $tval, $fval)>;
11351147 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETGE)),
1148 (SELECT_QSRC (CRORC $rhs, $lhs), $tval, $fval)>;
1149 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETUGE)),
11361150 (SELECT_QSRC (CRORC $lhs, $rhs), $tval, $fval)>;
11371151 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETGT)),
1152 (SELECT_QSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
1153 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETUGT)),
11381154 (SELECT_QSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
11391155 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETNE)),
11401156 (SELECT_QSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
11411157
11421158 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETLT)),
1159 (SELECT_QBRC (CRANDC $lhs, $rhs), $tval, $fval)>;
1160 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETULT)),
11431161 (SELECT_QBRC (CRANDC $rhs, $lhs), $tval, $fval)>;
11441162 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETLE)),
1163 (SELECT_QBRC (CRORC $lhs, $rhs), $tval, $fval)>;
1164 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETULE)),
11451165 (SELECT_QBRC (CRORC $rhs, $lhs), $tval, $fval)>;
11461166 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETEQ)),
11471167 (SELECT_QBRC (CREQV $lhs, $rhs), $tval, $fval)>;
11481168 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETGE)),
1169 (SELECT_QBRC (CRORC $rhs, $lhs), $tval, $fval)>;
1170 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETUGE)),
11491171 (SELECT_QBRC (CRORC $lhs, $rhs), $tval, $fval)>;
11501172 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETGT)),
1173 (SELECT_QBRC (CRANDC $rhs, $lhs), $tval, $fval)>;
1174 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETUGT)),
11511175 (SELECT_QBRC (CRANDC $lhs, $rhs), $tval, $fval)>;
11521176 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETNE)),
11531177 (SELECT_QBRC (CRXOR $lhs, $rhs), $tval, $fval)>;
957957
958958 // Selects.
959959 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)),
960 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
961 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULT)),
960962 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
961963 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLE)),
964 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>;
965 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULE)),
962966 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>;
963967 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETEQ)),
964968 (SELECT_VSRC (CREQV $lhs, $rhs), $tval, $fval)>;
965969 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)),
970 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>;
971 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGE)),
966972 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>;
967973 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGT)),
974 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
975 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGT)),
968976 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
969977 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)),
970978 (SELECT_VSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
971979
972980 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
981 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>;
982 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
973983 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>;
974984 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
985 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>;
986 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
975987 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>;
976988 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
977989 (SELECT_VSFRC (CREQV $lhs, $rhs), $tval, $fval)>;
978990 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
991 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>;
992 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
979993 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>;
980994 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
995 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>;
996 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
981997 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>;
982998 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
983999 (SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>;
10591075 (COPY_TO_REGCLASS (LXSSPX xoaddr:$src), VSFRC)>;
10601076 def : Pat<(f64 (fextend f32:$src)),
10611077 (COPY_TO_REGCLASS $src, VSFRC)>;
1078
10621079 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
1080 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
1081 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
10631082 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
10641083 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
1084 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>;
1085 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
10651086 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>;
10661087 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
10671088 (SELECT_VSSRC (CREQV $lhs, $rhs), $tval, $fval)>;
10681089 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
1090 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>;
1091 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
10691092 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>;
10701093 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
1094 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
1095 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
10711096 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
10721097 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
1073 (SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
1098 (SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
10741099
10751100 // VSX Elementary Scalar FP arithmetic (SP)
10761101 let isCommutable = 1 in {
0 ; RUN: llc < %s | FileCheck %s
1 target datalayout = "E-m:e-i64:64-n32:64"
2 target triple = "powerpc64-unknown-linux-gnu"
3
4 ; FIXME: We should check the operands to the cr* logical operation itself, but
5 ; unfortunately, FileCheck does not yet understand how to do arithmetic, so we
6 ; can't do so without introducing a register-allocation dependency.
7
8 define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
9 entry:
10 %cmp1 = icmp eq i32 %c3, %c4
11 %cmp3tmp = icmp eq i32 %c1, %c2
12 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
13 %cond = select i1 %cmp3, i32 %a1, i32 %a2
14 ret i32 %cond
15
16 ; CHECK-LABEL: @testi32slt
17 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
18 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
19 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
20 ; CHECK: isel 3, 7, 8, [[REG1]]
21 ; CHECK: blr
22 }
23
24 define signext i32 @testi32ult(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
25 entry:
26 %cmp1 = icmp eq i32 %c3, %c4
27 %cmp3tmp = icmp eq i32 %c1, %c2
28 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
29 %cond = select i1 %cmp3, i32 %a1, i32 %a2
30 ret i32 %cond
31
32 ; CHECK-LABEL: @testi32ult
33 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
34 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
35 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
36 ; CHECK: isel 3, 7, 8, [[REG1]]
37 ; CHECK: blr
38 }
39
40 define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
41 entry:
42 %cmp1 = icmp eq i32 %c3, %c4
43 %cmp3tmp = icmp eq i32 %c1, %c2
44 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
45 %cond = select i1 %cmp3, i32 %a1, i32 %a2
46 ret i32 %cond
47
48 ; CHECK-LABEL: @testi32sle
49 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
50 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
51 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
52 ; CHECK: isel 3, 7, 8, [[REG1]]
53 ; CHECK: blr
54 }
55
56 define signext i32 @testi32ule(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
57 entry:
58 %cmp1 = icmp eq i32 %c3, %c4
59 %cmp3tmp = icmp eq i32 %c1, %c2
60 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
61 %cond = select i1 %cmp3, i32 %a1, i32 %a2
62 ret i32 %cond
63
64 ; CHECK-LABEL: @testi32ule
65 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
66 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
67 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
68 ; CHECK: isel 3, 7, 8, [[REG1]]
69 ; CHECK: blr
70 }
71
72 define signext i32 @testi32eq(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
73 entry:
74 %cmp1 = icmp eq i32 %c3, %c4
75 %cmp3tmp = icmp eq i32 %c1, %c2
76 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
77 %cond = select i1 %cmp3, i32 %a1, i32 %a2
78 ret i32 %cond
79
80 ; CHECK-LABEL: @testi32eq
81 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
82 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
83 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
84 ; CHECK: isel 3, 7, 8, [[REG1]]
85 ; CHECK: blr
86 }
87
88 define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
89 entry:
90 %cmp1 = icmp eq i32 %c3, %c4
91 %cmp3tmp = icmp eq i32 %c1, %c2
92 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
93 %cond = select i1 %cmp3, i32 %a1, i32 %a2
94 ret i32 %cond
95
96 ; CHECK-LABEL: @testi32sge
97 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
98 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
99 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
100 ; CHECK: isel 3, 7, 8, [[REG1]]
101 ; CHECK: blr
102 }
103
104 define signext i32 @testi32uge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
105 entry:
106 %cmp1 = icmp eq i32 %c3, %c4
107 %cmp3tmp = icmp eq i32 %c1, %c2
108 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
109 %cond = select i1 %cmp3, i32 %a1, i32 %a2
110 ret i32 %cond
111
112 ; CHECK-LABEL: @testi32uge
113 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
114 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
115 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
116 ; CHECK: isel 3, 7, 8, [[REG1]]
117 ; CHECK: blr
118 }
119
120 define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
121 entry:
122 %cmp1 = icmp eq i32 %c3, %c4
123 %cmp3tmp = icmp eq i32 %c1, %c2
124 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
125 %cond = select i1 %cmp3, i32 %a1, i32 %a2
126 ret i32 %cond
127
128 ; CHECK-LABEL: @testi32sgt
129 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
130 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
131 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
132 ; CHECK: isel 3, 7, 8, [[REG1]]
133 ; CHECK: blr
134 }
135
136 define signext i32 @testi32ugt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
137 entry:
138 %cmp1 = icmp eq i32 %c3, %c4
139 %cmp3tmp = icmp eq i32 %c1, %c2
140 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
141 %cond = select i1 %cmp3, i32 %a1, i32 %a2
142 ret i32 %cond
143
144 ; CHECK-LABEL: @testi32ugt
145 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
146 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
147 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
148 ; CHECK: isel 3, 7, 8, [[REG1]]
149 ; CHECK: blr
150 }
151
152 define signext i32 @testi32ne(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
153 entry:
154 %cmp1 = icmp eq i32 %c3, %c4
155 %cmp3tmp = icmp eq i32 %c1, %c2
156 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
157 %cond = select i1 %cmp3, i32 %a1, i32 %a2
158 ret i32 %cond
159
160 ; CHECK-LABEL: @testi32ne
161 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
162 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
163 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
164 ; CHECK: isel 3, 7, 8, [[REG1]]
165 ; CHECK: blr
166 }
167
168 define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
169 entry:
170 %cmp1 = icmp eq i64 %c3, %c4
171 %cmp3tmp = icmp eq i64 %c1, %c2
172 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
173 %cond = select i1 %cmp3, i64 %a1, i64 %a2
174 ret i64 %cond
175
176 ; CHECK-LABEL: @testi64slt
177 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
178 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
179 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
180 ; CHECK: isel 3, 7, 8, [[REG1]]
181 ; CHECK: blr
182 }
183
184 define i64 @testi64ult(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
185 entry:
186 %cmp1 = icmp eq i64 %c3, %c4
187 %cmp3tmp = icmp eq i64 %c1, %c2
188 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
189 %cond = select i1 %cmp3, i64 %a1, i64 %a2
190 ret i64 %cond
191
192 ; CHECK-LABEL: @testi64ult
193 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
194 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
195 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
196 ; CHECK: isel 3, 7, 8, [[REG1]]
197 ; CHECK: blr
198 }
199
200 define i64 @testi64sle(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
201 entry:
202 %cmp1 = icmp eq i64 %c3, %c4
203 %cmp3tmp = icmp eq i64 %c1, %c2
204 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
205 %cond = select i1 %cmp3, i64 %a1, i64 %a2
206 ret i64 %cond
207
208 ; CHECK-LABEL: @testi64sle
209 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
210 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
211 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
212 ; CHECK: isel 3, 7, 8, [[REG1]]
213 ; CHECK: blr
214 }
215
216 define i64 @testi64ule(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
217 entry:
218 %cmp1 = icmp eq i64 %c3, %c4
219 %cmp3tmp = icmp eq i64 %c1, %c2
220 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
221 %cond = select i1 %cmp3, i64 %a1, i64 %a2
222 ret i64 %cond
223
224 ; CHECK-LABEL: @testi64ule
225 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
226 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
227 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
228 ; CHECK: isel 3, 7, 8, [[REG1]]
229 ; CHECK: blr
230 }
231
232 define i64 @testi64eq(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
233 entry:
234 %cmp1 = icmp eq i64 %c3, %c4
235 %cmp3tmp = icmp eq i64 %c1, %c2
236 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
237 %cond = select i1 %cmp3, i64 %a1, i64 %a2
238 ret i64 %cond
239
240 ; CHECK-LABEL: @testi64eq
241 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
242 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
243 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
244 ; CHECK: isel 3, 7, 8, [[REG1]]
245 ; CHECK: blr
246 }
247
248 define i64 @testi64sge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
249 entry:
250 %cmp1 = icmp eq i64 %c3, %c4
251 %cmp3tmp = icmp eq i64 %c1, %c2
252 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
253 %cond = select i1 %cmp3, i64 %a1, i64 %a2
254 ret i64 %cond
255
256 ; CHECK-LABEL: @testi64sge
257 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
258 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
259 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
260 ; CHECK: isel 3, 7, 8, [[REG1]]
261 ; CHECK: blr
262 }
263
264 define i64 @testi64uge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
265 entry:
266 %cmp1 = icmp eq i64 %c3, %c4
267 %cmp3tmp = icmp eq i64 %c1, %c2
268 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
269 %cond = select i1 %cmp3, i64 %a1, i64 %a2
270 ret i64 %cond
271
272 ; CHECK-LABEL: @testi64uge
273 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
274 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
275 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
276 ; CHECK: isel 3, 7, 8, [[REG1]]
277 ; CHECK: blr
278 }
279
280 define i64 @testi64sgt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
281 entry:
282 %cmp1 = icmp eq i64 %c3, %c4
283 %cmp3tmp = icmp eq i64 %c1, %c2
284 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
285 %cond = select i1 %cmp3, i64 %a1, i64 %a2
286 ret i64 %cond
287
288 ; CHECK-LABEL: @testi64sgt
289 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
290 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
291 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
292 ; CHECK: isel 3, 7, 8, [[REG1]]
293 ; CHECK: blr
294 }
295
296 define i64 @testi64ugt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
297 entry:
298 %cmp1 = icmp eq i64 %c3, %c4
299 %cmp3tmp = icmp eq i64 %c1, %c2
300 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
301 %cond = select i1 %cmp3, i64 %a1, i64 %a2
302 ret i64 %cond
303
304 ; CHECK-LABEL: @testi64ugt
305 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
306 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
307 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
308 ; CHECK: isel 3, 7, 8, [[REG1]]
309 ; CHECK: blr
310 }
311
312 define i64 @testi64ne(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
313 entry:
314 %cmp1 = icmp eq i64 %c3, %c4
315 %cmp3tmp = icmp eq i64 %c1, %c2
316 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
317 %cond = select i1 %cmp3, i64 %a1, i64 %a2
318 ret i64 %cond
319
320 ; CHECK-LABEL: @testi64ne
321 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
322 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
323 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
324 ; CHECK: isel 3, 7, 8, [[REG1]]
325 ; CHECK: blr
326 }
327
328 define float @testfloatslt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
329 entry:
330 %cmp1 = fcmp oeq float %c3, %c4
331 %cmp3tmp = fcmp oeq float %c1, %c2
332 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
333 %cond = select i1 %cmp3, float %a1, float %a2
334 ret float %cond
335
336 ; CHECK-LABEL: @testfloatslt
337 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
338 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
339 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
340 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
341 ; CHECK: fmr 5, 6
342 ; CHECK: .LBB[[BB]]:
343 ; CHECK: fmr 1, 5
344 ; CHECK: blr
345 }
346
347 define float @testfloatult(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
348 entry:
349 %cmp1 = fcmp oeq float %c3, %c4
350 %cmp3tmp = fcmp oeq float %c1, %c2
351 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
352 %cond = select i1 %cmp3, float %a1, float %a2
353 ret float %cond
354
355 ; CHECK-LABEL: @testfloatult
356 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
357 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
358 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
359 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
360 ; CHECK: fmr 5, 6
361 ; CHECK: .LBB[[BB]]:
362 ; CHECK: fmr 1, 5
363 ; CHECK: blr
364 }
365
366 define float @testfloatsle(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
367 entry:
368 %cmp1 = fcmp oeq float %c3, %c4
369 %cmp3tmp = fcmp oeq float %c1, %c2
370 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
371 %cond = select i1 %cmp3, float %a1, float %a2
372 ret float %cond
373
374 ; CHECK-LABEL: @testfloatsle
375 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
376 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
377 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
378 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
379 ; CHECK: fmr 5, 6
380 ; CHECK: .LBB[[BB]]:
381 ; CHECK: fmr 1, 5
382 ; CHECK: blr
383 }
384
385 define float @testfloatule(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
386 entry:
387 %cmp1 = fcmp oeq float %c3, %c4
388 %cmp3tmp = fcmp oeq float %c1, %c2
389 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
390 %cond = select i1 %cmp3, float %a1, float %a2
391 ret float %cond
392
393 ; CHECK-LABEL: @testfloatule
394 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
395 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
396 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
397 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
398 ; CHECK: fmr 5, 6
399 ; CHECK: .LBB[[BB]]:
400 ; CHECK: fmr 1, 5
401 ; CHECK: blr
402 }
403
404 define float @testfloateq(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
405 entry:
406 %cmp1 = fcmp oeq float %c3, %c4
407 %cmp3tmp = fcmp oeq float %c1, %c2
408 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
409 %cond = select i1 %cmp3, float %a1, float %a2
410 ret float %cond
411
412 ; CHECK-LABEL: @testfloateq
413 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
414 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
415 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
416 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
417 ; CHECK: fmr 5, 6
418 ; CHECK: .LBB[[BB]]:
419 ; CHECK: fmr 1, 5
420 ; CHECK: blr
421 }
422
423 define float @testfloatsge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
424 entry:
425 %cmp1 = fcmp oeq float %c3, %c4
426 %cmp3tmp = fcmp oeq float %c1, %c2
427 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
428 %cond = select i1 %cmp3, float %a1, float %a2
429 ret float %cond
430
431 ; CHECK-LABEL: @testfloatsge
432 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
433 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
434 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
435 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
436 ; CHECK: fmr 5, 6
437 ; CHECK: .LBB[[BB]]:
438 ; CHECK: fmr 1, 5
439 ; CHECK: blr
440 }
441
442 define float @testfloatuge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
443 entry:
444 %cmp1 = fcmp oeq float %c3, %c4
445 %cmp3tmp = fcmp oeq float %c1, %c2
446 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
447 %cond = select i1 %cmp3, float %a1, float %a2
448 ret float %cond
449
450 ; CHECK-LABEL: @testfloatuge
451 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
452 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
453 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
454 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
455 ; CHECK: fmr 5, 6
456 ; CHECK: .LBB[[BB]]:
457 ; CHECK: fmr 1, 5
458 ; CHECK: blr
459 }
460
461 define float @testfloatsgt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
462 entry:
463 %cmp1 = fcmp oeq float %c3, %c4
464 %cmp3tmp = fcmp oeq float %c1, %c2
465 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
466 %cond = select i1 %cmp3, float %a1, float %a2
467 ret float %cond
468
469 ; CHECK-LABEL: @testfloatsgt
470 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
471 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
472 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
473 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
474 ; CHECK: fmr 5, 6
475 ; CHECK: .LBB[[BB]]:
476 ; CHECK: fmr 1, 5
477 ; CHECK: blr
478 }
479
480 define float @testfloatugt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
481 entry:
482 %cmp1 = fcmp oeq float %c3, %c4
483 %cmp3tmp = fcmp oeq float %c1, %c2
484 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
485 %cond = select i1 %cmp3, float %a1, float %a2
486 ret float %cond
487
488 ; CHECK-LABEL: @testfloatugt
489 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
490 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
491 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
492 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
493 ; CHECK: fmr 5, 6
494 ; CHECK: .LBB[[BB]]:
495 ; CHECK: fmr 1, 5
496 ; CHECK: blr
497 }
498
499 define float @testfloatne(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
500 entry:
501 %cmp1 = fcmp oeq float %c3, %c4
502 %cmp3tmp = fcmp oeq float %c1, %c2
503 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
504 %cond = select i1 %cmp3, float %a1, float %a2
505 ret float %cond
506
507 ; CHECK-LABEL: @testfloatne
508 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
509 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
510 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
511 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
512 ; CHECK: fmr 5, 6
513 ; CHECK: .LBB[[BB]]:
514 ; CHECK: fmr 1, 5
515 ; CHECK: blr
516 }
517
518 define double @testdoubleslt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
519 entry:
520 %cmp1 = fcmp oeq double %c3, %c4
521 %cmp3tmp = fcmp oeq double %c1, %c2
522 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
523 %cond = select i1 %cmp3, double %a1, double %a2
524 ret double %cond
525
526 ; CHECK-LABEL: @testdoubleslt
527 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
528 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
529 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
530 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
531 ; CHECK: fmr 5, 6
532 ; CHECK: .LBB[[BB]]:
533 ; CHECK: fmr 1, 5
534 ; CHECK: blr
535 }
536
537 define double @testdoubleult(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
538 entry:
539 %cmp1 = fcmp oeq double %c3, %c4
540 %cmp3tmp = fcmp oeq double %c1, %c2
541 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
542 %cond = select i1 %cmp3, double %a1, double %a2
543 ret double %cond
544
545 ; CHECK-LABEL: @testdoubleult
546 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
547 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
548 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
549 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
550 ; CHECK: fmr 5, 6
551 ; CHECK: .LBB[[BB]]:
552 ; CHECK: fmr 1, 5
553 ; CHECK: blr
554 }
555
556 define double @testdoublesle(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
557 entry:
558 %cmp1 = fcmp oeq double %c3, %c4
559 %cmp3tmp = fcmp oeq double %c1, %c2
560 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
561 %cond = select i1 %cmp3, double %a1, double %a2
562 ret double %cond
563
564 ; CHECK-LABEL: @testdoublesle
565 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
566 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
567 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
568 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
569 ; CHECK: fmr 5, 6
570 ; CHECK: .LBB[[BB]]:
571 ; CHECK: fmr 1, 5
572 ; CHECK: blr
573 }
574
575 define double @testdoubleule(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
576 entry:
577 %cmp1 = fcmp oeq double %c3, %c4
578 %cmp3tmp = fcmp oeq double %c1, %c2
579 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
580 %cond = select i1 %cmp3, double %a1, double %a2
581 ret double %cond
582
583 ; CHECK-LABEL: @testdoubleule
584 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
585 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
586 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
587 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
588 ; CHECK: fmr 5, 6
589 ; CHECK: .LBB[[BB]]:
590 ; CHECK: fmr 1, 5
591 ; CHECK: blr
592 }
593
594 define double @testdoubleeq(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
595 entry:
596 %cmp1 = fcmp oeq double %c3, %c4
597 %cmp3tmp = fcmp oeq double %c1, %c2
598 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
599 %cond = select i1 %cmp3, double %a1, double %a2
600 ret double %cond
601
602 ; CHECK-LABEL: @testdoubleeq
603 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
604 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
605 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
606 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
607 ; CHECK: fmr 5, 6
608 ; CHECK: .LBB[[BB]]:
609 ; CHECK: fmr 1, 5
610 ; CHECK: blr
611 }
612
613 define double @testdoublesge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
614 entry:
615 %cmp1 = fcmp oeq double %c3, %c4
616 %cmp3tmp = fcmp oeq double %c1, %c2
617 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
618 %cond = select i1 %cmp3, double %a1, double %a2
619 ret double %cond
620
621 ; CHECK-LABEL: @testdoublesge
622 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
623 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
624 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
625 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
626 ; CHECK: fmr 5, 6
627 ; CHECK: .LBB[[BB]]:
628 ; CHECK: fmr 1, 5
629 ; CHECK: blr
630 }
631
632 define double @testdoubleuge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
633 entry:
634 %cmp1 = fcmp oeq double %c3, %c4
635 %cmp3tmp = fcmp oeq double %c1, %c2
636 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
637 %cond = select i1 %cmp3, double %a1, double %a2
638 ret double %cond
639
640 ; CHECK-LABEL: @testdoubleuge
641 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
642 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
643 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
644 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
645 ; CHECK: fmr 5, 6
646 ; CHECK: .LBB[[BB]]:
647 ; CHECK: fmr 1, 5
648 ; CHECK: blr
649 }
650
651 define double @testdoublesgt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
652 entry:
653 %cmp1 = fcmp oeq double %c3, %c4
654 %cmp3tmp = fcmp oeq double %c1, %c2
655 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
656 %cond = select i1 %cmp3, double %a1, double %a2
657 ret double %cond
658
659 ; CHECK-LABEL: @testdoublesgt
660 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
661 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
662 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
663 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
664 ; CHECK: fmr 5, 6
665 ; CHECK: .LBB[[BB]]:
666 ; CHECK: fmr 1, 5
667 ; CHECK: blr
668 }
669
670 define double @testdoubleugt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
671 entry:
672 %cmp1 = fcmp oeq double %c3, %c4
673 %cmp3tmp = fcmp oeq double %c1, %c2
674 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
675 %cond = select i1 %cmp3, double %a1, double %a2
676 ret double %cond
677
678 ; CHECK-LABEL: @testdoubleugt
679 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
680 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
681 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
682 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
683 ; CHECK: fmr 5, 6
684 ; CHECK: .LBB[[BB]]:
685 ; CHECK: fmr 1, 5
686 ; CHECK: blr
687 }
688
689 define double @testdoublene(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
690 entry:
691 %cmp1 = fcmp oeq double %c3, %c4
692 %cmp3tmp = fcmp oeq double %c1, %c2
693 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
694 %cond = select i1 %cmp3, double %a1, double %a2
695 ret double %cond
696
697 ; CHECK-LABEL: @testdoublene
698 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
699 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
700 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
701 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
702 ; CHECK: fmr 5, 6
703 ; CHECK: .LBB[[BB]]:
704 ; CHECK: fmr 1, 5
705 ; CHECK: blr
706 }
707
708 define <4 x float> @testv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
709 entry:
710 %cmp1 = fcmp oeq float %c3, %c4
711 %cmp3tmp = fcmp oeq float %c1, %c2
712 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
713 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
714 ret <4 x float> %cond
715
716 ; FIXME: This test (and the other v4f32 tests) should use the same bclr
717 ; technique as the v2f64 tests below.
718
719 ; CHECK-LABEL: @testv4floatslt
720 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
721 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
722 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
723 ; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
724 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
725 ; CHECK: xxlor [[REG2]], 35, 35
726 ; CHECK: .LBB[[BB]]:
727 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
728 ; CHECK: blr
729 }
730
731 define <4 x float> @testv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
732 entry:
733 %cmp1 = fcmp oeq float %c3, %c4
734 %cmp3tmp = fcmp oeq float %c1, %c2
735 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
736 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
737 ret <4 x float> %cond
738
739 ; CHECK-LABEL: @testv4floatult
740 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
741 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
742 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
743 ; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
744 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
745 ; CHECK: xxlor [[REG2]], 35, 35
746 ; CHECK: .LBB[[BB]]:
747 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
748 ; CHECK: blr
749 }
750
751 define <4 x float> @testv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
752 entry:
753 %cmp1 = fcmp oeq float %c3, %c4
754 %cmp3tmp = fcmp oeq float %c1, %c2
755 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
756 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
757 ret <4 x float> %cond
758
759 ; CHECK-LABEL: @testv4floatsle
760 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
761 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
762 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
763 ; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
764 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
765 ; CHECK: xxlor [[REG2]], 35, 35
766 ; CHECK: .LBB[[BB]]:
767 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
768 ; CHECK: blr
769 }
770
771 define <4 x float> @testv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
772 entry:
773 %cmp1 = fcmp oeq float %c3, %c4
774 %cmp3tmp = fcmp oeq float %c1, %c2
775 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
776 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
777 ret <4 x float> %cond
778
779 ; CHECK-LABEL: @testv4floatule
780 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
781 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
782 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
783 ; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
784 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
785 ; CHECK: xxlor [[REG2]], 35, 35
786 ; CHECK: .LBB[[BB]]:
787 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
788 ; CHECK: blr
789 }
790
791 define <4 x float> @testv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
792 entry:
793 %cmp1 = fcmp oeq float %c3, %c4
794 %cmp3tmp = fcmp oeq float %c1, %c2
795 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
796 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
797 ret <4 x float> %cond
798
799 ; CHECK-LABEL: @testv4floateq
800 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
801 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
802 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
803 ; CHECK-DAG: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
804 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
805 ; CHECK: xxlor [[REG2]], 35, 35
806 ; CHECK: .LBB[[BB]]:
807 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
808 ; CHECK: blr
809 }
810
811 define <4 x float> @testv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
812 entry:
813 %cmp1 = fcmp oeq float %c3, %c4
814 %cmp3tmp = fcmp oeq float %c1, %c2
815 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
816 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
817 ret <4 x float> %cond
818
819 ; CHECK-LABEL: @testv4floatsge
820 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
821 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
822 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
823 ; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
824 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
825 ; CHECK: xxlor [[REG2]], 35, 35
826 ; CHECK: .LBB[[BB]]:
827 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
828 ; CHECK: blr
829 }
830
831 define <4 x float> @testv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
832 entry:
833 %cmp1 = fcmp oeq float %c3, %c4
834 %cmp3tmp = fcmp oeq float %c1, %c2
835 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
836 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
837 ret <4 x float> %cond
838
839 ; CHECK-LABEL: @testv4floatuge
840 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
841 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
842 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
843 ; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
844 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
845 ; CHECK: xxlor [[REG2]], 35, 35
846 ; CHECK: .LBB[[BB]]:
847 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
848 ; CHECK: blr
849 }
850
851 define <4 x float> @testv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
852 entry:
853 %cmp1 = fcmp oeq float %c3, %c4
854 %cmp3tmp = fcmp oeq float %c1, %c2
855 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
856 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
857 ret <4 x float> %cond
858
859 ; CHECK-LABEL: @testv4floatsgt
860 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
861 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
862 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
863 ; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
864 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
865 ; CHECK: xxlor [[REG2]], 35, 35
866 ; CHECK: .LBB[[BB]]:
867 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
868 ; CHECK: blr
869 }
870
871 define <4 x float> @testv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
872 entry:
873 %cmp1 = fcmp oeq float %c3, %c4
874 %cmp3tmp = fcmp oeq float %c1, %c2
875 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
876 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
877 ret <4 x float> %cond
878
879 ; CHECK-LABEL: @testv4floatugt
880 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
881 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
882 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
883 ; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
884 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
885 ; CHECK: xxlor [[REG2]], 35, 35
886 ; CHECK: .LBB[[BB]]:
887 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
888 ; CHECK: blr
889 }
890
891 define <4 x float> @testv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
892 entry:
893 %cmp1 = fcmp oeq float %c3, %c4
894 %cmp3tmp = fcmp oeq float %c1, %c2
895 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
896 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
897 ret <4 x float> %cond
898
899 ; CHECK-LABEL: @testv4floatne
900 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
901 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
902 ; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
903 ; CHECK-DAG: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
904 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
905 ; CHECK: xxlor [[REG2]], 35, 35
906 ; CHECK: .LBB[[BB]]:
907 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
908 ; CHECK: blr
909 }
910
911 define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, ppc_fp128 %c4, ppc_fp128 %a1, ppc_fp128 %a2) #0 {
912 entry:
913 %cmp1 = fcmp oeq ppc_fp128 %c3, %c4
914 %cmp3tmp = fcmp oeq ppc_fp128 %c1, %c2
915 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
916 %cond = select i1 %cmp3, ppc_fp128 %a1, ppc_fp128 %a2
917 ret ppc_fp128 %cond
918
919 ; FIXME: Because of the way that the late SELECT_* pseudo-instruction expansion
920 ; works, we end up with two blocks with the same predicate. These could be
921 ; combined.
922
923 ; CHECK-LABEL: @testppc_fp128eq
924 ; CHECK-DAG: fcmpu {{[0-9]+}}, 6, 8
925 ; CHECK-DAG: fcmpu {{[0-9]+}}, 5, 7
926 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, 4
927 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 3
928 ; CHECK: crand [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
929 ; CHECK: crand [[REG2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
930 ; CHECK: creqv [[REG3:[0-9]+]], [[REG2]], [[REG1]]
931 ; CHECK: bc 12, [[REG3]], .LBB[[BB1:[0-9_]+]]
932 ; CHECK: fmr 9, 11
933 ; CHECK: .LBB[[BB1]]:
934 ; CHECK: bc 12, [[REG3]], .LBB[[BB2:[0-9_]+]]
935 ; CHECK: fmr 10, 12
936 ; CHECK: .LBB[[BB2]]:
937 ; CHECK-DAG: fmr 1, 9
938 ; CHECK-DAG: fmr 2, 10
939 ; CHECK: blr
940 }
941
942 define <2 x double> @testv2doubleslt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
943 entry:
944 %cmp1 = fcmp oeq float %c3, %c4
945 %cmp3tmp = fcmp oeq float %c1, %c2
946 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
947 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
948 ret <2 x double> %cond
949
950 ; CHECK-LABEL: @testv2doubleslt
951 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
952 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
953 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
954 ; CHECK: bclr 12, [[REG1]], 0
955 ; CHECK: vor 2, 3, 3
956 ; CHECK: blr
957 }
958
959 define <2 x double> @testv2doubleult(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
960 entry:
961 %cmp1 = fcmp oeq float %c3, %c4
962 %cmp3tmp = fcmp oeq float %c1, %c2
963 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
964 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
965 ret <2 x double> %cond
966
967 ; CHECK-LABEL: @testv2doubleult
968 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
969 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
970 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
971 ; CHECK: bclr 12, [[REG1]], 0
972 ; CHECK: vor 2, 3, 3
973 ; CHECK: blr
974 }
975
976 define <2 x double> @testv2doublesle(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
977 entry:
978 %cmp1 = fcmp oeq float %c3, %c4
979 %cmp3tmp = fcmp oeq float %c1, %c2
980 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
981 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
982 ret <2 x double> %cond
983
984 ; CHECK-LABEL: @testv2doublesle
985 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
986 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
987 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
988 ; CHECK: bclr 12, [[REG1]], 0
989 ; CHECK: vor 2, 3, 3
990 ; CHECK: blr
991 }
992
993 define <2 x double> @testv2doubleule(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
994 entry:
995 %cmp1 = fcmp oeq float %c3, %c4
996 %cmp3tmp = fcmp oeq float %c1, %c2
997 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
998 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
999 ret <2 x double> %cond
1000
1001 ; CHECK-LABEL: @testv2doubleule
1002 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1003 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1004 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1005 ; CHECK: bclr 12, [[REG1]], 0
1006 ; CHECK: vor 2, 3, 3
1007 ; CHECK: blr
1008 }
1009
1010 define <2 x double> @testv2doubleeq(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1011 entry:
1012 %cmp1 = fcmp oeq float %c3, %c4
1013 %cmp3tmp = fcmp oeq float %c1, %c2
1014 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
1015 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1016 ret <2 x double> %cond
1017
1018 ; CHECK-LABEL: @testv2doubleeq
1019 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1020 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1021 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1022 ; CHECK: bclr 12, [[REG1]], 0
1023 ; CHECK: vor 2, 3, 3
1024 ; CHECK: blr
1025 }
1026
1027 define <2 x double> @testv2doublesge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1028 entry:
1029 %cmp1 = fcmp oeq float %c3, %c4
1030 %cmp3tmp = fcmp oeq float %c1, %c2
1031 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
1032 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1033 ret <2 x double> %cond
1034
1035 ; CHECK-LABEL: @testv2doublesge
1036 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1037 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1038 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1039 ; CHECK: bclr 12, [[REG1]], 0
1040 ; CHECK: vor 2, 3, 3
1041 ; CHECK: blr
1042 }
1043
1044 define <2 x double> @testv2doubleuge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1045 entry:
1046 %cmp1 = fcmp oeq float %c3, %c4
1047 %cmp3tmp = fcmp oeq float %c1, %c2
1048 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
1049 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1050 ret <2 x double> %cond
1051
1052 ; CHECK-LABEL: @testv2doubleuge
1053 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1054 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1055 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1056 ; CHECK: bclr 12, [[REG1]], 0
1057 ; CHECK: vor 2, 3, 3
1058 ; CHECK: blr
1059 }
1060
1061 define <2 x double> @testv2doublesgt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1062 entry:
1063 %cmp1 = fcmp oeq float %c3, %c4
1064 %cmp3tmp = fcmp oeq float %c1, %c2
1065 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
1066 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1067 ret <2 x double> %cond
1068
1069 ; CHECK-LABEL: @testv2doublesgt
1070 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1071 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1072 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1073 ; CHECK: bclr 12, [[REG1]], 0
1074 ; CHECK: vor 2, 3, 3
1075 ; CHECK: blr
1076 }
1077
1078 define <2 x double> @testv2doubleugt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1079 entry:
1080 %cmp1 = fcmp oeq float %c3, %c4
1081 %cmp3tmp = fcmp oeq float %c1, %c2
1082 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
1083 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1084 ret <2 x double> %cond
1085
1086 ; CHECK-LABEL: @testv2doubleugt
1087 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1088 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1089 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1090 ; CHECK: bclr 12, [[REG1]], 0
1091 ; CHECK: vor 2, 3, 3
1092 ; CHECK: blr
1093 }
1094
1095 define <2 x double> @testv2doublene(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1096 entry:
1097 %cmp1 = fcmp oeq float %c3, %c4
1098 %cmp3tmp = fcmp oeq float %c1, %c2
1099 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
1100 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1101 ret <2 x double> %cond
1102
1103 ; CHECK-LABEL: @testv2doublene
1104 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1105 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1106 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1107 ; CHECK: bclr 12, [[REG1]], 0
1108 ; CHECK: vor 2, 3, 3
1109 ; CHECK: blr
1110 }
1111
1112 define <4 x double> @testqv4doubleslt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1113 entry:
1114 %cmp1 = fcmp oeq float %c3, %c4
1115 %cmp3tmp = fcmp oeq float %c1, %c2
1116 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
1117 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1118 ret <4 x double> %cond
1119
1120 ; CHECK-LABEL: @testqv4doubleslt
1121 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1122 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1123 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1124 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1125 ; CHECK: qvfmr 5, 6
1126 ; CHECK: .LBB[[BB]]:
1127 ; CHECK: qvfmr 1, 5
1128 ; CHECK: blr
1129 }
1130
1131 define <4 x double> @testqv4doubleult(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1132 entry:
1133 %cmp1 = fcmp oeq float %c3, %c4
1134 %cmp3tmp = fcmp oeq float %c1, %c2
1135 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
1136 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1137 ret <4 x double> %cond
1138
1139 ; CHECK-LABEL: @testqv4doubleult
1140 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1141 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1142 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1143 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1144 ; CHECK: qvfmr 5, 6
1145 ; CHECK: .LBB[[BB]]:
1146 ; CHECK: qvfmr 1, 5
1147 ; CHECK: blr
1148 }
1149
1150 define <4 x double> @testqv4doublesle(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1151 entry:
1152 %cmp1 = fcmp oeq float %c3, %c4
1153 %cmp3tmp = fcmp oeq float %c1, %c2
1154 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
1155 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1156 ret <4 x double> %cond
1157
1158 ; CHECK-LABEL: @testqv4doublesle
1159 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1160 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1161 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1162 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1163 ; CHECK: qvfmr 5, 6
1164 ; CHECK: .LBB[[BB]]:
1165 ; CHECK: qvfmr 1, 5
1166 ; CHECK: blr
1167 }
1168
1169 define <4 x double> @testqv4doubleule(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1170 entry:
1171 %cmp1 = fcmp oeq float %c3, %c4
1172 %cmp3tmp = fcmp oeq float %c1, %c2
1173 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
1174 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1175 ret <4 x double> %cond
1176
1177 ; CHECK-LABEL: @testqv4doubleule
1178 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1179 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1180 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1181 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1182 ; CHECK: qvfmr 5, 6
1183 ; CHECK: .LBB[[BB]]:
1184 ; CHECK: qvfmr 1, 5
1185 ; CHECK: blr
1186 }
1187
1188 define <4 x double> @testqv4doubleeq(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1189 entry:
1190 %cmp1 = fcmp oeq float %c3, %c4
1191 %cmp3tmp = fcmp oeq float %c1, %c2
1192 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
1193 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1194 ret <4 x double> %cond
1195
1196 ; CHECK-LABEL: @testqv4doubleeq
1197 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1198 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1199 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1200 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1201 ; CHECK: qvfmr 5, 6
1202 ; CHECK: .LBB[[BB]]:
1203 ; CHECK: qvfmr 1, 5
1204 ; CHECK: blr
1205 }
1206
1207 define <4 x double> @testqv4doublesge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1208 entry:
1209 %cmp1 = fcmp oeq float %c3, %c4
1210 %cmp3tmp = fcmp oeq float %c1, %c2
1211 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
1212 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1213 ret <4 x double> %cond
1214
1215 ; CHECK-LABEL: @testqv4doublesge
1216 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1217 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1218 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1219 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1220 ; CHECK: qvfmr 5, 6
1221 ; CHECK: .LBB[[BB]]:
1222 ; CHECK: qvfmr 1, 5
1223 ; CHECK: blr
1224 }
1225
1226 define <4 x double> @testqv4doubleuge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1227 entry:
1228 %cmp1 = fcmp oeq float %c3, %c4
1229 %cmp3tmp = fcmp oeq float %c1, %c2
1230 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
1231 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1232 ret <4 x double> %cond
1233
1234 ; CHECK-LABEL: @testqv4doubleuge
1235 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1236 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1237 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1238 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1239 ; CHECK: qvfmr 5, 6
1240 ; CHECK: .LBB[[BB]]:
1241 ; CHECK: qvfmr 1, 5
1242 ; CHECK: blr
1243 }
1244
1245 define <4 x double> @testqv4doublesgt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1246 entry:
1247 %cmp1 = fcmp oeq float %c3, %c4
1248 %cmp3tmp = fcmp oeq float %c1, %c2
1249 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
1250 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1251 ret <4 x double> %cond
1252
1253 ; CHECK-LABEL: @testqv4doublesgt
1254 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1255 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1256 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1257 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1258 ; CHECK: qvfmr 5, 6
1259 ; CHECK: .LBB[[BB]]:
1260 ; CHECK: qvfmr 1, 5
1261 ; CHECK: blr
1262 }
1263
1264 define <4 x double> @testqv4doubleugt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1265 entry:
1266 %cmp1 = fcmp oeq float %c3, %c4
1267 %cmp3tmp = fcmp oeq float %c1, %c2
1268 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
1269 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1270 ret <4 x double> %cond
1271
1272 ; CHECK-LABEL: @testqv4doubleugt
1273 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1274 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1275 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1276 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1277 ; CHECK: qvfmr 5, 6
1278 ; CHECK: .LBB[[BB]]:
1279 ; CHECK: qvfmr 1, 5
1280 ; CHECK: blr
1281 }
1282
1283 define <4 x double> @testqv4doublene(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1284 entry:
1285 %cmp1 = fcmp oeq float %c3, %c4
1286 %cmp3tmp = fcmp oeq float %c1, %c2
1287 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
1288 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1289 ret <4 x double> %cond
1290
1291 ; CHECK-LABEL: @testqv4doublene
1292 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1293 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1294 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1295 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1296 ; CHECK: qvfmr 5, 6
1297 ; CHECK: .LBB[[BB]]:
1298 ; CHECK: qvfmr 1, 5
1299 ; CHECK: blr
1300 }
1301
1302 define <4 x float> @testqv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1303 entry:
1304 %cmp1 = fcmp oeq float %c3, %c4
1305 %cmp3tmp = fcmp oeq float %c1, %c2
1306 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
1307 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1308 ret <4 x float> %cond
1309
1310 ; CHECK-LABEL: @testqv4floatslt
1311 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1312 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1313 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1314 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1315 ; CHECK: qvfmr 5, 6
1316 ; CHECK: .LBB[[BB]]:
1317 ; CHECK: qvfmr 1, 5
1318 ; CHECK: blr
1319 }
1320
1321 define <4 x float> @testqv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1322 entry:
1323 %cmp1 = fcmp oeq float %c3, %c4
1324 %cmp3tmp = fcmp oeq float %c1, %c2
1325 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
1326 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1327 ret <4 x float> %cond
1328
1329 ; CHECK-LABEL: @testqv4floatult
1330 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1331 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1332 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1333 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1334 ; CHECK: qvfmr 5, 6
1335 ; CHECK: .LBB[[BB]]:
1336 ; CHECK: qvfmr 1, 5
1337 ; CHECK: blr
1338 }
1339
1340 define <4 x float> @testqv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1341 entry:
1342 %cmp1 = fcmp oeq float %c3, %c4
1343 %cmp3tmp = fcmp oeq float %c1, %c2
1344 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
1345 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1346 ret <4 x float> %cond
1347
1348 ; CHECK-LABEL: @testqv4floatsle
1349 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1350 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1351 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1352 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1353 ; CHECK: qvfmr 5, 6
1354 ; CHECK: .LBB[[BB]]:
1355 ; CHECK: qvfmr 1, 5
1356 ; CHECK: blr
1357 }
1358
1359 define <4 x float> @testqv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1360 entry:
1361 %cmp1 = fcmp oeq float %c3, %c4
1362 %cmp3tmp = fcmp oeq float %c1, %c2
1363 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
1364 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1365 ret <4 x float> %cond
1366
1367 ; CHECK-LABEL: @testqv4floatule
1368 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1369 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1370 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1371 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1372 ; CHECK: qvfmr 5, 6
1373 ; CHECK: .LBB[[BB]]:
1374 ; CHECK: qvfmr 1, 5
1375 ; CHECK: blr
1376 }
1377
1378 define <4 x float> @testqv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1379 entry:
1380 %cmp1 = fcmp oeq float %c3, %c4
1381 %cmp3tmp = fcmp oeq float %c1, %c2
1382 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
1383 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1384 ret <4 x float> %cond
1385
1386 ; CHECK-LABEL: @testqv4floateq
1387 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1388 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1389 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1390 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1391 ; CHECK: qvfmr 5, 6
1392 ; CHECK: .LBB[[BB]]:
1393 ; CHECK: qvfmr 1, 5
1394 ; CHECK: blr
1395 }
1396
1397 define <4 x float> @testqv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1398 entry:
1399 %cmp1 = fcmp oeq float %c3, %c4
1400 %cmp3tmp = fcmp oeq float %c1, %c2
1401 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
1402 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1403 ret <4 x float> %cond
1404
1405 ; CHECK-LABEL: @testqv4floatsge
1406 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1407 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1408 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1409 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1410 ; CHECK: qvfmr 5, 6
1411 ; CHECK: .LBB[[BB]]:
1412 ; CHECK: qvfmr 1, 5
1413 ; CHECK: blr
1414 }
1415
1416 define <4 x float> @testqv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1417 entry:
1418 %cmp1 = fcmp oeq float %c3, %c4
1419 %cmp3tmp = fcmp oeq float %c1, %c2
1420 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
1421 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1422 ret <4 x float> %cond
1423
1424 ; CHECK-LABEL: @testqv4floatuge
1425 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1426 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1427 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1428 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1429 ; CHECK: qvfmr 5, 6
1430 ; CHECK: .LBB[[BB]]:
1431 ; CHECK: qvfmr 1, 5
1432 ; CHECK: blr
1433 }
1434
1435 define <4 x float> @testqv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1436 entry:
1437 %cmp1 = fcmp oeq float %c3, %c4
1438 %cmp3tmp = fcmp oeq float %c1, %c2
1439 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
1440 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1441 ret <4 x float> %cond
1442
1443 ; CHECK-LABEL: @testqv4floatsgt
1444 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1445 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1446 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1447 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1448 ; CHECK: qvfmr 5, 6
1449 ; CHECK: .LBB[[BB]]:
1450 ; CHECK: qvfmr 1, 5
1451 ; CHECK: blr
1452 }
1453
1454 define <4 x float> @testqv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1455 entry:
1456 %cmp1 = fcmp oeq float %c3, %c4
1457 %cmp3tmp = fcmp oeq float %c1, %c2
1458 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
1459 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1460 ret <4 x float> %cond
1461
1462 ; CHECK-LABEL: @testqv4floatugt
1463 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1464 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1465 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1466 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1467 ; CHECK: qvfmr 5, 6
1468 ; CHECK: .LBB[[BB]]:
1469 ; CHECK: qvfmr 1, 5
1470 ; CHECK: blr
1471 }
1472
1473 define <4 x float> @testqv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1474 entry:
1475 %cmp1 = fcmp oeq float %c3, %c4
1476 %cmp3tmp = fcmp oeq float %c1, %c2
1477 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
1478 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1479 ret <4 x float> %cond
1480
1481 ; CHECK-LABEL: @testqv4floatne
1482 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1483 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1484 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1485 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1486 ; CHECK: qvfmr 5, 6
1487 ; CHECK: .LBB[[BB]]:
1488 ; CHECK: qvfmr 1, 5
1489 ; CHECK: blr
1490 }
1491
1492 define <4 x i1> @testqv4i1slt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1493 entry:
1494 %cmp1 = fcmp oeq float %c3, %c4
1495 %cmp3tmp = fcmp oeq float %c1, %c2
1496 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
1497 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1498 ret <4 x i1> %cond
1499
1500 ; CHECK-LABEL: @testqv4i1slt
1501 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1502 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1503 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1504 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1505 ; CHECK: qvfmr 5, 6
1506 ; CHECK: .LBB[[BB]]:
1507 ; CHECK: qvfmr 1, 5
1508 ; CHECK: blr
1509 }
1510
1511 define <4 x i1> @testqv4i1ult(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1512 entry:
1513 %cmp1 = fcmp oeq float %c3, %c4
1514 %cmp3tmp = fcmp oeq float %c1, %c2
1515 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
1516 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1517 ret <4 x i1> %cond
1518
1519 ; CHECK-LABEL: @testqv4i1ult
1520 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1521 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1522 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1523 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1524 ; CHECK: qvfmr 5, 6
1525 ; CHECK: .LBB[[BB]]:
1526 ; CHECK: qvfmr 1, 5
1527 ; CHECK: blr
1528 }
1529
1530 define <4 x i1> @testqv4i1sle(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1531 entry:
1532 %cmp1 = fcmp oeq float %c3, %c4
1533 %cmp3tmp = fcmp oeq float %c1, %c2
1534 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
1535 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1536 ret <4 x i1> %cond
1537
1538 ; CHECK-LABEL: @testqv4i1sle
1539 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1540 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1541 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1542 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1543 ; CHECK: qvfmr 5, 6
1544 ; CHECK: .LBB[[BB]]:
1545 ; CHECK: qvfmr 1, 5
1546 ; CHECK: blr
1547 }
1548
1549 define <4 x i1> @testqv4i1ule(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1550 entry:
1551 %cmp1 = fcmp oeq float %c3, %c4
1552 %cmp3tmp = fcmp oeq float %c1, %c2
1553 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
1554 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1555 ret <4 x i1> %cond
1556
1557 ; CHECK-LABEL: @testqv4i1ule
1558 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1559 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1560 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1561 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1562 ; CHECK: qvfmr 5, 6
1563 ; CHECK: .LBB[[BB]]:
1564 ; CHECK: qvfmr 1, 5
1565 ; CHECK: blr
1566 }
1567
1568 define <4 x i1> @testqv4i1eq(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1569 entry:
1570 %cmp1 = fcmp oeq float %c3, %c4
1571 %cmp3tmp = fcmp oeq float %c1, %c2
1572 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
1573 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1574 ret <4 x i1> %cond
1575
1576 ; CHECK-LABEL: @testqv4i1eq
1577 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1578 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1579 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1580 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1581 ; CHECK: qvfmr 5, 6
1582 ; CHECK: .LBB[[BB]]:
1583 ; CHECK: qvfmr 1, 5
1584 ; CHECK: blr
1585 }
1586
1587 define <4 x i1> @testqv4i1sge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1588 entry:
1589 %cmp1 = fcmp oeq float %c3, %c4
1590 %cmp3tmp = fcmp oeq float %c1, %c2
1591 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
1592 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1593 ret <4 x i1> %cond
1594
1595 ; CHECK-LABEL: @testqv4i1sge
1596 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1597 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1598 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1599 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1600 ; CHECK: qvfmr 5, 6
1601 ; CHECK: .LBB[[BB]]:
1602 ; CHECK: qvfmr 1, 5
1603 ; CHECK: blr
1604 }
1605
1606 define <4 x i1> @testqv4i1uge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1607 entry:
1608 %cmp1 = fcmp oeq float %c3, %c4
1609 %cmp3tmp = fcmp oeq float %c1, %c2
1610 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
1611 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1612 ret <4 x i1> %cond
1613
1614 ; CHECK-LABEL: @testqv4i1uge
1615 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1616 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1617 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1618 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1619 ; CHECK: qvfmr 5, 6
1620 ; CHECK: .LBB[[BB]]:
1621 ; CHECK: qvfmr 1, 5
1622 ; CHECK: blr
1623 }
1624
1625 define <4 x i1> @testqv4i1sgt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1626 entry:
1627 %cmp1 = fcmp oeq float %c3, %c4
1628 %cmp3tmp = fcmp oeq float %c1, %c2
1629 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
1630 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1631 ret <4 x i1> %cond
1632
1633 ; CHECK-LABEL: @testqv4i1sgt
1634 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1635 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1636 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1637 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1638 ; CHECK: qvfmr 5, 6
1639 ; CHECK: .LBB[[BB]]:
1640 ; CHECK: qvfmr 1, 5
1641 ; CHECK: blr
1642 }
1643
1644 define <4 x i1> @testqv4i1ugt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1645 entry:
1646 %cmp1 = fcmp oeq float %c3, %c4
1647 %cmp3tmp = fcmp oeq float %c1, %c2
1648 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
1649 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1650 ret <4 x i1> %cond
1651
1652 ; CHECK-LABEL: @testqv4i1ugt
1653 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1654 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1655 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1656 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1657 ; CHECK: qvfmr 5, 6
1658 ; CHECK: .LBB[[BB]]:
1659 ; CHECK: qvfmr 1, 5
1660 ; CHECK: blr
1661 }
1662
1663 define <4 x i1> @testqv4i1ne(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1664 entry:
1665 %cmp1 = fcmp oeq float %c3, %c4
1666 %cmp3tmp = fcmp oeq float %c1, %c2
1667 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
1668 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1669 ret <4 x i1> %cond
1670
1671 ; CHECK-LABEL: @testqv4i1ne
1672 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1673 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1674 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1675 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1676 ; CHECK: qvfmr 5, 6
1677 ; CHECK: .LBB[[BB]]:
1678 ; CHECK: qvfmr 1, 5
1679 ; CHECK: blr
1680 }
1681
1682 attributes #0 = { nounwind readnone "target-cpu"="pwr7" }
1683 attributes #1 = { nounwind readnone "target-cpu"="a2q" }
1684