llvm.org GIT mirror llvm / 6cdb1ab
Merge the OptimizeExts and OptimizeCmps passes into one PeepholeOptimizer pass. This pass should expand with all of the small, fine-grained optimization passes to reduce compile time and increase happiment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110627 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 9 years ago
5 changed file(s) with 297 addition(s) and 342 deletion(s). Raw diff Collapse all Expand all
171171 /// instructions.
172172 FunctionPass *createMachineSinkingPass();
173173
174 /// createOptimizeExtsPass - This pass performs sign / zero extension
175 /// optimization by increasing uses of extended values.
176 FunctionPass *createOptimizeExtsPass();
174 /// createPeepholeOptimizerPass - This pass performs peephole optimizations -
175 /// like extension and comparison eliminations.
176 FunctionPass *createPeepholeOptimizerPass();
177177
178178 /// createOptimizePHIsPass - This pass optimizes machine instruction PHIs
179179 /// to take advantage of opportunities created during DAG legalization.
180180 FunctionPass *createOptimizePHIsPass();
181181
182 /// createOptimizeCmpsPass - This pass performs redundant comparison removal
183 /// optimization.
184 FunctionPass *createOptimizeCmpsPass();
185
186182 /// createStackSlotColoringPass - This pass performs stack slot coloring.
187183 FunctionPass *createStackSlotColoringPass(bool);
188184
352352 PM.add(createDeadMachineInstructionElimPass());
353353 printAndVerify(PM, "After codegen DCE pass");
354354
355 PM.add(createOptimizeExtsPass());
356 PM.add(createOptimizeCmpsPass());
355 PM.add(createPeepholeOptimizerPass());
357356 if (!DisableMachineLICM)
358357 PM.add(createMachineLICMPass());
359358 PM.add(createMachineCSEPass());
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lib/CodeGen/OptimizeCmps.cpp less more
None //===-- OptimizeCmps.cpp - Optimize comparison instrs ---------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass performs optimization of comparison instructions. For instance, in
10 // this code:
11 //
12 // sub r1, 1
13 // cmp r1, 0
14 // bz L1
15 //
16 // If the "sub" instruction all ready sets (or could be modified to set) the
17 // same flag that the "cmp" instruction sets and that "bz" uses, then we can
18 // eliminate the "cmp" instruction.
19 //
20 //===----------------------------------------------------------------------===//
21
22 #define DEBUG_TYPE "opt-compares"
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/ADT/Statistic.h"
31 using namespace llvm;
32
33 STATISTIC(NumEliminated, "Number of compares eliminated");
34
35 static cl::opt
36 EnableOptCmps("enable-optimize-cmps", cl::init(false), cl::Hidden);
37
38 namespace {
39 class OptimizeCmps : public MachineFunctionPass {
40 const TargetMachine *TM;
41 const TargetInstrInfo *TII;
42 MachineRegisterInfo *MRI;
43
44 bool OptimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
45
46 public:
47 static char ID; // Pass identification
48 OptimizeCmps() : MachineFunctionPass(ID) {}
49
50 virtual bool runOnMachineFunction(MachineFunction &MF);
51
52 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
53 AU.setPreservesCFG();
54 MachineFunctionPass::getAnalysisUsage(AU);
55 }
56 };
57 }
58
59 char OptimizeCmps::ID = 0;
60 INITIALIZE_PASS(OptimizeCmps, "opt-cmps",
61 "Optimize comparison instrs", false, false);
62
63 FunctionPass *llvm::createOptimizeCmpsPass() { return new OptimizeCmps(); }
64
65 /// OptimizeCmpInstr - If the instruction is a compare and the previous
66 /// instruction it's comparing against all ready sets (or could be modified to
67 /// set) the same flag as the compare, then we can remove the comparison and use
68 /// the flag from the previous instruction.
69 bool OptimizeCmps::OptimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB) {
70 // If this instruction is a comparison against zero and isn't comparing a
71 // physical register, we can try to optimize it.
72 unsigned SrcReg;
73 int CmpValue;
74 if (!TII->AnalyzeCompare(MI, SrcReg, CmpValue) ||
75 TargetRegisterInfo::isPhysicalRegister(SrcReg) || CmpValue != 0)
76 return false;
77
78 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
79 if (llvm::next(DI) != MRI->def_end())
80 // Only support one definition.
81 return false;
82
83 // Attempt to convert the defining instruction to set the "zero" flag.
84 if (TII->ConvertToSetZeroFlag(&*DI, MI)) {
85 ++NumEliminated;
86 return true;
87 }
88
89 return false;
90 }
91
92 bool OptimizeCmps::runOnMachineFunction(MachineFunction &MF) {
93 TM = &MF.getTarget();
94 TII = TM->getInstrInfo();
95 MRI = &MF.getRegInfo();
96
97 if (!EnableOptCmps) return false;
98
99 bool Changed = false;
100 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
101 MachineBasicBlock *MBB = &*I;
102 for (MachineBasicBlock::iterator
103 MII = MBB->begin(), ME = MBB->end(); MII != ME; ) {
104 MachineInstr *MI = &*MII++;
105 if (MI->getDesc().isCompare())
106 Changed |= OptimizeCmpInstr(MI, MBB);
107 }
108 }
109
110 return Changed;
111 }
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lib/CodeGen/OptimizeExts.cpp less more
None //===-- OptimizeExts.cpp - Optimize sign / zero extension instrs -----===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass performs optimization of sign / zero extension instructions. It
10 // may be extended to handle other instructions of similar property.
11 //
12 // On some targets, some instructions, e.g. X86 sign / zero extension, may
13 // leave the source value in the lower part of the result. This pass will
14 // replace (some) uses of the pre-extension value with uses of the sub-register
15 // of the results.
16 //
17 //===----------------------------------------------------------------------===//
18
19 #define DEBUG_TYPE "ext-opt"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/MachineDominators.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetRegisterInfo.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/ADT/SmallPtrSet.h"
28 #include "llvm/ADT/Statistic.h"
29 using namespace llvm;
30
31 static cl::opt Aggressive("aggressive-ext-opt", cl::Hidden,
32 cl::desc("Aggressive extension optimization"));
33
34 STATISTIC(NumReuse, "Number of extension results reused");
35
36 namespace {
37 class OptimizeExts : public MachineFunctionPass {
38 const TargetMachine *TM;
39 const TargetInstrInfo *TII;
40 MachineRegisterInfo *MRI;
41 MachineDominatorTree *DT; // Machine dominator tree
42
43 public:
44 static char ID; // Pass identification
45 OptimizeExts() : MachineFunctionPass(ID) {}
46
47 virtual bool runOnMachineFunction(MachineFunction &MF);
48
49 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
50 AU.setPreservesCFG();
51 MachineFunctionPass::getAnalysisUsage(AU);
52 if (Aggressive) {
53 AU.addRequired();
54 AU.addPreserved();
55 }
56 }
57
58 private:
59 bool OptimizeInstr(MachineInstr *MI, MachineBasicBlock *MBB,
60 SmallPtrSet &LocalMIs);
61 };
62 }
63
64 char OptimizeExts::ID = 0;
65 INITIALIZE_PASS(OptimizeExts, "opt-exts",
66 "Optimize sign / zero extensions", false, false);
67
68 FunctionPass *llvm::createOptimizeExtsPass() { return new OptimizeExts(); }
69
70 /// OptimizeInstr - If instruction is a copy-like instruction, i.e. it reads
71 /// a single register and writes a single register and it does not modify
72 /// the source, and if the source value is preserved as a sub-register of
73 /// the result, then replace all reachable uses of the source with the subreg
74 /// of the result.
75 /// Do not generate an EXTRACT that is used only in a debug use, as this
76 /// changes the code. Since this code does not currently share EXTRACTs, just
77 /// ignore all debug uses.
78 bool OptimizeExts::OptimizeInstr(MachineInstr *MI, MachineBasicBlock *MBB,
79 SmallPtrSet &LocalMIs) {
80 LocalMIs.insert(MI);
81
82 unsigned SrcReg, DstReg, SubIdx;
83 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
84 return false;
85
86 if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
87 TargetRegisterInfo::isPhysicalRegister(SrcReg))
88 return false;
89
90 MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(SrcReg);
91 if (++UI == MRI->use_nodbg_end())
92 // No other uses.
93 return false;
94
95 // Ok, the source has other uses. See if we can replace the other uses
96 // with use of the result of the extension.
97 SmallPtrSet ReachedBBs;
98 UI = MRI->use_nodbg_begin(DstReg);
99 for (MachineRegisterInfo::use_nodbg_iterator UE = MRI->use_nodbg_end();
100 UI != UE; ++UI)
101 ReachedBBs.insert(UI->getParent());
102
103 bool ExtendLife = true;
104 // Uses that are in the same BB of uses of the result of the instruction.
105 SmallVector Uses;
106 // Uses that the result of the instruction can reach.
107 SmallVector ExtendedUses;
108
109 UI = MRI->use_nodbg_begin(SrcReg);
110 for (MachineRegisterInfo::use_nodbg_iterator UE = MRI->use_nodbg_end();
111 UI != UE; ++UI) {
112 MachineOperand &UseMO = UI.getOperand();
113 MachineInstr *UseMI = &*UI;
114 if (UseMI == MI)
115 continue;
116 if (UseMI->isPHI()) {
117 ExtendLife = false;
118 continue;
119 }
120
121 // It's an error to translate this:
122 //
123 // %reg1025 = %reg1024
124 // ...
125 // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
126 //
127 // into this:
128 //
129 // %reg1025 = %reg1024
130 // ...
131 // %reg1027 = COPY %reg1025:4
132 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
133 //
134 // The problem here is that SUBREG_TO_REG is there to assert that an
135 // implicit zext occurs. It doesn't insert a zext instruction. If we allow
136 // the COPY here, it will give us the value after the , not the
137 // original value of %reg1024 before .
138 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
139 continue;
140
141 MachineBasicBlock *UseMBB = UseMI->getParent();
142 if (UseMBB == MBB) {
143 // Local uses that come after the extension.
144 if (!LocalMIs.count(UseMI))
145 Uses.push_back(&UseMO);
146 } else if (ReachedBBs.count(UseMBB))
147 // Non-local uses where the result of extension is used. Always replace
148 // these unless it's a PHI.
149 Uses.push_back(&UseMO);
150 else if (Aggressive && DT->dominates(MBB, UseMBB))
151 // We may want to extend live range of the extension result in order to
152 // replace these uses.
153 ExtendedUses.push_back(&UseMO);
154 else {
155 // Both will be live out of the def MBB anyway. Don't extend live range of
156 // the extension result.
157 ExtendLife = false;
158 break;
159 }
160 }
161
162 if (ExtendLife && !ExtendedUses.empty())
163 // Ok, we'll extend the liveness of the extension result.
164 std::copy(ExtendedUses.begin(), ExtendedUses.end(),
165 std::back_inserter(Uses));
166
167 // Now replace all uses.
168 bool Changed = false;
169 if (!Uses.empty()) {
170 SmallPtrSet PHIBBs;
171 // Look for PHI uses of the extended result, we don't want to extend the
172 // liveness of a PHI input. It breaks all kinds of assumptions down
173 // stream. A PHI use is expected to be the kill of its source values.
174 UI = MRI->use_nodbg_begin(DstReg);
175 for (MachineRegisterInfo::use_nodbg_iterator UE = MRI->use_nodbg_end();
176 UI != UE; ++UI)
177 if (UI->isPHI())
178 PHIBBs.insert(UI->getParent());
179
180 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
181 for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
182 MachineOperand *UseMO = Uses[i];
183 MachineInstr *UseMI = UseMO->getParent();
184 MachineBasicBlock *UseMBB = UseMI->getParent();
185 if (PHIBBs.count(UseMBB))
186 continue;
187 unsigned NewVR = MRI->createVirtualRegister(RC);
188 BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
189 TII->get(TargetOpcode::COPY), NewVR)
190 .addReg(DstReg, 0, SubIdx);
191 UseMO->setReg(NewVR);
192 ++NumReuse;
193 Changed = true;
194 }
195 }
196
197 return Changed;
198 }
199
200 bool OptimizeExts::runOnMachineFunction(MachineFunction &MF) {
201 TM = &MF.getTarget();
202 TII = TM->getInstrInfo();
203 MRI = &MF.getRegInfo();
204 DT = Aggressive ? &getAnalysis() : 0;
205
206 bool Changed = false;
207
208 SmallPtrSet LocalMIs;
209 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
210 MachineBasicBlock *MBB = &*I;
211 LocalMIs.clear();
212 for (MachineBasicBlock::iterator MII = I->begin(), ME = I->end(); MII != ME;
213 ++MII) {
214 MachineInstr *MI = &*MII;
215 Changed |= OptimizeInstr(MI, MBB, LocalMIs);
216 }
217 }
218
219 return Changed;
220 }
0 //===-- PeepholeOptimizer.cpp - Peephole Optimizations --------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Perform peephole optimizations on the machine code:
10 //
11 // - Optimize Extensions
12 //
13 // Optimization of sign / zero extension instructions. It may be extended to
14 // handle other instructions with similar properties.
15 //
16 // On some targets, some instructions, e.g. X86 sign / zero extension, may
17 // leave the source value in the lower part of the result. This optimization
18 // will replace some uses of the pre-extension value with uses of the
19 // sub-register of the results.
20 //
21 // - Optimize Comparisons
22 //
23 // Optimization of comparison instructions. For instance, in this code:
24 //
25 // sub r1, 1
26 // cmp r1, 0
27 // bz L1
28 //
29 // If the "sub" instruction all ready sets (or could be modified to set) the
30 // same flag that the "cmp" instruction sets and that "bz" uses, then we can
31 // eliminate the "cmp" instruction.
32 //
33 //===----------------------------------------------------------------------===//
34
35 #define DEBUG_TYPE "peephole-opt"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/MachineDominators.h"
38 #include "llvm/CodeGen/MachineInstrBuilder.h"
39 #include "llvm/CodeGen/MachineRegisterInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/ADT/SmallPtrSet.h"
44 #include "llvm/ADT/Statistic.h"
45 using namespace llvm;
46
47 // Optimize Extensions
48 static cl::opt
49 Aggressive("aggressive-ext-opt", cl::Hidden,
50 cl::desc("Aggressive extension optimization"));
51
52 STATISTIC(NumReuse, "Number of extension results reused");
53
54 // Optimize Comparisons
55 static cl::opt
56 EnableOptCmps("enable-optimize-cmps", cl::init(false), cl::Hidden);
57
58 STATISTIC(NumEliminated, "Number of compares eliminated");
59
60 namespace {
61 class PeepholeOptimizer : public MachineFunctionPass {
62 const TargetMachine *TM;
63 const TargetInstrInfo *TII;
64 MachineRegisterInfo *MRI;
65 MachineDominatorTree *DT; // Machine dominator tree
66
67 public:
68 static char ID; // Pass identification
69 PeepholeOptimizer() : MachineFunctionPass(ID) {}
70
71 virtual bool runOnMachineFunction(MachineFunction &MF);
72
73 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
74 AU.setPreservesCFG();
75 MachineFunctionPass::getAnalysisUsage(AU);
76 if (Aggressive) {
77 AU.addRequired();
78 AU.addPreserved();
79 }
80 }
81
82 private:
83 bool OptimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
84 bool OptimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
85 SmallPtrSet &LocalMIs);
86 };
87 }
88
89 char PeepholeOptimizer::ID = 0;
90 INITIALIZE_PASS(PeepholeOptimizer, "peephole-opts",
91 "Peephole Optimizations", false, false);
92
93 FunctionPass *llvm::createPeepholeOptimizerPass() {
94 return new PeepholeOptimizer();
95 }
96
97 /// OptimizeExtInstr - If instruction is a copy-like instruction, i.e. it reads
98 /// a single register and writes a single register and it does not modify the
99 /// source, and if the source value is preserved as a sub-register of the
100 /// result, then replace all reachable uses of the source with the subreg of the
101 /// result.
102 ///
103 /// Do not generate an EXTRACT that is used only in a debug use, as this changes
104 /// the code. Since this code does not currently share EXTRACTs, just ignore all
105 /// debug uses.
106 bool PeepholeOptimizer::
107 OptimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
108 SmallPtrSet &LocalMIs) {
109 LocalMIs.insert(MI);
110
111 unsigned SrcReg, DstReg, SubIdx;
112 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
113 return false;
114
115 if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
116 TargetRegisterInfo::isPhysicalRegister(SrcReg))
117 return false;
118
119 MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(SrcReg);
120 if (++UI == MRI->use_nodbg_end())
121 // No other uses.
122 return false;
123
124 // The source has other uses. See if we can replace the other uses with use of
125 // the result of the extension.
126 SmallPtrSet ReachedBBs;
127 UI = MRI->use_nodbg_begin(DstReg);
128 for (MachineRegisterInfo::use_nodbg_iterator UE = MRI->use_nodbg_end();
129 UI != UE; ++UI)
130 ReachedBBs.insert(UI->getParent());
131
132 // Uses that are in the same BB of uses of the result of the instruction.
133 SmallVector Uses;
134
135 // Uses that the result of the instruction can reach.
136 SmallVector ExtendedUses;
137
138 bool ExtendLife = true;
139 UI = MRI->use_nodbg_begin(SrcReg);
140 for (MachineRegisterInfo::use_nodbg_iterator UE = MRI->use_nodbg_end();
141 UI != UE; ++UI) {
142 MachineOperand &UseMO = UI.getOperand();
143 MachineInstr *UseMI = &*UI;
144 if (UseMI == MI)
145 continue;
146
147 if (UseMI->isPHI()) {
148 ExtendLife = false;
149 continue;
150 }
151
152 // It's an error to translate this:
153 //
154 // %reg1025 = %reg1024
155 // ...
156 // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
157 //
158 // into this:
159 //
160 // %reg1025 = %reg1024
161 // ...
162 // %reg1027 = COPY %reg1025:4
163 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
164 //
165 // The problem here is that SUBREG_TO_REG is there to assert that an
166 // implicit zext occurs. It doesn't insert a zext instruction. If we allow
167 // the COPY here, it will give us the value after the , not the
168 // original value of %reg1024 before .
169 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
170 continue;
171
172 MachineBasicBlock *UseMBB = UseMI->getParent();
173 if (UseMBB == MBB) {
174 // Local uses that come after the extension.
175 if (!LocalMIs.count(UseMI))
176 Uses.push_back(&UseMO);
177 } else if (ReachedBBs.count(UseMBB)) {
178 // Non-local uses where the result of the extension is used. Always
179 // replace these unless it's a PHI.
180 Uses.push_back(&UseMO);
181 } else if (Aggressive && DT->dominates(MBB, UseMBB)) {
182 // We may want to extend the live range of the extension result in order
183 // to replace these uses.
184 ExtendedUses.push_back(&UseMO);
185 } else {
186 // Both will be live out of the def MBB anyway. Don't extend live range of
187 // the extension result.
188 ExtendLife = false;
189 break;
190 }
191 }
192
193 if (ExtendLife && !ExtendedUses.empty())
194 // Extend the liveness of the extension result.
195 std::copy(ExtendedUses.begin(), ExtendedUses.end(),
196 std::back_inserter(Uses));
197
198 // Now replace all uses.
199 bool Changed = false;
200 if (!Uses.empty()) {
201 SmallPtrSet PHIBBs;
202
203 // Look for PHI uses of the extended result, we don't want to extend the
204 // liveness of a PHI input. It breaks all kinds of assumptions down
205 // stream. A PHI use is expected to be the kill of its source values.
206 UI = MRI->use_nodbg_begin(DstReg);
207 for (MachineRegisterInfo::use_nodbg_iterator
208 UE = MRI->use_nodbg_end(); UI != UE; ++UI)
209 if (UI->isPHI())
210 PHIBBs.insert(UI->getParent());
211
212 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
213 for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
214 MachineOperand *UseMO = Uses[i];
215 MachineInstr *UseMI = UseMO->getParent();
216 MachineBasicBlock *UseMBB = UseMI->getParent();
217 if (PHIBBs.count(UseMBB))
218 continue;
219
220 unsigned NewVR = MRI->createVirtualRegister(RC);
221 BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
222 TII->get(TargetOpcode::COPY), NewVR)
223 .addReg(DstReg, 0, SubIdx);
224
225 UseMO->setReg(NewVR);
226 ++NumReuse;
227 Changed = true;
228 }
229 }
230
231 return Changed;
232 }
233
234 /// OptimizeCmpInstr - If the instruction is a compare and the previous
235 /// instruction it's comparing against all ready sets (or could be modified to
236 /// set) the same flag as the compare, then we can remove the comparison and use
237 /// the flag from the previous instruction.
238 bool PeepholeOptimizer::OptimizeCmpInstr(MachineInstr *MI,
239 MachineBasicBlock *MBB) {
240 if (!EnableOptCmps) return false;
241
242 // If this instruction is a comparison against zero and isn't comparing a
243 // physical register, we can try to optimize it.
244 unsigned SrcReg;
245 int CmpValue;
246 if (!TII->AnalyzeCompare(MI, SrcReg, CmpValue) ||
247 TargetRegisterInfo::isPhysicalRegister(SrcReg) || CmpValue != 0)
248 return false;
249
250 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
251 if (llvm::next(DI) != MRI->def_end())
252 // Only support one definition.
253 return false;
254
255 // Attempt to convert the defining instruction to set the "zero" flag.
256 if (TII->ConvertToSetZeroFlag(&*DI, MI)) {
257 ++NumEliminated;
258 return true;
259 }
260
261 return false;
262 }
263
264 bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
265 TM = &MF.getTarget();
266 TII = TM->getInstrInfo();
267 MRI = &MF.getRegInfo();
268 DT = Aggressive ? &getAnalysis() : 0;
269
270 bool Changed = false;
271
272 SmallPtrSet LocalMIs;
273 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
274 MachineBasicBlock *MBB = &*I;
275 LocalMIs.clear();
276
277 for (MachineBasicBlock::iterator
278 MII = I->begin(), ME = I->end(); MII != ME; ) {
279 MachineInstr *MI = &*MII;
280
281 if (MI->getDesc().isCompare()) {
282 ++MII; // The iterator may become invalid if the compare is deleted.
283 Changed |= OptimizeCmpInstr(MI, MBB);
284 } else {
285 Changed |= OptimizeExtInstr(MI, MBB, LocalMIs);
286 ++MII;
287 }
288 }
289 }
290
291 return Changed;
292 }