llvm.org GIT mirror llvm / 6c9712f
New machine model for cortex-a9. Schedule for resources and latency. Schedule more conservatively to account for stalls on floating point resources and latency. Use the AGU resource to model latency stalls since it's shared between FP and LD/ST instructions. This might not be completely accurate but should work well in practice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198125 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 5 years ago
2 changed file(s) with 22 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
19011901
19021902 //===----------------------------------------------------------------------===//
19031903 // Define each kind of processor resource and number available.
1904 //
1905 // The AGU unit has BufferSize=1 so that the latency between operations
1906 // that use it are considered to stall other operations.
1907 //
1908 // The FP unit has BufferSize=0 so that it is a hard dispatch
1909 // hazard. No instruction may be dispatched while the unit is reserved.
19041910
19051911 let SchedModel = CortexA9Model in {
19061912
19071913 def A9UnitALU : ProcResource<2>;
19081914 def A9UnitMul : ProcResource<1> { let Super = A9UnitALU; }
1909 def A9UnitAGU : ProcResource<1>;
1915 def A9UnitAGU : ProcResource<1> { let BufferSize = 1; }
19101916 def A9UnitLS : ProcResource<1>;
1911 def A9UnitFP : ProcResource<1> { let BufferSize = 1; }
1917 def A9UnitFP : ProcResource<1> { let BufferSize = 0; }
19121918 def A9UnitB : ProcResource<1>;
19131919
19141920 //===----------------------------------------------------------------------===//
None ; RUN: llc < %s -march=arm -mtriple=thumbv7-apple-ios7.0.0 -float-abi=hard -mcpu=cortex-a9 -disable-post-ra -misched-bench -scheditins=false | FileCheck %s
0 ; RUN: llc < %s -march=arm -mtriple=thumbv7-apple-ios7.0.0 -float-abi=hard -mcpu=cortex-a9 -misched-postra -misched-bench -scheditins=false | FileCheck %s
11 ;
22 ; Test MI-Sched suppory latency based stalls on in in-order pipeline
33 ; using the new machine model.
1414 ; CHECK: vldr
1515 ; CHECK: vldr
1616 ; CHECK: vldr
17 ; CHECK-NEXT: vmul
1817 ; CHECK-NEXT: vadd
1918 ; CHECK-NEXT: vadd
2019 ; CHECK-NEXT: vldr
2120 ; CHECK-NEXT: vldr
21 ; CHECK-NEXT: vldr
22 ; CHECK-NEXT: vadd
2223 ; CHECK-NEXT: vmul
24 ; CHECK-NEXT: vldr
25 ; CHECK-NEXT: vadd
26 ; CHECK-NEXT: vadd
27 ; CHECK-NEXT: vmul
28 ; CHECK-NEXT: vldr
2329 ; CHECK-NEXT: vadd
2430 ; CHECK-NEXT: vadd
2531 ; CHECK-NEXT: vldr
32 ; CHECK-NEXT: vmul
33 ; CHECK-NEXT: vadd
34 ; CHECK-NEXT: vldr
35 ; CHECK-NEXT: vadd
2636 ; CHECK-NEXT: vldr
2737 ; CHECK-NEXT: vmul
2838 ; CHECK-NEXT: vadd
39 ; CHECK-NEXT: vldr
2940 ; CHECK-NEXT: vadd
30 ; CHECK-NEXT: vldr
3141 ; CHECK-NEXT: vldr
3242 ; CHECK-NEXT: vmul
3343 ; CHECK-NEXT: vadd
44 ; CHECK-NEXT: vldr
3445 ; CHECK-NEXT: vadd
35 ; CHECK-NEXT: vldr
3646 ; CHECK-NEXT: vldr
3747 ; CHECK-NEXT: vmul
3848 ; CHECK-NEXT: vadd
39 ; CHECK-NEXT: vadd
40 ; CHECK-NEXT: vldr
4149 ; CHECK-NEXT: vldr
4250 ; CHECK-NEXT: vmul
4351 ; CHECK-NEXT: vadd
44 ; CHECK-NEXT: vadd
45 ; CHECK-NEXT: vldr
4652 ; CHECK-NEXT: vldr
4753 ; CHECK-NEXT: vmul
48 ; CHECK-NEXT: vadd
49 ; CHECK-NEXT: vadd
50 ; CHECK-NEXT: vldr
51 ; CHECK-NEXT: vldr
52 ; CHECK-NEXT: vmul
53 ; CHECK-NEXT: vadd
5454 ; CHECK-NEXT: vadd
5555 ; CHECK-NEXT: vldr
5656 ; CHECK-NEXT: vadd