llvm.org GIT mirror llvm / 6c6dbe6
[AMDGPU] Disassembler: print label names in branch instructions Summary: Add AMDGPUSymbolizer for finding names for labels from ELF symbol table. Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D24802 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282394 91177308-0d34-0410-b5e6-96231b3b80d8 Sam Kolton 3 years ago
5 changed file(s) with 159 addition(s) and 57 deletion(s). Raw diff Collapse all Expand all
2727 #include "llvm/MC/MCInst.h"
2828 #include "llvm/MC/MCInstrDesc.h"
2929 #include "llvm/MC/MCSubtargetInfo.h"
30 #include "llvm/Support/ELF.h"
3031 #include "llvm/Support/Endian.h"
3132 #include "llvm/Support/Debug.h"
3233 #include "llvm/Support/TargetRegistry.h"
4546 return Opnd.isValid() ?
4647 MCDisassembler::Success :
4748 MCDisassembler::SoftFail;
49 }
50
51 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
52 uint64_t Addr, const void *Decoder) {
53 auto DAsm = static_cast(Decoder);
54
55 APInt SignedOffset(18, Imm * 4, true);
56 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
57
58 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
59 return MCDisassembler::Success;
60 return addOperand(Inst, MCOperand::createImm(Imm));
4861 }
4962
5063 #define DECODE_OPERAND2(RegClass, DecName) \
430443 return errOperand(Val, "unknown operand encoding " + Twine(Val));
431444 }
432445
446 //===----------------------------------------------------------------------===//
447 // AMDGPUSymbolizer
448 //===----------------------------------------------------------------------===//
449
450 // Try to find symbol name for specified label
451 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
452 raw_ostream &/*cStream*/, int64_t Value,
453 uint64_t /*Address*/, bool IsBranch,
454 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
455 typedef std::tuple SymbolInfoTy;
456 typedef std::vector SectionSymbolsTy;
457
458 if (!IsBranch) {
459 return false;
460 }
461
462 auto *Symbols = static_cast(DisInfo);
463 auto Result = std::find_if(Symbols->begin(), Symbols->end(),
464 [Value](const SymbolInfoTy& Val) {
465 return std::get<0>(Val) == static_cast(Value)
466 && std::get<2>(Val) == ELF::STT_NOTYPE;
467 });
468 if (Result != Symbols->end()) {
469 auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
470 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
471 Inst.addOperand(MCOperand::createExpr(Add));
472 return true;
473 }
474 return false;
475 }
476
477 //===----------------------------------------------------------------------===//
478 // Initialization
479 //===----------------------------------------------------------------------===//
480
481 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
482 LLVMOpInfoCallback /*GetOpInfo*/,
483 LLVMSymbolLookupCallback /*SymbolLookUp*/,
484 void *DisInfo,
485 MCContext *Ctx,
486 std::unique_ptr &&RelInfo) {
487 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
488 }
489
433490 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
434491 const MCSubtargetInfo &STI,
435492 MCContext &Ctx) {
438495
439496 extern "C" void LLVMInitializeAMDGPUDisassembler() {
440497 TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler);
441 }
498 TargetRegistry::RegisterMCSymbolizer(TheGCNTarget, createAMDGPUSymbolizer);
499 }
1717
1818 #include "llvm/ADT/ArrayRef.h"
1919 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
20 #include "llvm/MC/MCDisassembler/MCSymbolizer.h"
2021
2122 namespace llvm {
2223
23 class MCContext;
24 class MCInst;
25 class MCOperand;
26 class MCSubtargetInfo;
27 class Twine;
24 class MCContext;
25 class MCInst;
26 class MCOperand;
27 class MCSubtargetInfo;
28 class Twine;
2829
29 class AMDGPUDisassembler : public MCDisassembler {
30 private:
31 mutable ArrayRef Bytes;
30 //===----------------------------------------------------------------------===//
31 // AMDGPUDisassembler
32 //===----------------------------------------------------------------------===//
3233
33 public:
34 AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
35 MCDisassembler(STI, Ctx) {}
34 class AMDGPUDisassembler : public MCDisassembler {
35 private:
36 mutable ArrayRef Bytes;
3637
37 ~AMDGPUDisassembler() {}
38 public:
39 AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
40 MCDisassembler(STI, Ctx) {}
3841
39 DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
40 ArrayRef Bytes, uint64_t Address,
41 raw_ostream &WS, raw_ostream &CS) const override;
42 ~AMDGPUDisassembler() {}
4243
43 const char* getRegClassName(unsigned RegClassID) const;
44 DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
45 ArrayRef Bytes, uint64_t Address,
46 raw_ostream &WS, raw_ostream &CS) const override;
4447
45 MCOperand createRegOperand(unsigned int RegId) const;
46 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
47 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
48 const char* getRegClassName(unsigned RegClassID) const;
4849
49 MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
50 MCOperand createRegOperand(unsigned int RegId) const;
51 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
52 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
5053
51 DecodeStatus tryDecodeInst(const uint8_t* Table,
52 MCInst &MI,
53 uint64_t Inst,
54 uint64_t Address) const;
54 MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
5555
56 MCOperand decodeOperand_VGPR_32(unsigned Val) const;
57 MCOperand decodeOperand_VS_32(unsigned Val) const;
58 MCOperand decodeOperand_VS_64(unsigned Val) const;
56 DecodeStatus tryDecodeInst(const uint8_t* Table,
57 MCInst &MI,
58 uint64_t Inst,
59 uint64_t Address) const;
5960
60 MCOperand decodeOperand_VReg_64(unsigned Val) const;
61 MCOperand decodeOperand_VReg_96(unsigned Val) const;
62 MCOperand decodeOperand_VReg_128(unsigned Val) const;
61 MCOperand decodeOperand_VGPR_32(unsigned Val) const;
62 MCOperand decodeOperand_VS_32(unsigned Val) const;
63 MCOperand decodeOperand_VS_64(unsigned Val) const;
6364
64 MCOperand decodeOperand_SReg_32(unsigned Val) const;
65 MCOperand decodeOperand_SReg_32_XM0(unsigned Val) const;
66 MCOperand decodeOperand_SReg_64(unsigned Val) const;
67 MCOperand decodeOperand_SReg_128(unsigned Val) const;
68 MCOperand decodeOperand_SReg_256(unsigned Val) const;
69 MCOperand decodeOperand_SReg_512(unsigned Val) const;
65 MCOperand decodeOperand_VReg_64(unsigned Val) const;
66 MCOperand decodeOperand_VReg_96(unsigned Val) const;
67 MCOperand decodeOperand_VReg_128(unsigned Val) const;
7068
71 enum OpWidthTy {
72 OPW32,
73 OPW64,
74 OPW128,
75 OPW_LAST_,
76 OPW_FIRST_ = OPW32
77 };
78 unsigned getVgprClassId(const OpWidthTy Width) const;
79 unsigned getSgprClassId(const OpWidthTy Width) const;
80 unsigned getTtmpClassId(const OpWidthTy Width) const;
69 MCOperand decodeOperand_SReg_32(unsigned Val) const;
70 MCOperand decodeOperand_SReg_32_XM0(unsigned Val) const;
71 MCOperand decodeOperand_SReg_64(unsigned Val) const;
72 MCOperand decodeOperand_SReg_128(unsigned Val) const;
73 MCOperand decodeOperand_SReg_256(unsigned Val) const;
74 MCOperand decodeOperand_SReg_512(unsigned Val) const;
8175
82 static MCOperand decodeIntImmed(unsigned Imm);
83 static MCOperand decodeFPImmed(bool Is32, unsigned Imm);
84 MCOperand decodeLiteralConstant() const;
76 enum OpWidthTy {
77 OPW32,
78 OPW64,
79 OPW128,
80 OPW_LAST_,
81 OPW_FIRST_ = OPW32
82 };
83 unsigned getVgprClassId(const OpWidthTy Width) const;
84 unsigned getSgprClassId(const OpWidthTy Width) const;
85 unsigned getTtmpClassId(const OpWidthTy Width) const;
8586
86 MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
87 MCOperand decodeSpecialReg32(unsigned Val) const;
88 MCOperand decodeSpecialReg64(unsigned Val) const;
89 };
87 static MCOperand decodeIntImmed(unsigned Imm);
88 static MCOperand decodeFPImmed(bool Is32, unsigned Imm);
89 MCOperand decodeLiteralConstant() const;
90
91 MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
92 MCOperand decodeSpecialReg32(unsigned Val) const;
93 MCOperand decodeSpecialReg64(unsigned Val) const;
94 };
95
96 //===----------------------------------------------------------------------===//
97 // AMDGPUSymbolizer
98 //===----------------------------------------------------------------------===//
99
100 class AMDGPUSymbolizer : public MCSymbolizer {
101 private:
102 void *DisInfo;
103
104 public:
105 AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr &&RelInfo,
106 void *disInfo)
107 : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
108
109 bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
110 int64_t Value, uint64_t Address,
111 bool IsBranch, uint64_t Offset,
112 uint64_t InstSize) override;
113
114 void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
115 int64_t Value,
116 uint64_t Address) override {
117 assert(false && "Implement if needed");
118 }
119 };
120
90121 } // namespace llvm
91122
92123 #endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
290290
291291 def sopp_brtarget : Operand {
292292 let EncoderMethod = "getSOPPBrEncoding";
293 let DecoderMethod = "decodeSoppBrTarget";
293294 let OperandType = "OPERAND_PCREL";
294295 let ParserMatchClass = SoppBrTarget;
295296 }
55 // VI: s_branch loop_start ; encoding: [A,A,0x82,0xbf]
66 // VI-NEXT: ; fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br
77 // BIN: loop_start:
8 // BIN-NEXT: BF82FFFF
8 // BIN-NEXT: s_branch loop_start // 000000000000: BF82FFFF
99
1010 s_branch loop_end
1111 // VI: s_branch loop_end ; encoding: [A,A,0x82,0xbf]
1212 // VI-NEXT: ; fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br
13 // BIN: BF820000
13 // BIN: s_branch loop_end // 000000000004: BF820000
1414 // BIN: loop_end:
1515 loop_end:
1616
1717 s_branch gds
1818 // VI: s_branch gds ; encoding: [A,A,0x82,0xbf]
1919 // VI-NEXT: ; fixup A - offset: 0, value: gds, kind: fixup_si_sopp_br
20 // BIN: BF820000
20 // BIN: s_branch gds // 000000000008: BF820000
2121 // BIN: gds:
2222 gds:
2323 s_nop 0
12261226
12271227 std::sort(DataMappingSymsAddr.begin(), DataMappingSymsAddr.end());
12281228 std::sort(TextMappingSymsAddr.begin(), TextMappingSymsAddr.end());
1229
1230 if (Obj->isELF() && Obj->getArch() == Triple::amdgcn) {
1231 // AMDGPU disassembler uses symbolizer for printing labels
1232 std::unique_ptr RelInfo(
1233 TheTarget->createMCRelocationInfo(TripleName, Ctx));
1234 if (RelInfo) {
1235 std::unique_ptr Symbolizer(
1236 TheTarget->createMCSymbolizer(
1237 TripleName, nullptr, nullptr, &Symbols, &Ctx, std::move(RelInfo)));
1238 DisAsm->setSymbolizer(std::move(Symbolizer));
1239 }
1240 }
12291241
12301242 // Make a list of all the relocations for this section.
12311243 std::vector Rels;