llvm.org GIT mirror llvm / 6c28a7e
This patch fixes failures in the SingleSource/Regression/C/uint64_to_float test case on PowerPC caused by rounding errors when converting from a 64-bit integer to a single-precision floating point. The reason for this are double-rounding effects, since on PowerPC we have to convert to an intermediate double-precision value first, which gets rounded to the final single-precision result. The patch fixes the problem by preparing the 64-bit integer so that the first conversion step to double-precision will always be exact, and the final rounding step will result in the correctly-rounded single-precision result. The generated code sequence is equivalent to what GCC would generate. When -enable-unsafe-fp-math is in effect, that extra effort is omitted and we accept possible rounding errors (just like GCC does as well). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166178 91177308-0d34-0410-b5e6-96231b3b80d8 Ulrich Weigand 8 years ago
2 changed file(s) with 73 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
42234223 return SDValue();
42244224
42254225 if (Op.getOperand(0).getValueType() == MVT::i64) {
4226 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0));
4226 SDValue SINT = Op.getOperand(0);
4227 // When converting to single-precision, we actually need to convert
4228 // to double-precision first and then round to single-precision.
4229 // To avoid double-rounding effects during that operation, we have
4230 // to prepare the input operand. Bits that might be truncated when
4231 // converting to double-precision are replaced by a bit that won't
4232 // be lost at this stage, but is below the single-precision rounding
4233 // position.
4234 //
4235 // However, if -enable-unsafe-fp-math is in effect, accept double
4236 // rounding to avoid the extra overhead.
4237 if (Op.getValueType() == MVT::f32 &&
4238 !DAG.getTarget().Options.UnsafeFPMath) {
4239
4240 // Twiddle input to make sure the low 11 bits are zero. (If this
4241 // is the case, we are guaranteed the value will fit into the 53 bit
4242 // mantissa of an IEEE double-precision value without rounding.)
4243 // If any of those low 11 bits were not zero originally, make sure
4244 // bit 12 (value 2048) is set instead, so that the final rounding
4245 // to single-precision gets the correct result.
4246 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4247 SINT, DAG.getConstant(2047, MVT::i64));
4248 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4249 Round, DAG.getConstant(2047, MVT::i64));
4250 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4251 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4252 Round, DAG.getConstant(-2048, MVT::i64));
4253
4254 // However, we cannot use that value unconditionally: if the magnitude
4255 // of the input value is small, the bit-twiddling we did above might
4256 // end up visibly changing the output. Fortunately, in that case, we
4257 // don't need to twiddle bits since the original input will convert
4258 // exactly to double-precision floating-point already. Therefore,
4259 // construct a conditional to use the original value if the top 11
4260 // bits are all sign-bit copies, and use the rounded value computed
4261 // above otherwise.
4262 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4263 SINT, DAG.getConstant(53, MVT::i32));
4264 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4265 Cond, DAG.getConstant(1, MVT::i64));
4266 Cond = DAG.getSetCC(dl, MVT::i32,
4267 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4268
4269 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4270 }
4271 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
42274272 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
42284273 if (Op.getValueType() == MVT::f32)
42294274 FP = DAG.getNode(ISD::FP_ROUND, dl,
0 ; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
1 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
2 target triple = "powerpc64-unknown-linux-gnu"
3
4 define float @test(i64 %x) nounwind readnone {
5 entry:
6 %conv = sitofp i64 %x to float
7 ret float %conv
8 }
9
10 ; Verify that we get the code sequence needed to avoid double-rounding.
11 ; Note that only parts of the sequence are checked for here, to allow
12 ; for minor code generation differences.
13
14 ; CHECK: sradi [[REGISTER:[0-9]+]], 3, 53
15 ; CHECK: addi [[REGISTER:[0-9]+]], [[REGISTER]], 1
16 ; CHECK: cmpldi 0, [[REGISTER]], 1
17 ; CHECK: isel [[REGISTER:[0-9]+]], {{[0-9]+}}, 3, 1
18 ; CHECK: std [[REGISTER]], -{{[0-9]+}}(1)
19
20
21 ; Also check that with -enable-unsafe-fp-math we do not get that extra
22 ; code sequence. Simply verify that there is no "isel" present.
23
24 ; RUN: llc -mcpu=pwr7 -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=UNSAFE
25 ; CHECK-UNSAFE-NOT: isel
26