llvm.org GIT mirror llvm / 6c22695
For ARM disassembly only print 32 unsigned bits for the address of branch targets so if the branch target has the high bit set it does not get printed as: beq 0xffffffff8008c404 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154685 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Enderby 8 years ago
1 changed file(s) with 2 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
208208 } else {
209209 assert(Op.isExpr() && "unknown operand kind in printOperand");
210210 // If a symbolic branch target was added as a constant expression then print
211 // that address in hex.
211 // that address in hex. And only print 32 unsigned bits for the address.
212212 const MCConstantExpr *BranchTarget = dyn_cast(Op.getExpr());
213213 int64_t Address;
214214 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
215215 O << "0x";
216 O.write_hex(Address);
216 O.write_hex((uint32_t)Address);
217217 }
218218 else {
219219 // Otherwise, just print the expression.