llvm.org GIT mirror llvm / 6c00f26
Merging r213653: ------------------------------------------------------------------------ r213653 | sstankovic | 2014-07-22 14:36:02 +0100 (Tue, 22 Jul 2014) | 7 lines [mips] Fix two patterns that select i32's (for MIPS32r6) / i64's (for MIPS64r6) from setne comparison with an i32. The patterns that are fixed: * (select (i32 (setne i32, immZExt16)), i32, i32) (for MIPS32r6) * (select (i32 (setne i32, immZExt16)), i64, i64) (for MIPS64r6) ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@213746 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Sanders 6 years ago
3 changed file(s) with 78 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
795795 (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
796796 ISA_MIPS32R6;
797797 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
798 (OR (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)),
799 (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)))>,
798 (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
799 (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
800800 ISA_MIPS32R6;
801801 def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t,
802802 i32:$f),
190190 immZExt16:$imm))))>,
191191 ISA_MIPS64R6;
192192 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
193 (OR64 (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
193 (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
194194 immZExt16:$imm))),
195 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
195 (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
196196 immZExt16:$imm))))>,
197197 ISA_MIPS64R6;
198198
115115 ret i32 %cond
116116 }
117117
118 ; ALL-LABEL: cmov3_ne:
119
120 ; We won't check the result register since we can't know if the move is first
121 ; or last. We do know it will be either one of two registers so we can at least
122 ; check that.
123
124 ; FIXME: Use xori instead of addiu+xor.
125 ; 32-CMOV: addiu $[[R0:[0-9]+]], $zero, 234
126 ; 32-CMOV: xor $[[R1:[0-9]+]], $4, $[[R0]]
127 ; 32-CMOV: movn ${{[26]}}, $5, $[[R1]]
128
129 ; 32-CMP-DAG: xori $[[CC:[0-9]+]], $4, 234
130 ; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $5, $[[CC]]
131 ; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $6, $[[CC]]
132 ; 32-CMP-DAG: or $2, $[[T0]], $[[T1]]
133
134 ; FIXME: Use xori instead of addiu+xor.
135 ; 64-CMOV: addiu $[[R0:[0-9]+]], $zero, 234
136 ; 64-CMOV: xor $[[R1:[0-9]+]], $4, $[[R0]]
137 ; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]
138
139 ; 64-CMP-DAG: xori $[[CC:[0-9]+]], $4, 234
140 ; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $5, $[[CC]]
141 ; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $6, $[[CC]]
142 ; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
143
144 define i32 @cmov3_ne(i32 %a, i32 %b, i32 %c) nounwind readnone {
145 entry:
146 %cmp = icmp ne i32 %a, 234
147 %cond = select i1 %cmp, i32 %b, i32 %c
148 ret i32 %cond
149 }
150
118151 ; ALL-LABEL: cmov4:
119152
120153 ; We won't check the result register since we can't know if the move is first
148181 define i64 @cmov4(i32 %a, i64 %b, i64 %c) nounwind readnone {
149182 entry:
150183 %cmp = icmp eq i32 %a, 234
184 %cond = select i1 %cmp, i64 %b, i64 %c
185 ret i64 %cond
186 }
187
188 ; ALL-LABEL: cmov4_ne:
189
190 ; We won't check the result register since we can't know if the move is first
191 ; or last. We do know it will be one of two registers so we can at least check
192 ; that.
193
194 ; FIXME: Use xori instead of addiu+xor.
195 ; 32-CMOV-DAG: addiu $[[R0:[0-9]+]], $zero, 234
196 ; 32-CMOV-DAG: xor $[[R1:[0-9]+]], $4, $[[R0]]
197 ; 32-CMOV-DAG: lw $[[R2:2]], 16($sp)
198 ; 32-CMOV-DAG: lw $[[R3:3]], 20($sp)
199 ; 32-CMOV-DAG: movn $[[R2]], $6, $[[R1]]
200 ; 32-CMOV-DAG: movn $[[R3]], $7, $[[R1]]
201
202 ; 32-CMP-DAG: xori $[[R0:[0-9]+]], $4, 234
203 ; 32-CMP-DAG: lw $[[R1:[0-9]+]], 16($sp)
204 ; 32-CMP-DAG: lw $[[R2:[0-9]+]], 20($sp)
205 ; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $6, $[[R0]]
206 ; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $7, $[[R0]]
207 ; 32-CMP-DAG: seleqz $[[T2:[0-9]+]], $[[R1]], $[[R0]]
208 ; 32-CMP-DAG: seleqz $[[T3:[0-9]+]], $[[R2]], $[[R0]]
209 ; 32-CMP-DAG: or $2, $[[T0]], $[[T2]]
210 ; 32-CMP-DAG: or $3, $[[T1]], $[[T3]]
211
212 ; FIXME: Use xori instead of addiu+xor.
213 ; 64-CMOV: addiu $[[R0:[0-9]+]], $zero, 234
214 ; 64-CMOV: xor $[[R1:[0-9]+]], $4, $[[R0]]
215 ; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]
216
217 ; 64-CMP-DAG: xori $[[R0:[0-9]+]], $4, 234
218 ; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $5, $[[R0]]
219 ; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $6, $[[R0]]
220 ; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
221
222 define i64 @cmov4_ne(i32 %a, i64 %b, i64 %c) nounwind readnone {
223 entry:
224 %cmp = icmp ne i32 %a, 234
151225 %cond = select i1 %cmp, i64 %b, i64 %c
152226 ret i64 %cond
153227 }