llvm.org GIT mirror llvm / 6bfba2e
Prefer cheap registers for busy live ranges. On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 9 years ago
9 changed file(s) with 81 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
7777 // -1 indicates that the gcc number is undefined and -2 that register number
7878 // is invalid for this mode/flavour.
7979 list DwarfNumbers = [];
80
81 // CostPerUse - Additional cost of instructions using this register compared
82 // to other registers in its class. The register allocator will try to
83 // minimize the number of instructions using a register with a CostPerUse.
84 // This is used by the x86-64 and ARM Thumb targets where some registers
85 // require larger instruction encodings.
86 int CostPerUse = 0;
8087 }
8188
8289 // RegisterWithSubRegs - This can be used to define instances of Register which
4545 const unsigned *Overlaps; // Overlapping registers, described above
4646 const unsigned *SubRegs; // Sub-register set, described above
4747 const unsigned *SuperRegs; // Super-register set, described above
48 unsigned CostPerUse; // Extra cost of instructions using register.
4849 };
4950
5051 class TargetRegisterClass {
425426 return get(RegNo).Name;
426427 }
427428
429 /// getCostPerUse - Return the additional cost of using this register instead
430 /// of other registers in its class.
431 unsigned getCostPerUse(unsigned RegNo) const {
432 return get(RegNo).CostPerUse;
433 }
434
428435 /// getNumRegs - Return the number of registers this target has (useful for
429436 /// sizing arrays holding per register information)
430437 unsigned getNumRegs() const {
277277 << " to " << PrintReg(PhysReg, TRI) << '\n');
278278 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
279279 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
280 MRI->setPhysRegUsed(PhysReg);
280281 PhysReg2LiveUnion[PhysReg].unify(VirtReg);
281282 ++NumAssigned;
282283 }
186186 unsigned nextSplitPoint(unsigned);
187187 bool canEvictInterference(LiveInterval&, unsigned, float&);
188188
189 unsigned tryAssign(LiveInterval&, AllocationOrder&,
190 SmallVectorImpl&);
189191 unsigned tryEvict(LiveInterval&, AllocationOrder&,
190 SmallVectorImpl&);
192 SmallVectorImpl&, unsigned = ~0u);
191193 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
192194 SmallVectorImpl&);
193195 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
333335 return LI;
334336 }
335337
338
339 //===----------------------------------------------------------------------===//
340 // Direct Assignment
341 //===----------------------------------------------------------------------===//
342
343 /// tryAssign - Try to assign VirtReg to an available register.
344 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
345 AllocationOrder &Order,
346 SmallVectorImpl &NewVRegs) {
347 Order.rewind();
348 unsigned PhysReg;
349 while ((PhysReg = Order.next()))
350 if (!checkPhysRegInterference(VirtReg, PhysReg))
351 break;
352 if (!PhysReg || Order.isHint(PhysReg))
353 return PhysReg;
354
355 // PhysReg is available. Try to evict interference from a cheaper alternative.
356 unsigned Cost = TRI->getCostPerUse(PhysReg);
357
358 // Most registers have 0 additional cost.
359 if (!Cost)
360 return PhysReg;
361
362 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
363 << '\n');
364 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
365 return CheapReg ? CheapReg : PhysReg;
366 }
367
368
336369 //===----------------------------------------------------------------------===//
337370 // Interference eviction
338371 //===----------------------------------------------------------------------===//
370403 /// @return Physreg to assign VirtReg, or 0.
371404 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
372405 AllocationOrder &Order,
373 SmallVectorImpl &NewVRegs){
406 SmallVectorImpl &NewVRegs,
407 unsigned CostPerUseLimit) {
374408 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
375409
376410 // Keep track of the lightest single interference seen so far.
379413
380414 Order.rewind();
381415 while (unsigned PhysReg = Order.next()) {
416 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
417 continue;
418 // The first use of a register in a function has cost 1.
419 if (CostPerUseLimit == 1 && !MRI->isPhysRegUsed(PhysReg))
420 continue;
421
382422 float Weight = BestWeight;
383423 if (!canEvictInterference(VirtReg, PhysReg, Weight))
384424 continue;
12291269 SmallVectorImpl &NewVRegs) {
12301270 // First try assigning a free register.
12311271 AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
1232 while (unsigned PhysReg = Order.next()) {
1233 if (!checkPhysRegInterference(VirtReg, PhysReg))
1234 return PhysReg;
1235 }
1272 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1273 return PhysReg;
12361274
12371275 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
12381276 return PhysReg;
6969 def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
7070 def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
7171 def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
72 // These require 32-bit instructions.
73 let CostPerUse = 1 in {
7274 def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
7375 def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
7476 def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
7779 def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>;
7880 def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>;
7981 def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>;
82 }
8083
8184 // Float registers
8285 def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">;
4545 def CL : Register<"cl">, DwarfRegNum<[2, 1, 1]>;
4646 def BL : Register<"bl">, DwarfRegNum<[3, 3, 3]>;
4747
48 // X86-64 only
48 // X86-64 only, requires REX.
49 let CostPerUse = 1 in {
4950 def SIL : Register<"sil">, DwarfRegNum<[4, 6, 6]>;
5051 def DIL : Register<"dil">, DwarfRegNum<[5, 7, 7]>;
5152 def BPL : Register<"bpl">, DwarfRegNum<[6, 4, 5]>;
5859 def R13B : Register<"r13b">, DwarfRegNum<[13, -2, -2]>;
5960 def R14B : Register<"r14b">, DwarfRegNum<[14, -2, -2]>;
6061 def R15B : Register<"r15b">, DwarfRegNum<[15, -2, -2]>;
62 }
6163
6264 // High registers. On x86-64, these cannot be used in any instruction
6365 // with a REX prefix.
8183 }
8284 def IP : Register<"ip">, DwarfRegNum<[16]>;
8385
84 // X86-64 only
85 let SubRegIndices = [sub_8bit] in {
86 // X86-64 only, requires REX.
87 let SubRegIndices = [sub_8bit], CostPerUse = 1 in {
8688 def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>;
8789 def R9W : RegisterWithSubRegs<"r9w", [R9B]>, DwarfRegNum<[9, -2, -2]>;
8890 def R10W : RegisterWithSubRegs<"r10w", [R10B]>, DwarfRegNum<[10, -2, -2]>;
104106 def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>;
105107 def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>;
106108
107 // X86-64 only
109 // X86-64 only, requires REX
110 let CostPerUse = 1 in {
108111 def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>;
109112 def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>;
110113 def R10D : RegisterWithSubRegs<"r10d", [R10W]>, DwarfRegNum<[10, -2, -2]>;
113116 def R13D : RegisterWithSubRegs<"r13d", [R13W]>, DwarfRegNum<[13, -2, -2]>;
114117 def R14D : RegisterWithSubRegs<"r14d", [R14W]>, DwarfRegNum<[14, -2, -2]>;
115118 def R15D : RegisterWithSubRegs<"r15d", [R15W]>, DwarfRegNum<[15, -2, -2]>;
116 }
119 }}
117120
118121 // 64-bit registers, X86-64 only
119122 let SubRegIndices = [sub_32bit] in {
126129 def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
127130 def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
128131
132 // These also require REX.
133 let CostPerUse = 1 in {
129134 def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
130135 def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
131136 def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
135140 def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
136141 def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
137142 def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
138 }
143 }}
139144
140145 // MMX Registers. These are actually aliased to ST0 .. ST7
141146 def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
169174 def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
170175
171176 // X86-64 only
177 let CostPerUse = 1 in {
172178 def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
173179 def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
174180 def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
177183 def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
178184 def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
179185 def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
180 }
186 }}
181187
182188 // YMM Registers, used by AVX instructions
183189 let SubRegIndices = [sub_xmm] in {
3030 const std::string &getName() const;
3131 unsigned DeclaredSpillSize, DeclaredSpillAlignment;
3232 unsigned EnumValue;
33 unsigned CostPerUse;
3334 CodeGenRegister(Record *R);
3435 };
3536
171171 CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
172172 DeclaredSpillSize = R->getValueAsInt("SpillSize");
173173 DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
174 CostPerUse = R->getValueAsInt("CostPerUse");
174175 }
175176
176177 const std::string &CodeGenRegister::getName() const {
840840 }
841841
842842 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
843 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
843 OS << " { \"NOREG\",\t0,\t0,\t0,\t0 },\n";
844844
845845 // Now that register alias and sub-registers sets have been emitted, emit the
846846 // register descriptors now.
853853 else
854854 OS << "Empty_SubRegsSet,\t";
855855 if (!RegisterSuperRegs[Reg.TheDef].empty())
856 OS << Reg.getName() << "_SuperRegsSet },\n";
856 OS << Reg.getName() << "_SuperRegsSet,\t";
857857 else
858 OS << "Empty_SuperRegsSet },\n";
858 OS << "Empty_SuperRegsSet,\t";
859 OS << Reg.CostPerUse << " },\n";
859860 }
860861 OS << " };\n"; // End of register descriptors...
861862