llvm.org GIT mirror llvm / 6bfa6d9
Remove the need to cache the subtarget in the AArch64 TargetRegisterInfo classes. Replace it with a cache to the Triple and use that where applicable at the moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232005 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 5 years ago
4 changed file(s) with 26 addition(s) and 21 deletion(s). Raw diff Collapse all Expand all
3030
3131 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
3232 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
33 RI(this, &STI), Subtarget(STI) {}
33 RI(STI.getTargetTriple()), Subtarget(STI) {}
3434
3535 /// GetInstSize - Return the number of bytes of code the specified
3636 /// instruction may be. This returns the maximum number of bytes.
1717 #include "AArch64Subtarget.h"
1818 #include "MCTargetDesc/AArch64AddressingModes.h"
1919 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/Triple.h"
2021 #include "llvm/CodeGen/MachineFrameInfo.h"
2122 #include "llvm/CodeGen/MachineInstrBuilder.h"
2223 #include "llvm/CodeGen/MachineRegisterInfo.h"
3637 ReserveX18("aarch64-reserve-x18", cl::Hidden,
3738 cl::desc("Reserve X18, making it unavailable as GPR"));
3839
39 AArch64RegisterInfo::AArch64RegisterInfo(const AArch64InstrInfo *tii,
40 const AArch64Subtarget *sti)
41 : AArch64GenRegisterInfo(AArch64::LR), TII(tii), STI(sti) {}
40 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
41 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {}
4242
4343 const MCPhysReg *
4444 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
6666 }
6767
6868 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
69 if (STI->isTargetDarwin())
69 if (TT.isOSDarwin())
7070 return CSR_AArch64_TLS_Darwin_RegMask;
7171
72 assert(STI->isTargetELF() && "only expect Darwin or ELF TLS");
72 assert(TT.isOSBinFormatELF() && "only expect Darwin or ELF TLS");
7373 return CSR_AArch64_TLS_ELF_RegMask;
7474 }
7575
9898 Reserved.set(AArch64::WSP);
9999 Reserved.set(AArch64::WZR);
100100
101 if (TFI->hasFP(MF) || STI->isTargetDarwin()) {
101 if (TFI->hasFP(MF) || TT.isOSDarwin()) {
102102 Reserved.set(AArch64::FP);
103103 Reserved.set(AArch64::W29);
104104 }
105105
106 if (STI->isTargetDarwin() || ReserveX18) {
106 if (TT.isOSDarwin() || ReserveX18) {
107107 Reserved.set(AArch64::X18); // Platform register
108108 Reserved.set(AArch64::W18);
109109 }
130130 return true;
131131 case AArch64::X18:
132132 case AArch64::W18:
133 return STI->isTargetDarwin() || ReserveX18;
133 return TT.isOSDarwin() || ReserveX18;
134134 case AArch64::FP:
135135 case AArch64::W29:
136 return TFI->hasFP(MF) || STI->isTargetDarwin();
136 return TFI->hasFP(MF) || TT.isOSDarwin();
137137 case AArch64::W19:
138138 case AArch64::X19:
139139 return hasBasePointer(MF);
303303 DebugLoc DL; // Defaults to "unknown"
304304 if (Ins != MBB->end())
305305 DL = Ins->getDebugLoc();
306
306 const MachineFunction &MF = *MBB->getParent();
307 const AArch64InstrInfo *TII =
308 MF.getSubtarget().getInstrInfo();
307309 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
308310 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
309 const MachineFunction &MF = *MBB->getParent();
310311 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
311312 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
312313
325326 ++i;
326327 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
327328 }
329 const MachineFunction *MF = MI.getParent()->getParent();
330 const AArch64InstrInfo *TII =
331 MF->getSubtarget().getInstrInfo();
328332 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
329333 assert(Done && "Unable to resolve frame index!");
330334 (void)Done;
338342 MachineInstr &MI = *II;
339343 MachineBasicBlock &MBB = *MI.getParent();
340344 MachineFunction &MF = *MBB.getParent();
345 const AArch64InstrInfo *TII =
346 MF.getSubtarget().getInstrInfo();
341347 const AArch64FrameLowering *TFI = static_cast(
342348 MF.getSubtarget().getFrameLowering());
343349
390396 case AArch64::GPR64RegClassID:
391397 case AArch64::GPR32commonRegClassID:
392398 case AArch64::GPR64commonRegClassID:
393 return 32 - 1 // XZR/SP
394 - (TFI->hasFP(MF) || STI->isTargetDarwin()) // FP
395 - (STI->isTargetDarwin() || ReserveX18) // X18 reserved as platform register
396 - hasBasePointer(MF); // X19
399 return 32 - 1 // XZR/SP
400 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
401 - (TT.isOSDarwin() || ReserveX18) // X18 reserved as platform register
402 - hasBasePointer(MF); // X19
397403 case AArch64::FPR8RegClassID:
398404 case AArch64::FPR16RegClassID:
399405 case AArch64::FPR32RegClassID:
1818
1919 namespace llvm {
2020
21 class AArch64InstrInfo;
22 class AArch64Subtarget;
2321 class MachineFunction;
2422 class RegScavenger;
2523 class TargetRegisterClass;
24 class Triple;
2625
2726 struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
2827 private:
29 const AArch64InstrInfo *TII;
30 const AArch64Subtarget *STI;
28 const Triple &TT;
3129
3230 public:
33 AArch64RegisterInfo(const AArch64InstrInfo *tii, const AArch64Subtarget *sti);
31 AArch64RegisterInfo(const Triple &TT);
3432
3533 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
3634
8585 const AArch64RegisterInfo *getRegisterInfo() const override {
8686 return &getInstrInfo()->getRegisterInfo();
8787 }
88 const Triple &getTargetTriple() const { return TargetTriple; }
8889 bool enableMachineScheduler() const override { return true; }
8990 bool enablePostMachineScheduler() const override {
9091 return isCortexA53() || isCortexA57();