llvm.org GIT mirror llvm / 6b6dfa5
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200626 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 6 years ago
15 changed file(s) with 569 addition(s) and 576 deletion(s). Raw diff Collapse all Expand all
309309 //===------------------------------------------------------------------===//
310310 // Actual flags...
311311
312 // OpSize - Set if this instruction requires an operand size prefix (0x66),
313 // which most often indicates that the instruction operates on 16 bit data
314 // instead of 32 bit data. OpSize16 in 16 bit mode indicates that the
315 // instruction operates on 32 bit data instead of 16 bit data.
316 OpSize = 1 << 6,
317 OpSize16 = 1 << 7,
312 // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
313 // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
314 // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
315 // prefix in 16-bit mode.
316 OpSizeShift = 6,
317 OpSizeMask = 0x3 << OpSizeShift,
318
319 OpSize16 = 1,
320 OpSize32 = 2,
318321
319322 // AsSize - Set if this instruction requires an operand size prefix (0x67),
320323 // which most often indicates that the instruction address 16 bit address
11181118 raw_ostream &OS) const {
11191119
11201120 // Emit the operand size opcode prefix as needed.
1121 if (TSFlags & (is16BitMode(STI) ? X86II::OpSize16 : X86II::OpSize))
1121 unsigned char OpSize = (TSFlags & X86II::OpSizeMask) >> X86II::OpSizeShift;
1122 if (OpSize == (is16BitMode(STI) ? X86II::OpSize32 : X86II::OpSize16))
11221123 EmitByte(0x66, CurByte, OS);
11231124
11241125 switch (TSFlags & X86II::OpPrefixMask) {
12761277 // Emit segment override opcode prefix as needed (not for %ds).
12771278 if (MI.getOperand(2).getReg() != X86::DS)
12781279 EmitSegmentOverridePrefix(CurByte, 2, MI, OS);
1279 // Emit OpSize prefix as needed.
1280 // Emit AdSize prefix as needed.
12801281 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
12811282 (is32BitMode(STI) && siReg == X86::SI))
12821283 EmitByte(0x67, CurByte, OS);
12891290 // Emit segment override opcode prefix as needed (not for %ds).
12901291 if (MI.getOperand(1).getReg() != X86::DS)
12911292 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1292 // Emit OpSize prefix as needed.
1293 // Emit AdSize prefix as needed.
12931294 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
12941295 (is32BitMode(STI) && siReg == X86::SI))
12951296 EmitByte(0x67, CurByte, OS);
12991300 }
13001301 case X86II::RawFrmDst: {
13011302 unsigned siReg = MI.getOperand(0).getReg();
1302 // Emit OpSize prefix as needed.
1303 // Emit AdSize prefix as needed.
13031304 if ((!is32BitMode(STI) && siReg == X86::EDI) ||
13041305 (is32BitMode(STI) && siReg == X86::DI))
13051306 EmitByte(0x67, CurByte, OS);
654654 const MachineInstr &MI,
655655 const MCInstrDesc *Desc) const {
656656 // Emit the operand size opcode prefix as needed.
657 if (TSFlags & X86II::OpSize)
657 if (((TSFlags & X86II::OpSizeMask) >> X86II::OpSizeShift) == X86II::OpSize16)
658658 MCE.emitByte(0x66);
659659
660660 switch (Desc->TSFlags & X86II::OpPrefixMask) {
1717 let neverHasSideEffects = 1 in
1818 def LEA16r : I<0x8D, MRMSrcMem,
1919 (outs GR16:$dst), (ins i32mem:$src),
20 "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize;
20 "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize16;
2121 let isReMaterializable = 1 in
2222 def LEA32r : I<0x8D, MRMSrcMem,
2323 (outs GR32:$dst), (ins i32mem:$src),
2424 "lea{l}\t{$src|$dst}, {$dst|$src}",
2525 [(set GR32:$dst, lea32addr:$src)], IIC_LEA>,
26 OpSize16, Requires<[Not64BitMode]>;
26 OpSize32, Requires<[Not64BitMode]>;
2727
2828 def LEA64_32r : I<0x8D, MRMSrcMem,
2929 (outs GR32:$dst), (ins lea64_32mem:$src),
3030 "lea{l}\t{$src|$dst}, {$dst|$src}",
3131 [(set GR32:$dst, lea64_32addr:$src)], IIC_LEA>,
32 OpSize16, Requires<[In64BitMode]>;
32 OpSize32, Requires<[In64BitMode]>;
3333
3434 let isReMaterializable = 1 in
3535 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
6767 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
6868 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
6969 "mul{w}\t$src",
70 [], IIC_MUL16_REG>, OpSize, Sched<[WriteIMul]>;
70 [], IIC_MUL16_REG>, OpSize16, Sched<[WriteIMul]>;
7171 // EAX,EDX = EAX*GR32
7272 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
7373 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
7474 "mul{l}\t$src",
7575 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/],
76 IIC_MUL32_REG>, OpSize16, Sched<[WriteIMul]>;
76 IIC_MUL32_REG>, OpSize32, Sched<[WriteIMul]>;
7777 // RAX,RDX = RAX*GR64
7878 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
7979 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
9494 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
9595 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
9696 "mul{w}\t$src",
97 [], IIC_MUL16_MEM>, OpSize, SchedLoadReg;
97 [], IIC_MUL16_MEM>, OpSize16, SchedLoadReg;
9898 // EAX,EDX = EAX*[mem32]
9999 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
100100 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
101101 "mul{l}\t$src",
102 [], IIC_MUL32_MEM>, OpSize16, SchedLoadReg;
102 [], IIC_MUL32_MEM>, OpSize32, SchedLoadReg;
103103 // RAX,RDX = RAX*[mem64]
104104 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
105105 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
114114 // AX,DX = AX*GR16
115115 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
116116 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", [],
117 IIC_IMUL16_RR>, OpSize, Sched<[WriteIMul]>;
117 IIC_IMUL16_RR>, OpSize16, Sched<[WriteIMul]>;
118118 // EAX,EDX = EAX*GR32
119119 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
120120 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [],
121 IIC_IMUL32_RR>, OpSize16, Sched<[WriteIMul]>;
121 IIC_IMUL32_RR>, OpSize32, Sched<[WriteIMul]>;
122122 // RAX,RDX = RAX*GR64
123123 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
124124 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [],
132132 // AX,DX = AX*[mem16]
133133 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
134134 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
135 "imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize,
135 "imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize16,
136136 SchedLoadReg;
137137 // EAX,EDX = EAX*[mem32]
138138 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
139139 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
140 "imul{l}\t$src", [], IIC_IMUL32_MEM>, OpSize16,
140 "imul{l}\t$src", [], IIC_IMUL32_MEM>, OpSize32,
141141 SchedLoadReg;
142142 // RAX,RDX = RAX*[mem64]
143143 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
157157 "imul{w}\t{$src2, $dst|$dst, $src2}",
158158 [(set GR16:$dst, EFLAGS,
159159 (X86smul_flag GR16:$src1, GR16:$src2))], IIC_IMUL16_RR>,
160 TB, OpSize;
160 TB, OpSize16;
161161 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
162162 "imul{l}\t{$src2, $dst|$dst, $src2}",
163163 [(set GR32:$dst, EFLAGS,
164164 (X86smul_flag GR32:$src1, GR32:$src2))], IIC_IMUL32_RR>,
165 TB, OpSize16;
165 TB, OpSize32;
166166 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
167167 (ins GR64:$src1, GR64:$src2),
168168 "imul{q}\t{$src2, $dst|$dst, $src2}",
179179 [(set GR16:$dst, EFLAGS,
180180 (X86smul_flag GR16:$src1, (load addr:$src2)))],
181181 IIC_IMUL16_RM>,
182 TB, OpSize;
182 TB, OpSize16;
183183 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
184184 (ins GR32:$src1, i32mem:$src2),
185185 "imul{l}\t{$src2, $dst|$dst, $src2}",
186186 [(set GR32:$dst, EFLAGS,
187187 (X86smul_flag GR32:$src1, (load addr:$src2)))],
188188 IIC_IMUL32_RM>,
189 TB, OpSize16;
189 TB, OpSize32;
190190 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
191191 (ins GR64:$src1, i64mem:$src2),
192192 "imul{q}\t{$src2, $dst|$dst, $src2}",
208208 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
209209 [(set GR16:$dst, EFLAGS,
210210 (X86smul_flag GR16:$src1, imm:$src2))],
211 IIC_IMUL16_RRI>, OpSize;
211 IIC_IMUL16_RRI>, OpSize16;
212212 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
213213 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
214214 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
215215 [(set GR16:$dst, EFLAGS,
216216 (X86smul_flag GR16:$src1, i16immSExt8:$src2))],
217 IIC_IMUL16_RRI>,
218 OpSize;
217 IIC_IMUL16_RRI>, OpSize16;
219218 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
220219 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
221220 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
222221 [(set GR32:$dst, EFLAGS,
223222 (X86smul_flag GR32:$src1, imm:$src2))],
224 IIC_IMUL32_RRI>, OpSize16;
223 IIC_IMUL32_RRI>, OpSize32;
225224 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
226225 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
227226 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228227 [(set GR32:$dst, EFLAGS,
229228 (X86smul_flag GR32:$src1, i32immSExt8:$src2))],
230 IIC_IMUL32_RRI>, OpSize16;
229 IIC_IMUL32_RRI>, OpSize32;
231230 def IMUL64rri32 : RIi32S<0x69, MRMSrcReg, // GR64 = GR64*I32
232231 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
233232 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
250249 [(set GR16:$dst, EFLAGS,
251250 (X86smul_flag (load addr:$src1), imm:$src2))],
252251 IIC_IMUL16_RMI>,
253 OpSize;
252 OpSize16;
254253 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
255254 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
256255 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
257256 [(set GR16:$dst, EFLAGS,
258257 (X86smul_flag (load addr:$src1),
259258 i16immSExt8:$src2))], IIC_IMUL16_RMI>,
260 OpSize;
259 OpSize16;
261260 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
262261 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
263262 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
264263 [(set GR32:$dst, EFLAGS,
265264 (X86smul_flag (load addr:$src1), imm:$src2))],
266 IIC_IMUL32_RMI>, OpSize16;
265 IIC_IMUL32_RMI>, OpSize32;
267266 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
268267 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
269268 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
270269 [(set GR32:$dst, EFLAGS,
271270 (X86smul_flag (load addr:$src1),
272271 i32immSExt8:$src2))],
273 IIC_IMUL32_RMI>, OpSize16;
272 IIC_IMUL32_RMI>, OpSize32;
274273 def IMUL64rmi32 : RIi32S<0x69, MRMSrcMem, // GR64 = [mem64]*I32
275274 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
276275 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
299298 "div{b}\t$src", [], IIC_DIV8_REG>;
300299 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
301300 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
302 "div{w}\t$src", [], IIC_DIV16>, OpSize;
301 "div{w}\t$src", [], IIC_DIV16>, OpSize16;
303302 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
304303 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
305 "div{l}\t$src", [], IIC_DIV32>, OpSize16;
304 "div{l}\t$src", [], IIC_DIV32>, OpSize32;
306305 // RDX:RAX/r64 = RAX,RDX
307306 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
308307 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
316315 SchedLoadReg;
317316 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
318317 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
319 "div{w}\t$src", [], IIC_DIV16>, OpSize,
318 "div{w}\t$src", [], IIC_DIV16>, OpSize16,
320319 SchedLoadReg;
321320 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
322321 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
323322 "div{l}\t$src", [], IIC_DIV32>,
324 SchedLoadReg, OpSize16;
323 SchedLoadReg, OpSize32;
325324 // RDX:RAX/[mem64] = RAX,RDX
326325 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
327326 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
336335 "idiv{b}\t$src", [], IIC_IDIV8>;
337336 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
338337 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
339 "idiv{w}\t$src", [], IIC_IDIV16>, OpSize;
338 "idiv{w}\t$src", [], IIC_IDIV16>, OpSize16;
340339 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
341340 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
342 "idiv{l}\t$src", [], IIC_IDIV32>, OpSize16;
341 "idiv{l}\t$src", [], IIC_IDIV32>, OpSize32;
343342 // RDX:RAX/r64 = RAX,RDX
344343 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
345344 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
353352 SchedLoadReg;
354353 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
355354 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
356 "idiv{w}\t$src", [], IIC_IDIV16>, OpSize,
355 "idiv{w}\t$src", [], IIC_IDIV16>, OpSize16,
357356 SchedLoadReg;
358357 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
359358 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
360 "idiv{l}\t$src", [], IIC_IDIV32>, OpSize16,
359 "idiv{l}\t$src", [], IIC_IDIV32>, OpSize32,
361360 SchedLoadReg;
362361 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
363362 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
381380 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
382381 "neg{w}\t$dst",
383382 [(set GR16:$dst, (ineg GR16:$src1)),
384 (implicit EFLAGS)], IIC_UNARY_REG>, OpSize;
383 (implicit EFLAGS)], IIC_UNARY_REG>, OpSize16;
385384 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
386385 "neg{l}\t$dst",
387386 [(set GR32:$dst, (ineg GR32:$src1)),
388 (implicit EFLAGS)], IIC_UNARY_REG>, OpSize16;
387 (implicit EFLAGS)], IIC_UNARY_REG>, OpSize32;
389388 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
390389 [(set GR64:$dst, (ineg GR64:$src1)),
391390 (implicit EFLAGS)], IIC_UNARY_REG>;
400399 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
401400 "neg{w}\t$dst",
402401 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
403 (implicit EFLAGS)], IIC_UNARY_MEM>, OpSize;
402 (implicit EFLAGS)], IIC_UNARY_MEM>, OpSize16;
404403 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
405404 "neg{l}\t$dst",
406405 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
407 (implicit EFLAGS)], IIC_UNARY_MEM>, OpSize16;
406 (implicit EFLAGS)], IIC_UNARY_MEM>, OpSize32;
408407 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
409408 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
410409 (implicit EFLAGS)], IIC_UNARY_MEM>;
422421 [(set GR8:$dst, (not GR8:$src1))], IIC_UNARY_REG>;
423422 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
424423 "not{w}\t$dst",
425 [(set GR16:$dst, (not GR16:$src1))], IIC_UNARY_REG>, OpSize;
424 [(set GR16:$dst, (not GR16:$src1))], IIC_UNARY_REG>, OpSize16;
426425 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
427426 "not{l}\t$dst",
428 [(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>, OpSize16;
427 [(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>, OpSize32;
429428 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
430429 [(set GR64:$dst, (not GR64:$src1))], IIC_UNARY_REG>;
431430 }
438437 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
439438 "not{w}\t$dst",
440439 [(store (not (loadi16 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>,
441 OpSize;
440 OpSize16;
442441 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
443442 "not{l}\t$dst",
444443 [(store (not (loadi32 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>,
445 OpSize16;
444 OpSize32;
446445 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
447446 [(store (not (loadi64 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
448447 } // SchedRW
461460 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
462461 "inc{w}\t$dst",
463462 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))], IIC_UNARY_REG>,
464 OpSize, Requires<[Not64BitMode]>;
463 OpSize16, Requires<[Not64BitMode]>;
465464 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
466465 "inc{l}\t$dst",
467466 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
468467 IIC_UNARY_REG>,
469 OpSize16, Requires<[Not64BitMode]>;
468 OpSize32, Requires<[Not64BitMode]>;
470469 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
471470 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))],
472471 IIC_UNARY_REG>;
480479 "inc{w}\t$dst",
481480 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))],
482481 IIC_UNARY_REG>,
483 OpSize, Requires<[In64BitMode]>;
482 OpSize16, Requires<[In64BitMode]>;
484483 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
485484 "inc{l}\t$dst",
486485 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
487486 IIC_UNARY_REG>,
488 OpSize16, Requires<[In64BitMode]>;
487 OpSize32, Requires<[In64BitMode]>;
489488 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
490489 "dec{w}\t$dst",
491490 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
492491 IIC_UNARY_REG>,
493 OpSize, Requires<[In64BitMode]>;
492 OpSize16, Requires<[In64BitMode]>;
494493 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
495494 "dec{l}\t$dst",
496495 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
497496 IIC_UNARY_REG>,
498 OpSize16, Requires<[In64BitMode]>;
497 OpSize32, Requires<[In64BitMode]>;
499498 } // isConvertibleToThreeAddress = 1, CodeSize = 2
500499
501500 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
502501 CodeSize = 2 in {
503502 def INC32_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
504503 "inc{w}\t$dst", [], IIC_UNARY_REG>,
505 OpSize, Requires<[Not64BitMode]>;
504 OpSize16, Requires<[Not64BitMode]>;
506505 def INC32_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
507506 "inc{l}\t$dst", [], IIC_UNARY_REG>,
508 OpSize16, Requires<[Not64BitMode]>;
507 OpSize32, Requires<[Not64BitMode]>;
509508 def DEC32_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
510509 "dec{w}\t$dst", [], IIC_UNARY_REG>,
511 OpSize, Requires<[Not64BitMode]>;
510 OpSize16, Requires<[Not64BitMode]>;
512511 def DEC32_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
513512 "dec{l}\t$dst", [], IIC_UNARY_REG>,
514 OpSize16, Requires<[Not64BitMode]>;
513 OpSize32, Requires<[Not64BitMode]>;
515514 } // isCodeGenOnly = 1, ForceDisassemble = 1, HasSideEffects = 0, CodeSize = 2
516515
517516 } // Constraints = "$src1 = $dst", SchedRW
523522 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
524523 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
525524 (implicit EFLAGS)], IIC_UNARY_MEM>,
526 OpSize, Requires<[Not64BitMode]>;
525 OpSize16, Requires<[Not64BitMode]>;
527526 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
528527 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
529528 (implicit EFLAGS)], IIC_UNARY_MEM>,
530 OpSize16, Requires<[Not64BitMode]>;
529 OpSize32, Requires<[Not64BitMode]>;
531530 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
532531 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
533532 (implicit EFLAGS)], IIC_UNARY_MEM>;
538537 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
539538 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
540539 (implicit EFLAGS)], IIC_UNARY_MEM>,
541 OpSize, Requires<[In64BitMode]>;
540 OpSize16, Requires<[In64BitMode]>;
542541 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
543542 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
544543 (implicit EFLAGS)], IIC_UNARY_MEM>,
545 OpSize16, Requires<[In64BitMode]>;
544 OpSize32, Requires<[In64BitMode]>;
546545 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
547546 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
548547 (implicit EFLAGS)], IIC_UNARY_MEM>,
549 OpSize, Requires<[In64BitMode]>;
548 OpSize16, Requires<[In64BitMode]>;
550549 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
551550 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
552551 (implicit EFLAGS)], IIC_UNARY_MEM>,
553 OpSize16, Requires<[In64BitMode]>;
552 OpSize32, Requires<[In64BitMode]>;
554553 } // CodeSize = 2, SchedRW
555554
556555 let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
564563 "dec{w}\t$dst",
565564 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
566565 IIC_UNARY_REG>,
567 OpSize, Requires<[Not64BitMode]>;
566 OpSize16, Requires<[Not64BitMode]>;
568567 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
569568 "dec{l}\t$dst",
570569 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
571570 IIC_UNARY_REG>,
572 OpSize16, Requires<[Not64BitMode]>;
571 OpSize32, Requires<[Not64BitMode]>;
573572 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
574573 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))],
575574 IIC_UNARY_REG>;
584583 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
585584 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
586585 (implicit EFLAGS)], IIC_UNARY_MEM>,
587 OpSize, Requires<[Not64BitMode]>;
586 OpSize16, Requires<[Not64BitMode]>;
588587 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
589588 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
590589 (implicit EFLAGS)], IIC_UNARY_MEM>,
591 OpSize16, Requires<[Not64BitMode]>;
590 OpSize32, Requires<[Not64BitMode]>;
592591 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
593592 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
594593 (implicit EFLAGS)], IIC_UNARY_MEM>;
602601 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
603602 Operand immoperand, SDPatternOperator immoperator,
604603 Operand imm8operand, SDPatternOperator imm8operator,
605 bit hasOddOpcode, bit hasOpSizePrefix, bit hasOpSize16Prefix,
604 bit hasOddOpcode, OperandSize opSize,
606605 bit hasREX_WPrefix> {
607606 /// VT - This is the value type itself.
608607 ValueType VT = vt;
653652 /// other datatypes are odd.
654653 bit HasOddOpcode = hasOddOpcode;
655654
656 /// HasOpSizePrefix - This bit is set to true if the instruction should have
657 /// the 0x66 operand size prefix in 32-bit or 64-bit modes. This is set for
658 /// i16 types.
659 bit HasOpSizePrefix = hasOpSizePrefix;
660
661 /// HasOpSizePrefix - This bit is set to true if the instruction should have
662 /// the 0x66 operand size prefix in 16-bit mode. This is set for i32 types.
663 bit HasOpSize16Prefix = hasOpSize16Prefix;
655 /// OpSize - Selects whether the instruction needs a 0x66 prefix based on
656 /// 16-bit vs 32-bit mode. i8/i64 set this to OpSizeFixed. i16 sets this
657 /// to Opsize16. i32 sets this to OpSize32.
658 OperandSize OpSize = opSize;
664659
665660 /// HasREX_WPrefix - This bit is set to true if the instruction should have
666661 /// the 0x40 REX prefix. This is set for i64 types.
672667
673668 def Xi8 : X86TypeInfo
674669 Imm8 , i8imm , imm, i8imm , invalid_node,
675 0, 0, 0, 0>;
670 0, OpSizeFixed, 0>;
676671 def Xi16 : X86TypeInfo
677672 Imm16, i16imm, imm, i16i8imm, i16immSExt8,
678 1, 1, 0, 0>;
673 1, OpSize16, 0>;
679674 def Xi32 : X86TypeInfo
680675 Imm32, i32imm, imm, i32i8imm, i32immSExt8,
681 1, 0, 1, 0>;
676 1, OpSize32, 0>;
682677 def Xi64 : X86TypeInfo
683678 Imm32S, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8,
684 1, 0, 0, 1>;
679 1, OpSizeFixed, 1>;
685680
686681 /// ITy - This instruction base class takes the type info for the instruction.
687682 /// Using this, it:
701696 itin> {
702697
703698 // Infer instruction prefixes from type info.
704 let hasOpSizePrefix = typeinfo.HasOpSizePrefix;
705 let hasOpSize16Prefix = typeinfo.HasOpSize16Prefix;
699 let OpSize = typeinfo.OpSize;
706700 let hasREX_WPrefix = typeinfo.HasREX_WPrefix;
707701 }
708702
2121 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
2222 [(set GR16:$dst,
2323 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))],
24 IIC_CMOV16_RR>,TB,OpSize;
24 IIC_CMOV16_RR>, TB, OpSize16;
2525 def NAME#32rr
2626 : I
2727 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
2828 [(set GR32:$dst,
2929 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
30 IIC_CMOV32_RR>, TB, OpSize16;
30 IIC_CMOV32_RR>, TB, OpSize32;
3131 def NAME#64rr
3232 :RI
3333 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
4343 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
4444 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
4545 CondNode, EFLAGS))], IIC_CMOV16_RM>,
46 TB, OpSize;
46 TB, OpSize16;
4747 def NAME#32rm
4848 : I
4949 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
5050 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
5151 CondNode, EFLAGS))], IIC_CMOV32_RM>,
52 TB, OpSize16;
52 TB, OpSize32;
5353 def NAME#64rm
5454 :RI
5555 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
319319 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
320320 Requires<[Not64BitMode]>;
321321 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
322 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
322 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
323323 Requires<[Not64BitMode]>;
324324 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
325 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize16,
325 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
326326 Requires<[Not64BitMode]>;
327327 }
328328
331331 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
332332 Requires<[In64BitMode]>;
333333 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
334 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
334 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
335335 Requires<[In64BitMode]>;
336336 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
337 [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
337 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
338338 Requires<[In64BitMode]>;
339339 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
340340 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
349349 Requires<[Not64BitMode]>;
350350 let Uses = [AX,ECX,EDI] in
351351 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
352 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
352 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
353353 Requires<[Not64BitMode]>;
354354 let Uses = [EAX,ECX,EDI] in
355355 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
356 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize16,
356 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
357357 Requires<[Not64BitMode]>;
358358 }
359359
364364 Requires<[In64BitMode]>;
365365 let Uses = [AX,RCX,RDI] in
366366 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
367 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
367 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
368368 Requires<[In64BitMode]>;
369369 let Uses = [RAX,RCX,RDI] in
370370 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
371 [(X86rep_stos i32)], IIC_REP_STOS>, REP,
371 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
372372 Requires<[In64BitMode]>;
373373
374374 let Uses = [RAX,RCX,RDI] in
617617 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
618618 !strconcat(mnemonic, "{w}\t",
619619 "{$src2, $dst|$dst, $src2}"),
620 [], IIC_ALU_NONMEM>, OpSize, LOCK;
620 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
621621 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
622622 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
623623 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
624624 !strconcat(mnemonic, "{l}\t",
625625 "{$src2, $dst|$dst, $src2}"),
626 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
626 [], IIC_ALU_NONMEM>, OpSize32, LOCK;
627627 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
628628 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
629629 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
643643 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
644644 !strconcat(mnemonic, "{w}\t",
645645 "{$src2, $dst|$dst, $src2}"),
646 [], IIC_ALU_MEM>, OpSize, LOCK;
646 [], IIC_ALU_MEM>, OpSize16, LOCK;
647647
648648 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
649649 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
650650 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
651651 !strconcat(mnemonic, "{l}\t",
652652 "{$src2, $dst|$dst, $src2}"),
653 [], IIC_ALU_MEM>, OpSize16, LOCK;
653 [], IIC_ALU_MEM>, OpSize32, LOCK;
654654
655655 def NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
656656 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
664664 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
665665 !strconcat(mnemonic, "{w}\t",
666666 "{$src2, $dst|$dst, $src2}"),
667 [], IIC_ALU_MEM>, OpSize, LOCK;
667 [], IIC_ALU_MEM>, OpSize16, LOCK;
668668 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
669669 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
670670 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
671671 !strconcat(mnemonic, "{l}\t",
672672 "{$src2, $dst|$dst, $src2}"),
673 [], IIC_ALU_MEM>, OpSize16, LOCK;
673 [], IIC_ALU_MEM>, OpSize32, LOCK;
674674 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
675675 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
676676 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
699699 [], IIC_UNARY_MEM>, LOCK;
700700 def NAME#16m : I
701701 !strconcat(mnemonic, "{w}\t$dst"),
702 [], IIC_UNARY_MEM>, OpSize, LOCK;
702 [], IIC_UNARY_MEM>, OpSize16, LOCK;
703703 def NAME#32m : I
704704 !strconcat(mnemonic, "{l}\t$dst"),
705 [], IIC_UNARY_MEM>, OpSize16, LOCK;
705 [], IIC_UNARY_MEM>, OpSize32, LOCK;
706706 def NAME#64m : RI
707707 !strconcat(mnemonic, "{q}\t$dst"),
708708 [], IIC_UNARY_MEM>, LOCK;
734734 let Defs = [AX, EFLAGS], Uses = [AX] in
735735 def NAME#16 : I
736736 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
737 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize, LOCK;
737 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
738738 let Defs = [EAX, EFLAGS], Uses = [EAX] in
739739 def NAME#32 : I
740740 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
741 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize16, LOCK;
741 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
742742 let Defs = [RAX, EFLAGS], Uses = [RAX] in
743743 def NAME#64 : RI
744744 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
781781 [(set
782782 GR16:$dst,
783783 (!cast(frag # "_16") addr:$ptr, GR16:$val))],
784 itin>, OpSize;
784 itin>, OpSize16;
785785 def NAME#32 : I
786786 (ins GR32:$val, i32mem:$ptr),
787787 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
788788 [(set
789789 GR32:$dst,
790790 (!cast(frag # "_32") addr:$ptr, GR32:$val))],
791 itin>, OpSize16;
791 itin>, OpSize32;
792792 def NAME#64 : RI
793793 (ins GR64:$val, i64mem:$ptr),
794794 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
2222 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
2323 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
2424 "ret{l}",
25 [(X86retflag 0)], IIC_RET>, OpSize16, Requires<[Not64BitMode]>;
25 [(X86retflag 0)], IIC_RET>, OpSize32, Requires<[Not64BitMode]>;
2626 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
2727 "ret{q}",
2828 [(X86retflag 0)], IIC_RET>, Requires<[In64BitMode]>;
2929 def RETW : I <0xC3, RawFrm, (outs), (ins),
3030 "ret{w}",
31 [], IIC_RET>, OpSize;
31 [], IIC_RET>, OpSize16;
3232 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
3333 "ret{l}\t$amt",
34 [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize16,
34 [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize32,
3535 Requires<[Not64BitMode]>;
3636 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
3737 "ret{q}\t$amt",
3939 Requires<[In64BitMode]>;
4040 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
4141 "ret{w}\t$amt",
42 [], IIC_RET_IMM>, OpSize;
42 [], IIC_RET_IMM>, OpSize16;
4343 def LRETL : I <0xCB, RawFrm, (outs), (ins),
44 "{l}ret{l|f}", [], IIC_RET>, OpSize16;
44 "{l}ret{l|f}", [], IIC_RET>, OpSize32;
4545 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
4646 "{l}ret{|f}q", [], IIC_RET>, Requires<[In64BitMode]>;
4747 def LRETW : I <0xCB, RawFrm, (outs), (ins),
48 "{l}ret{w|f}", [], IIC_RET>, OpSize;
48 "{l}ret{w|f}", [], IIC_RET>, OpSize16;
4949 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
50 "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize16;
50 "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize32;
5151 def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
5252 "{l}ret{|f}q\t$amt", [], IIC_RET>, Requires<[In64BitMode]>;
5353 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
54 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize;
54 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize16;
5555 }
5656
5757 // Unconditional branches.
5858 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
5959 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
60 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize16;
60 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize32;
6161 def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
62 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize,
62 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize16,
6363 Requires<[In16BitMode]>;
6464 let hasSideEffects = 0 in
6565 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
7373 def _1 : Ii8PCRel
7474 IIC_Jcc>;
7575 def _2 : Ii16PCRel
76 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, OpSize,
76 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, OpSize16,
7777 TB, Requires<[In16BitMode]>;
7878 def _4 : Ii32PCRel
7979 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB,
80 OpSize16;
80 OpSize32;
8181 }
8282 }
8383
125125 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
126126 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
127127 [(brind GR16:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
128 OpSize, Sched<[WriteJump]>;
128 OpSize16, Sched<[WriteJump]>;
129129 def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst",
130130 [(brind (loadi16 addr:$dst))], IIC_JMP_MEM>,
131 Requires<[Not64BitMode]>, OpSize, Sched<[WriteJumpLd]>;
131 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;
132132
133133 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
134134 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
135 OpSize16, Sched<[WriteJump]>;
135 OpSize32, Sched<[WriteJump]>;
136136 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
137137 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>,
138 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;
138 Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>;
139139
140140 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
141141 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>,
147147 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
148148 (ins i16imm:$off, i16imm:$seg),
149149 "ljmp{w}\t{$seg, $off|$off, $seg}", [],
150 IIC_JMP_FAR_PTR>, OpSize, Sched<[WriteJump]>;
150 IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
151151 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
152152 (ins i32imm:$off, i16imm:$seg),
153153 "ljmp{l}\t{$seg, $off|$off, $seg}", [],
154 IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
154 IIC_JMP_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
155155 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
156156 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
157157 Sched<[WriteJump]>;
158158
159159 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
160 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize,
160 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16,
161161 Sched<[WriteJumpLd]>;
162162 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
163 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16,
163 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize32,
164164 Sched<[WriteJumpLd]>;
165165 }
166166
183183 let Uses = [ESP] in {
184184 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
185185 (outs), (ins i32imm_pcrel:$dst),
186 "call{l}\t$dst", [], IIC_CALL_RI>, OpSize16,
186 "call{l}\t$dst", [], IIC_CALL_RI>, OpSize32,
187187 Requires<[Not64BitMode]>, Sched<[WriteJump]>;
188188 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
189189 (outs), (ins i16imm_pcrel:$dst),
190 "call{w}\t$dst", [], IIC_CALL_RI>, OpSize,
190 "call{w}\t$dst", [], IIC_CALL_RI>, OpSize16,
191191 Sched<[WriteJump]>;
192192 def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
193193 "call{w}\t{*}$dst", [(X86call GR16:$dst)], IIC_CALL_RI>,
194 OpSize, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
194 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
195195 def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst),
196196 "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))],
197 IIC_CALL_MEM>, OpSize,
197 IIC_CALL_MEM>, OpSize16,
198198 Requires<[Not64BitMode,FavorMemIndirectCall]>,
199199 Sched<[WriteJumpLd]>;
200200 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
201201 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
202 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
202 OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
203203 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
204204 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
205 IIC_CALL_MEM>, OpSize16,
205 IIC_CALL_MEM>, OpSize32,
206206 Requires<[Not64BitMode,FavorMemIndirectCall]>,
207207 Sched<[WriteJumpLd]>;
208208
209209 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
210210 (ins i16imm:$off, i16imm:$seg),
211211 "lcall{w}\t{$seg, $off|$off, $seg}", [],
212 IIC_CALL_FAR_PTR>, OpSize, Sched<[WriteJump]>;
212 IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
213213 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
214214 (ins i32imm:$off, i16imm:$seg),
215215 "lcall{l}\t{$seg, $off|$off, $seg}", [],
216 IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
216 IIC_CALL_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
217217
218218 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
219 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize,
219 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16,
220220 Sched<[WriteJumpLd]>;
221221 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
222 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16,
222 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize32,
223223 Sched<[WriteJumpLd]>;
224224 }
225225
1313 let neverHasSideEffects = 1 in {
1414 let Defs = [AX], Uses = [AL] in
1515 def CBW : I<0x98, RawFrm, (outs), (ins),
16 "{cbtw|cbw}", [], IIC_CBW>, OpSize; // AX = signext(AL)
16 "{cbtw|cbw}", [], IIC_CBW>, OpSize16; // AX = signext(AL)
1717 let Defs = [EAX], Uses = [AX] in
1818 def CWDE : I<0x98, RawFrm, (outs), (ins),
19 "{cwtl|cwde}", [], IIC_CBW>, OpSize16; // EAX = signext(AX)
19 "{cwtl|cwde}", [], IIC_CBW>, OpSize32; // EAX = signext(AX)
2020
2121 let Defs = [AX,DX], Uses = [AX] in
2222 def CWD : I<0x99, RawFrm, (outs), (ins),
23 "{cwtd|cwd}", [], IIC_CBW>, OpSize; // DX:AX = signext(AX)
23 "{cwtd|cwd}", [], IIC_CBW>, OpSize16; // DX:AX = signext(AX)
2424 let Defs = [EAX,EDX], Uses = [EAX] in
2525 def CDQ : I<0x99, RawFrm, (outs), (ins),
26 "{cltd|cdq}", [], IIC_CBW>, OpSize16; // EDX:EAX = signext(EAX)
26 "{cltd|cdq}", [], IIC_CBW>, OpSize32; // EDX:EAX = signext(EAX)
2727
2828
2929 let Defs = [RAX], Uses = [EAX] in
4141 let neverHasSideEffects = 1 in {
4242 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
4343 "movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_R8>,
44 TB, OpSize, Sched<[WriteALU]>;
44 TB, OpSize16, Sched<[WriteALU]>;
4545 let mayLoad = 1 in
4646 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
4747 "movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_M8>,
48 TB, OpSize, Sched<[WriteALULd]>;
48 TB, OpSize16, Sched<[WriteALULd]>;
4949 } // neverHasSideEffects = 1
5050 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
5151 "movs{bl|x}\t{$src, $dst|$dst, $src}",
5252 [(set GR32:$dst, (sext GR8:$src))], IIC_MOVSX>, TB,
53 OpSize16, Sched<[WriteALU]>;
53 OpSize32, Sched<[WriteALU]>;
5454 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
5555 "movs{bl|x}\t{$src, $dst|$dst, $src}",
5656 [(set GR32:$dst, (sextloadi32i8 addr:$src))], IIC_MOVSX>, TB,
57 OpSize16, Sched<[WriteALULd]>;
57 OpSize32, Sched<[WriteALULd]>;
5858 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
5959 "movs{wl|x}\t{$src, $dst|$dst, $src}",
6060 [(set GR32:$dst, (sext GR16:$src))], IIC_MOVSX>, TB,
61 OpSize16, Sched<[WriteALU]>;
61 OpSize32, Sched<[WriteALU]>;
6262 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
6363 "movs{wl|x}\t{$src, $dst|$dst, $src}",
6464 [(set GR32:$dst, (sextloadi32i16 addr:$src))], IIC_MOVSX>,
65 OpSize16, TB, Sched<[WriteALULd]>;
65 OpSize32, TB, Sched<[WriteALULd]>;
6666
6767 let neverHasSideEffects = 1 in {
6868 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
6969 "movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_R8>,
70 TB, OpSize, Sched<[WriteALU]>;
70 TB, OpSize16, Sched<[WriteALU]>;
7171 let mayLoad = 1 in
7272 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
7373 "movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_M8>,
74 TB, OpSize, Sched<[WriteALULd]>;
74 TB, OpSize16, Sched<[WriteALULd]>;
7575 } // neverHasSideEffects = 1
7676 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
7777 "movz{bl|x}\t{$src, $dst|$dst, $src}",
7878 [(set GR32:$dst, (zext GR8:$src))], IIC_MOVZX>, TB,
79 OpSize16, Sched<[WriteALU]>;
79 OpSize32, Sched<[WriteALU]>;
8080 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
8181 "movz{bl|x}\t{$src, $dst|$dst, $src}",
8282 [(set GR32:$dst, (zextloadi32i8 addr:$src))], IIC_MOVZX>, TB,
83 OpSize16, Sched<[WriteALULd]>;
83 OpSize32, Sched<[WriteALULd]>;
8484 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
8585 "movz{wl|x}\t{$src, $dst|$dst, $src}",
8686 [(set GR32:$dst, (zext GR16:$src))], IIC_MOVZX>, TB,
87 OpSize16, Sched<[WriteALU]>;
87 OpSize32, Sched<[WriteALU]>;
8888 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
8989 "movz{wl|x}\t{$src, $dst|$dst, $src}",
9090 [(set GR32:$dst, (zextloadi32i16 addr:$src))], IIC_MOVZX>,
91 TB, OpSize16, Sched<[WriteALULd]>;
91 TB, OpSize32, Sched<[WriteALULd]>;
9292
9393 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
9494 // except that they use GR32_NOREX for the output operand register class
151151 def EncXOP : Encoding<2>;
152152 def EncEVEX : Encoding<3>;
153153
154 // Operand size for encodings that change based on mode.
155 class OperandSize val> {
156 bits<2> Value = val;
157 }
158 def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
159 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
160 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
161
154162 // Prefix byte classes which are used to indicate to the ad-hoc machine code
155163 // emitter that various prefix bytes are required.
156 class OpSize { bit hasOpSizePrefix = 1; }
157 class OpSize16 { bit hasOpSize16Prefix = 1; }
164 class OpSize16 { OperandSize OpSize = OpSize16; }
165 class OpSize32 { OperandSize OpSize = OpSize32; }
158166 class AdSize { bit hasAdSizePrefix = 1; }
159167 class REX_W { bit hasREX_WPrefix = 1; }
160168 class LOCK { bit hasLockPrefix = 1; }
238246 // isCodeGenonly. Needed to hide an ambiguous
239247 // AsmString from the parser, but still disassemble.
240248
241 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
242 bit hasOpSize16Prefix = 0;// Does this inst have a 0x66 prefix in 16-bit mode?
249 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
250 // based on operand size of the mode
243251 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
244252
245253 Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have?
270278
271279 // TSFlags layout should be kept in sync with X86InstrInfo.h.
272280 let TSFlags{5-0} = FormBits;
273 let TSFlags{6} = hasOpSizePrefix;
274 let TSFlags{7} = hasOpSize16Prefix;
281 let TSFlags{7-6} = OpSize.Value;
275282 let TSFlags{8} = hasAdSizePrefix;
276283 let TSFlags{10-9} = OpPrefix.Value;
277284 let TSFlags{15-11} = OpMap.Value;
931931 let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
932932 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
933933 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
934 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
934 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
935935 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
936 "nop{l}\t$zero", [], IIC_NOP>, TB;
936 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
937937 }
938938
939939
960960 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
961961 let mayLoad = 1, SchedRW = [WriteLoad] in {
962962 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
963 IIC_POP_REG16>, OpSize;
963 IIC_POP_REG16>, OpSize16;
964964 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
965 IIC_POP_REG>, OpSize16, Requires<[Not64BitMode]>;
965 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
966966 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
967 IIC_POP_REG>, OpSize;
967 IIC_POP_REG>, OpSize16;
968968 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
969 IIC_POP_MEM>, OpSize;
969 IIC_POP_MEM>, OpSize16;
970970 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
971 IIC_POP_REG>, OpSize16, Requires<[Not64BitMode]>;
971 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
972972 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
973973 IIC_POP_MEM>, Requires<[Not64BitMode]>;
974974
975 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
975 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
976 OpSize16;
976977 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
977 OpSize16, Requires<[Not64BitMode]>;
978 OpSize32, Requires<[Not64BitMode]>;
978979 } // mayLoad, SchedRW
979980
980981 let mayStore = 1, SchedRW = [WriteStore] in {
981982 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
982 IIC_PUSH_REG>, OpSize;
983 IIC_PUSH_REG>, OpSize16;
983984 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
984 IIC_PUSH_REG>, OpSize16, Requires<[Not64BitMode]>;
985 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
985986 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
986 IIC_PUSH_REG>, OpSize;
987 IIC_PUSH_REG>, OpSize16;
987988 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
988 IIC_PUSH_MEM>, OpSize;
989 IIC_PUSH_MEM>, OpSize16;
989990 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
990 IIC_PUSH_REG>, OpSize16, Requires<[Not64BitMode]>;
991 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
991992 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
992 IIC_PUSH_MEM>, OpSize16, Requires<[Not64BitMode]>;
993 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
993994
994995 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
995 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
996 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
996997 Requires<[Not64BitMode]>;
997998 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
998 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
999 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
9991000 Requires<[Not64BitMode]>;
10001001 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1001 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
1002 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
10021003 Requires<[Not64BitMode]>;
10031004 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1004 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1005 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
10051006 Requires<[Not64BitMode]>;
10061007
10071008 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
1008 OpSize;
1009 OpSize16;
10091010 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
1010 OpSize16, Requires<[Not64BitMode]>;
1011 OpSize32, Requires<[Not64BitMode]>;
10111012
10121013 } // mayStore, SchedRW
10131014 }
10361037 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
10371038 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
10381039 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1039 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
1040 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
10401041 Requires<[In64BitMode]>;
10411042 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
10421043 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
10521053 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
10531054 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
10541055 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1056 OpSize32, Requires<[Not64BitMode]>;
1057 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
10551058 OpSize16, Requires<[Not64BitMode]>;
1056 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1057 OpSize, Requires<[Not64BitMode]>;
10581059 }
10591060 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
10601061 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
10611062 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1063 OpSize32, Requires<[Not64BitMode]>;
1064 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
10621065 OpSize16, Requires<[Not64BitMode]>;
1063 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1064 OpSize, Requires<[Not64BitMode]>;
10651066 }
10661067
10671068 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
10691070 def BSWAP32r : I<0xC8, AddRegFrm,
10701071 (outs GR32:$dst), (ins GR32:$src),
10711072 "bswap{l}\t$dst",
1072 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize16, TB;
1073 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
10731074
10741075 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
10751076 "bswap{q}\t$dst",
10811082 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
10821083 "bsf{w}\t{$src, $dst|$dst, $src}",
10831084 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1084 IIC_BIT_SCAN_REG>, TB, OpSize, Sched<[WriteShift]>;
1085 IIC_BIT_SCAN_REG>, TB, OpSize16, Sched<[WriteShift]>;
10851086 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
10861087 "bsf{w}\t{$src, $dst|$dst, $src}",
10871088 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1088 IIC_BIT_SCAN_MEM>, TB, OpSize, Sched<[WriteShiftLd]>;
1089 IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
10891090 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
10901091 "bsf{l}\t{$src, $dst|$dst, $src}",
10911092 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1092 IIC_BIT_SCAN_REG>, TB, OpSize16,
1093 IIC_BIT_SCAN_REG>, TB, OpSize32,
10931094 Sched<[WriteShift]>;
10941095 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
10951096 "bsf{l}\t{$src, $dst|$dst, $src}",
10961097 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1097 IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
1098 IIC_BIT_SCAN_MEM>, TB, OpSize32, Sched<[WriteShiftLd]>;
10981099 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
10991100 "bsf{q}\t{$src, $dst|$dst, $src}",
11001101 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
11081109 "bsr{w}\t{$src, $dst|$dst, $src}",
11091110 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
11101111 IIC_BIT_SCAN_REG>,
1111 TB, OpSize, Sched<[WriteShift]>;
1112 TB, OpSize16, Sched<[WriteShift]>;
11121113 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
11131114 "bsr{w}\t{$src, $dst|$dst, $src}",
11141115 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
11151116 IIC_BIT_SCAN_MEM>, TB,
1116 OpSize, Sched<[WriteShiftLd]>;
1117 OpSize16, Sched<[WriteShiftLd]>;
11171118 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
11181119 "bsr{l}\t{$src, $dst|$dst, $src}",
11191120 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1120 IIC_BIT_SCAN_REG>, TB, OpSize16,
1121 IIC_BIT_SCAN_REG>, TB, OpSize32,
11211122 Sched<[WriteShift]>;
11221123 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
11231124 "bsr{l}\t{$src, $dst|$dst, $src}",
11241125 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1125 IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
1126 IIC_BIT_SCAN_MEM>, TB, OpSize32, Sched<[WriteShiftLd]>;
11261127 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
11271128 "bsr{q}\t{$src, $dst|$dst, $src}",
11281129 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BIT_SCAN_REG>, TB,
11391140 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
11401141 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
11411142 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1142 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize;
1143 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
11431144 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1144 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1145 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
11451146 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
11461147 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
11471148 }
11521153 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
11531154 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
11541155 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1155 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize;
1156 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
11561157 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
11571158 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1158 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize16;
1159 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
11591160 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
11601161 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
11611162 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
11631164 def SCAS8 : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
11641165 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
11651166 def SCAS16 : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1166 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize;
1167 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
11671168 def SCAS32 : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1168 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize16;
1169 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
11691170 def SCAS64 : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
11701171 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
11711172
11721173 def CMPS8 : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
11731174 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
11741175 def CMPS16 : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1175 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize;
1176 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
11761177 def CMPS32 : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1177 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1178 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
11781179 def CMPS64 : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
11791180 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
11801181 } // SchedRW
11871188 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
11881189 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
11891190 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1190 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1191 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
11911192 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1192 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1193 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
11931194 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
11941195 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
11951196 }
12001201 [(set GR8:$dst, imm:$src)], IIC_MOV>;
12011202 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
12021203 "mov{w}\t{$src, $dst|$dst, $src}",
1203 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
1204 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
12041205 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
12051206 "mov{l}\t{$src, $dst|$dst, $src}",
1206 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize16;
1207 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
12071208 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
12081209 "movabs{q}\t{$src, $dst|$dst, $src}",
12091210 [(set GR64:$dst, imm:$src)], IIC_MOV>;
12191220 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
12201221 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
12211222 "mov{w}\t{$src, $dst|$dst, $src}",
1222 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
1223 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
12231224 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
12241225 "mov{l}\t{$src, $dst|$dst, $src}",
1225 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1226 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
12261227 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
12271228 "mov{q}\t{$src, $dst|$dst, $src}",
12281229 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
12381239 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
12391240 Requires<[In32BitMode]>;
12401241 def MOV16o16a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1241 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize,
1242 Requires<[In32BitMode]>;
1242 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1243 OpSize16, Requires<[In32BitMode]>;
12431244 def MOV32o32a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
12441245 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1245 OpSize16, Requires<[In32BitMode]>;
1246 OpSize32, Requires<[In32BitMode]>;
12461247
12471248 def MOV8o8a_16 : Ii16 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
12481249 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
12491250 AdSize, Requires<[In16BitMode]>;
12501251 def MOV16o16a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1251 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize,
1252 AdSize, Requires<[In16BitMode]>;
1252 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1253 OpSize16, AdSize, Requires<[In16BitMode]>;
12531254 def MOV32o32a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
12541255 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1255 AdSize, OpSize16, Requires<[In16BitMode]>;
1256 AdSize, OpSize32, Requires<[In16BitMode]>;
12561257 }
12571258 let mayStore = 1 in {
12581259 def MOV8ao8 : Ii32 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
12591260 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
12601261 Requires<[In32BitMode]>;
12611262 def MOV16ao16 : Ii32 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1262 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize,
1263 Requires<[In32BitMode]>;
1263 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1264 OpSize16, Requires<[In32BitMode]>;
12641265 def MOV32ao32 : Ii32 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
12651266 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1266 OpSize16, Requires<[In32BitMode]>;
1267 OpSize32, Requires<[In32BitMode]>;
12671268
12681269 def MOV8ao8_16 : Ii16 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
12691270 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
12701271 AdSize, Requires<[In16BitMode]>;
12711272 def MOV16ao16_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1272 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize,
1273 AdSize, Requires<[In16BitMode]>;
1273 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1274 OpSize16, AdSize, Requires<[In16BitMode]>;
12741275 def MOV32ao32_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
12751276 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1276 OpSize16, AdSize, Requires<[In16BitMode]>;
1277 OpSize32, AdSize, Requires<[In16BitMode]>;
12771278 }
12781279 }
12791280
12841285 "movabs{b}\t{$src, %al|al, $src}", []>,
12851286 Requires<[In64BitMode]>;
12861287 def MOV64o16a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1287 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize,
1288 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16,
12881289 Requires<[In64BitMode]>;
12891290 def MOV64o32a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
1290 "movabs{l}\t{$src, %eax|eax, $src}", []>,
1291 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
12911292 Requires<[In64BitMode]>;
12921293 def MOV64o64a : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64:$src),
12931294 "movabs{q}\t{$src, %rax|rax, $src}", []>,
12991300 "movabs{b}\t{%al, $dst|$dst, al}", []>,
13001301 Requires<[In64BitMode]>;
13011302 def MOV64ao16 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1302 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize,
1303 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16,
13031304 Requires<[In64BitMode]>;
13041305 def MOV64ao32 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
1305 "movabs{l}\t{%eax, $dst|$dst, eax}", []>,
1306 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
13061307 Requires<[In64BitMode]>;
13071308 def MOV64ao64 : RIi64<0xA3, RawFrmMemOffs, (outs offset64:$dst), (ins),
13081309 "movabs{q}\t{%rax, $dst|$dst, rax}", []>,
13151316 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
13161317 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
13171318 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1318 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1319 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
13191320 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1320 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1321 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
13211322 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
13221323 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
13231324 }
13281329 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
13291330 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
13301331 "mov{w}\t{$src, $dst|$dst, $src}",
1331 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
1332 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
13321333 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
13331334 "mov{l}\t{$src, $dst|$dst, $src}",
1334 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize16;
1335 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
13351336 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
13361337 "mov{q}\t{$src, $dst|$dst, $src}",
13371338 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
13431344 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
13441345 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
13451346 "mov{w}\t{$src, $dst|$dst, $src}",
1346 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
1347 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
13471348 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
13481349 "mov{l}\t{$src, $dst|$dst, $src}",
1349 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1350 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
13501351 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
13511352 "mov{q}\t{$src, $dst|$dst, $src}",
13521353 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
13931394 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
13941395 "bt{w}\t{$src2, $src1|$src1, $src2}",
13951396 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1396 OpSize, TB;
1397 OpSize16, TB;
13971398 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
13981399 "bt{l}\t{$src2, $src1|$src1, $src2}",
13991400 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1400 OpSize16, TB;
1401 OpSize32, TB;
14011402 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
14021403 "bt{q}\t{$src2, $src1|$src1, $src2}",
14031404 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
14141415 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
14151416 // (implicit EFLAGS)]
14161417 [], IIC_BT_MR
1417 >, OpSize, TB, Requires<[FastBTMem]>;
1418 >, OpSize16, TB, Requires<[FastBTMem]>;
14181419 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
14191420 "bt{l}\t{$src2, $src1|$src1, $src2}",
14201421 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
14211422 // (implicit EFLAGS)]
14221423 [], IIC_BT_MR
1423 >, OpSize16, TB, Requires<[FastBTMem]>;
1424 >, OpSize32, TB, Requires<[FastBTMem]>;
14241425 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
14251426 "bt{q}\t{$src2, $src1|$src1, $src2}",
14261427 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
14331434 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
14341435 "bt{w}\t{$src2, $src1|$src1, $src2}",
14351436 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1436 IIC_BT_RI>, OpSize, TB;
1437 IIC_BT_RI>, OpSize16, TB;
14371438 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
14381439 "bt{l}\t{$src2, $src1|$src1, $src2}",
14391440 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1440 IIC_BT_RI>, OpSize16, TB;
1441 IIC_BT_RI>, OpSize32, TB;
14411442 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
14421443 "bt{q}\t{$src2, $src1|$src1, $src2}",
14431444 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
14511452 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
14521453 "bt{w}\t{$src2, $src1|$src1, $src2}",
14531454 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1454 ], IIC_BT_MI>, OpSize, TB;
1455 ], IIC_BT_MI>, OpSize16, TB;
14551456 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
14561457 "bt{l}\t{$src2, $src1|$src1, $src2}",
14571458 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1458 ], IIC_BT_MI>, OpSize16, TB;
1459 ], IIC_BT_MI>, OpSize32, TB;
14591460 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
14601461 "bt{q}\t{$src2, $src1|$src1, $src2}",
14611462 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
14661467 let SchedRW = [WriteALU] in {
14671468 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
14681469 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1469 OpSize, TB;
1470 OpSize16, TB;
14701471 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
14711472 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1472 OpSize16, TB;
1473 OpSize32, TB;
14731474 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
14741475 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
14751476 } // SchedRW
14771478 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
14781479 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
14791480 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1480 OpSize, TB;
1481 OpSize16, TB;
14811482 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
14821483 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1483 OpSize16, TB;
1484 OpSize32, TB;
14841485 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
14851486 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
14861487 }
14881489 let SchedRW = [WriteALU] in {
14891490 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
14901491 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1491 OpSize, TB;
1492 OpSize16, TB;
14921493 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
14931494 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1494 OpSize16, TB;
1495 OpSize32, TB;
14951496 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
14961497 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
14971498 } // SchedRW
14991500 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
15001501 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
15011502 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1502 OpSize, TB;
1503 OpSize16, TB;
15031504 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
15041505 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1505 OpSize16, TB;
1506 OpSize32, TB;
15061507 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
15071508 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
15081509 }
15101511 let SchedRW = [WriteALU] in {
15111512 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
15121513 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1513 OpSize, TB;
1514 OpSize16, TB;
15141515 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
15151516 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1516 OpSize16, TB;
1517 OpSize32, TB;
15171518 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
15181519 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
15191520 } // SchedRW
15211522 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
15221523 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
15231524 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1524 OpSize, TB;
1525 OpSize16, TB;
15251526 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
15261527 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1527 OpSize16, TB;
1528 OpSize32, TB;
15281529 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
15291530 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
15301531 }
15321533 let SchedRW = [WriteALU] in {
15331534 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
15341535 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1535 OpSize, TB;
1536 OpSize16, TB;
15361537 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
15371538 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1538 OpSize16, TB;
1539 OpSize32, TB;
15391540 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
15401541 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
15411542 } // SchedRW
15431544 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
15441545 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
15451546 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1546 OpSize, TB;
1547 OpSize16, TB;
15471548 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
15481549 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1549 OpSize16, TB;
1550 OpSize32, TB;
15501551 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
15511552 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
15521553 }
15541555 let SchedRW = [WriteALU] in {
15551556 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
15561557 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1557 OpSize, TB;
1558 OpSize16, TB;
15581559 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
15591560 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1560 OpSize16, TB;
1561 OpSize32, TB;
15611562 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1562 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1563 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
15631564 } // SchedRW
15641565
15651566 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
15661567 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1567 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1568 OpSize, TB;
1568 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1569 OpSize16, TB;
15691570 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1570 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1571 OpSize16, TB;
1571 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1572 OpSize32, TB;
15721573 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
15731574 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
15741575 }
15761577 let SchedRW = [WriteALU] in {
15771578 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
15781579 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1579 OpSize, TB;
1580 OpSize16, TB;
15801581 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
15811582 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1582 OpSize16, TB;
1583 OpSize32, TB;
15831584 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
15841585 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
15851586 } // SchedRW
15871588 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
15881589 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
15891590 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1590 OpSize, TB;
1591 OpSize16, TB;
15911592 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
15921593 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1593 OpSize16, TB;
1594 OpSize32, TB;
15941595 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
15951596 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
15961597 }
16201621 [(set
16211622 GR16:$dst,
16221623 (!cast(frag # "_16") addr:$ptr, GR16:$val))],
1623 itin>, OpSize;
1624 itin>, OpSize16;
16241625 def NAME#32rm : I
16251626 (ins GR32:$val, i32mem:$ptr),
16261627 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
16271628 [(set
16281629 GR32:$dst,
16291630 (!cast(frag # "_32") addr:$ptr, GR32:$val))],
1630 itin>, OpSize16;
1631 itin>, OpSize32;
16311632 def NAME#64rm : RI
16321633 (ins GR64:$val, i64mem:$ptr),
16331634 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
16461647 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
16471648 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
16481649 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1649 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
1650 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1651 OpSize16;
16501652 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
16511653 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1652 OpSize16;
1654 OpSize32;
16531655 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
16541656 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
16551657 }
16561658
16571659 // Swap between EAX and other registers.
16581660 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1659 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize;
1661 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
16601662 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
16611663 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1662 OpSize16, Requires<[Not64BitMode]>;
1664 OpSize32, Requires<[Not64BitMode]>;
16631665 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
16641666 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
16651667 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
16741676 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
16751677 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
16761678 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1677 OpSize;
1679 OpSize16;
16781680 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
16791681 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1680 OpSize16;
1682 OpSize32;
16811683 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
16821684 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
16831685 } // SchedRW
16871689 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
16881690 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
16891691 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1690 OpSize;
1692 OpSize16;
16911693 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
16921694 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1693 OpSize16;
1695 OpSize32;
16941696 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
16951697 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
16961698
17021704 IIC_CMPXCHG_REG8>, TB;
17031705 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
17041706 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1705 IIC_CMPXCHG_REG>, TB, OpSize;
1707 IIC_CMPXCHG_REG>, TB, OpSize16;
17061708 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
17071709 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1708 IIC_CMPXCHG_REG>, TB, OpSize16;
1710 IIC_CMPXCHG_REG>, TB, OpSize32;
17091711 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
17101712 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
17111713 IIC_CMPXCHG_REG>, TB;
17181720 IIC_CMPXCHG_MEM8>, TB;
17191721 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
17201722 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1721 IIC_CMPXCHG_MEM>, TB, OpSize;
1723 IIC_CMPXCHG_MEM>, TB, OpSize16;
17221724 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
17231725 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1724 IIC_CMPXCHG_MEM>, TB, OpSize16;
1726 IIC_CMPXCHG_MEM>, TB, OpSize32;
17251727 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
17261728 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
17271729 IIC_CMPXCHG_MEM>, TB;
17631765 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
17641766 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
17651767 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1766 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize;
1768 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
17671769 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1768 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize16;
1770 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
17691771 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
17701772 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
17711773 }
17741776 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
17751777 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
17761778 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1777 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize;
1779 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
17781780 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1779 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1781 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
17801782 }
17811783
17821784 // Flag instructions
18311833 let SchedRW = [WriteSystem] in {
18321834 // Check Array Index Against Bounds
18331835 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1834 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
1836 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
18351837 Requires<[Not64BitMode]>;
18361838 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1837 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1839 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
18381840 Requires<[Not64BitMode]>;
18391841
18401842 // Adjust RPL Field of Segment Selector
18541856 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
18551857 "movbe{w}\t{$src, $dst|$dst, $src}",
18561858 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1857 OpSize, T8;
1859 OpSize16, T8;
18581860 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
18591861 "movbe{l}\t{$src, $dst|$dst, $src}",
18601862 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1861 OpSize16, T8;
1863 OpSize32, T8;
18621864 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
18631865 "movbe{q}\t{$src, $dst|$dst, $src}",
18641866 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
18681870 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
18691871 "movbe{w}\t{$src, $dst|$dst, $src}",
18701872 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1871 OpSize, T8;
1873 OpSize16, T8;
18721874 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
18731875 "movbe{l}\t{$src, $dst|$dst, $src}",
18741876 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1875 OpSize16, T8;
1877 OpSize32, T8;
18761878 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
18771879 "movbe{q}\t{$src, $dst|$dst, $src}",
18781880 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
18861888 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
18871889 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
18881890 "rdrand{w}\t$dst",
1889 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
1891 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
18901892 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
18911893 "rdrand{l}\t$dst",
1892 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1894 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
18931895 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
18941896 "rdrand{q}\t$dst",
18951897 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
19011903 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
19021904 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
19031905 "rdseed{w}\t$dst",
1904 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize, TB;
1906 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
19051907 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
19061908 "rdseed{l}\t$dst",
1907 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
1909 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
19081910 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
19091911 "rdseed{q}\t$dst",
19101912 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
19171919 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
19181920 "lzcnt{w}\t{$src, $dst|$dst, $src}",
19191921 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1920 OpSize;
1922 OpSize16;
19211923 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
19221924 "lzcnt{w}\t{$src, $dst|$dst, $src}",
19231925 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1924 (implicit EFLAGS)]>, XS, OpSize;
1926 (implicit EFLAGS)]>, XS, OpSize16;
19251927
19261928 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
19271929 "lzcnt{l}\t{$src, $dst|$dst, $src}",
19281930 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
1929 OpSize16;
1931 OpSize32;
19301932 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
19311933 "lzcnt{l}\t{$src, $dst|$dst, $src}",
19321934 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1933 (implicit EFLAGS)]>, XS, OpSize16;
1935 (implicit EFLAGS)]>, XS, OpSize32;
19341936
19351937 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
19361938 "lzcnt{q}\t{$src, $dst|$dst, $src}",
19491951 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
19501952 "tzcnt{w}\t{$src, $dst|$dst, $src}",
19511953 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1952 OpSize;
1954 OpSize16;
19531955 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
19541956 "tzcnt{w}\t{$src, $dst|$dst, $src}",
19551957 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1956 (implicit EFLAGS)]>, XS, OpSize;
1958 (implicit EFLAGS)]>, XS, OpSize16;
19571959
19581960 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
19591961 "tzcnt{l}\t{$src, $dst|$dst, $src}",
19601962 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
1961 OpSize16;
1963 OpSize32;
19621964 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
19631965 "tzcnt{l}\t{$src, $dst|$dst, $src}",
19641966 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1965 (implicit EFLAGS)]>, XS, OpSize16;
1967 (implicit EFLAGS)]>, XS, OpSize32;
19661968
19671969 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
19681970 "tzcnt{q}\t{$src, $dst|$dst, $src}",
67886788 "popcnt{w}\t{$src, $dst|$dst, $src}",
67896789 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
67906790 IIC_SSE_POPCNT_RR>,
6791 OpSize, XS;
6791 OpSize16, XS;
67926792 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
67936793 "popcnt{w}\t{$src, $dst|$dst, $src}",
67946794 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6795 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, OpSize, XS;
6795 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, OpSize16, XS;
67966796
67976797 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
67986798 "popcnt{l}\t{$src, $dst|$dst, $src}",
74777477 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
74787478 int_x86_sse42_crc32_32_8>;
74797479 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7480 int_x86_sse42_crc32_32_16>, OpSize;
7480 int_x86_sse42_crc32_32_16>, OpSize16;
74817481 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7482 int_x86_sse42_crc32_32_16>, OpSize;
7482 int_x86_sse42_crc32_32_16>, OpSize16;
74837483 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7484 int_x86_sse42_crc32_32_32>, OpSize16;
7484 int_x86_sse42_crc32_32_32>, OpSize32;
74857485 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7486 int_x86_sse42_crc32_32_32>, OpSize16;
7486 int_x86_sse42_crc32_32_32>, OpSize32;
74877487 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
74887488 int_x86_sse42_crc32_64_64>, REX_W;
74897489 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
2121 [(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>;
2222 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2323 "shl{w}\t{%cl, $dst|$dst, cl}",
24 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;
24 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize16;
2525 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2626 "shl{l}\t{%cl, $dst|$dst, cl}",
27 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize16;
27 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize32;
2828 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
2929 "shl{q}\t{%cl, $dst|$dst, cl}",
3030 [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
3838 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
3939 "shl{w}\t{$src2, $dst|$dst, $src2}",
4040 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
41 OpSize;
41 OpSize16;
4242 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
4343 "shl{l}\t{$src2, $dst|$dst, $src2}",
4444 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>,
45 OpSize16;
45 OpSize32;
4646 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
4747 (ins GR64:$src1, i8imm:$src2),
4848 "shl{q}\t{$src2, $dst|$dst, $src2}",
5555 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
5656 "shl{b}\t$dst", [], IIC_SR>;
5757 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
58 "shl{w}\t$dst", [], IIC_SR>, OpSize;
58 "shl{w}\t$dst", [], IIC_SR>, OpSize16;
5959 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
60 "shl{l}\t$dst", [], IIC_SR>, OpSize16;
60 "shl{l}\t$dst", [], IIC_SR>, OpSize32;
6161 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
6262 "shl{q}\t$dst", [], IIC_SR>;
6363 } // hasSideEffects = 0
7575 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
7676 "shl{w}\t{%cl, $dst|$dst, cl}",
7777 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
78 OpSize;
78 OpSize16;
7979 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
8080 "shl{l}\t{%cl, $dst|$dst, cl}",
8181 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
82 OpSize16;
82 OpSize32;
8383 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
8484 "shl{q}\t{%cl, $dst|$dst, cl}",
8585 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
9191 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
9292 "shl{w}\t{$src, $dst|$dst, $src}",
9393 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
94 IIC_SR>,
95 OpSize;
94 IIC_SR>, OpSize16;
9695 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
9796 "shl{l}\t{$src, $dst|$dst, $src}",
9897 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
99 IIC_SR>, OpSize16;
98 IIC_SR>, OpSize32;
10099 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
101100 "shl{q}\t{$src, $dst|$dst, $src}",
102101 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
110109 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
111110 "shl{w}\t$dst",
112111 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
113 IIC_SR>,
114 OpSize;
112 IIC_SR>, OpSize16;
115113 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
116114 "shl{l}\t$dst",
117115 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
118 IIC_SR>, OpSize16;
116 IIC_SR>, OpSize32;
119117 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
120118 "shl{q}\t$dst",
121119 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
129127 [(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>;
130128 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
131129 "shr{w}\t{%cl, $dst|$dst, cl}",
132 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;
130 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize16;
133131 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
134132 "shr{l}\t{%cl, $dst|$dst, cl}",
135 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize16;
133 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize32;
136134 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
137135 "shr{q}\t{%cl, $dst|$dst, cl}",
138136 [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
144142 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
145143 "shr{w}\t{$src2, $dst|$dst, $src2}",
146144 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))],
147 IIC_SR>, OpSize;
145 IIC_SR>, OpSize16;
148146 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
149147 "shr{l}\t{$src2, $dst|$dst, $src2}",
150148 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
151 IIC_SR>, OpSize16;
149 IIC_SR>, OpSize32;
152150 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
153151 "shr{q}\t{$src2, $dst|$dst, $src2}",
154152 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;
159157 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>;
160158 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
161159 "shr{w}\t$dst",
162 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize;
160 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize16;
163161 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
164162 "shr{l}\t$dst",
165 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize16;
163 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize32;
166164 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
167165 "shr{q}\t$dst",
168166 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
177175 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
178176 "shr{w}\t{%cl, $dst|$dst, cl}",
179177 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
180 OpSize;
178 OpSize16;
181179 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
182180 "shr{l}\t{%cl, $dst|$dst, cl}",
183181 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
184 OpSize16;
182 OpSize32;
185183 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
186184 "shr{q}\t{%cl, $dst|$dst, cl}",
187185 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
193191 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
194192 "shr{w}\t{$src, $dst|$dst, $src}",
195193 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
196 IIC_SR>,
197 OpSize;
194 IIC_SR>, OpSize16;
198195 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
199196 "shr{l}\t{$src, $dst|$dst, $src}",
200197 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
201 IIC_SR>, OpSize16;
198 IIC_SR>, OpSize32;
202199 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
203200 "shr{q}\t{$src, $dst|$dst, $src}",
204201 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
212209 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
213210 "shr{w}\t$dst",
214211 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
215 IIC_SR>,OpSize;
212 IIC_SR>, OpSize16;
216213 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
217214 "shr{l}\t$dst",
218215 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
219 IIC_SR>, OpSize16;
216 IIC_SR>, OpSize32;
220217 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
221218 "shr{q}\t$dst",
222219 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
232229 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
233230 "sar{w}\t{%cl, $dst|$dst, cl}",
234231 [(set GR16:$dst, (sra GR16:$src1, CL))],
235 IIC_SR>, OpSize;
232 IIC_SR>, OpSize16;
236233 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
237234 "sar{l}\t{%cl, $dst|$dst, cl}",
238235 [(set GR32:$dst, (sra GR32:$src1, CL))],
239 IIC_SR>, OpSize16;
236 IIC_SR>, OpSize32;
240237 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
241238 "sar{q}\t{%cl, $dst|$dst, cl}",
242239 [(set GR64:$dst, (sra GR64:$src1, CL))],
250247 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
251248 "sar{w}\t{$src2, $dst|$dst, $src2}",
252249 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))],
253 IIC_SR>,
254 OpSize;
250 IIC_SR>, OpSize16;
255251 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
256252 "sar{l}\t{$src2, $dst|$dst, $src2}",
257253 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
258 IIC_SR>, OpSize16;
254 IIC_SR>, OpSize32;
259255 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
260256 (ins GR64:$src1, i8imm:$src2),
261257 "sar{q}\t{$src2, $dst|$dst, $src2}",
270266 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
271267 "sar{w}\t$dst",
272268 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))],
273 IIC_SR>, OpSize;
269 IIC_SR>, OpSize16;
274270 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
275271 "sar{l}\t$dst",
276272 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))],
277 IIC_SR>, OpSize16;
273 IIC_SR>, OpSize32;
278274 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
279275 "sar{q}\t$dst",
280276 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
291287 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
292288 "sar{w}\t{%cl, $dst|$dst, cl}",
293289 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)],
294 IIC_SR>, OpSize;
290 IIC_SR>, OpSize16;
295291 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
296292 "sar{l}\t{%cl, $dst|$dst, cl}",
297293 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
298 IIC_SR>, OpSize16;
294 IIC_SR>, OpSize32;
299295 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
300296 "sar{q}\t{%cl, $dst|$dst, cl}",
301297 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
308304 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
309305 "sar{w}\t{$src, $dst|$dst, $src}",
310306 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
311 IIC_SR>,
312 OpSize;
307 IIC_SR>, OpSize16;
313308 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
314309 "sar{l}\t{$src, $dst|$dst, $src}",
315310 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
316 IIC_SR>, OpSize16;
311 IIC_SR>, OpSize32;
317312 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
318313 "sar{q}\t{$src, $dst|$dst, $src}",
319314 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
327322 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
328323 "sar{w}\t$dst",
329324 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)],
330 IIC_SR>,
331 OpSize;
325 IIC_SR>, OpSize16;
332326 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
333327 "sar{l}\t$dst",
334328 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)],
335 IIC_SR>, OpSize16;
329 IIC_SR>, OpSize32;
336330 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
337331 "sar{q}\t$dst",
338332 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
354348 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
355349
356350 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
357 "rcl{w}\t$dst", [], IIC_SR>, OpSize;
351 "rcl{w}\t$dst", [], IIC_SR>, OpSize16;
358352 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
359 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
353 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
360354 let Uses = [CL] in
361355 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
362 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
356 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
363357
364358 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
365 "rcl{l}\t$dst", [], IIC_SR>, OpSize16;
359 "rcl{l}\t$dst", [], IIC_SR>, OpSize32;
366360 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
367 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
361 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
368362 let Uses = [CL] in
369363 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
370 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
364 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
371365
372366
373367 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
388382 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
389383
390384 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
391 "rcr{w}\t$dst", [], IIC_SR>, OpSize;
385 "rcr{w}\t$dst", [], IIC_SR>, OpSize16;
392386 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
393 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
387 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
394388 let Uses = [CL] in
395389 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
396 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
390 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
397391
398392 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
399 "rcr{l}\t$dst", [], IIC_SR>, OpSize16;
393 "rcr{l}\t$dst", [], IIC_SR>, OpSize32;
400394 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
401 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
395 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
402396 let Uses = [CL] in
403397 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
404 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
398 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
405399
406400 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
407401 "rcr{q}\t$dst", [], IIC_SR>;
419413 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
420414 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
421415 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
422 "rcl{w}\t$dst", [], IIC_SR>, OpSize;
416 "rcl{w}\t$dst", [], IIC_SR>, OpSize16;
423417 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
424 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
418 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
425419 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
426 "rcl{l}\t$dst", [], IIC_SR>, OpSize16;
420 "rcl{l}\t$dst", [], IIC_SR>, OpSize32;
427421 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
428 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
422 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
429423 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
430424 "rcl{q}\t$dst", [], IIC_SR>;
431425 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
436430 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
437431 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
438432 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
439 "rcr{w}\t$dst", [], IIC_SR>, OpSize;
433 "rcr{w}\t$dst", [], IIC_SR>, OpSize16;
440434 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
441 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
435 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
442436 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
443 "rcr{l}\t$dst", [], IIC_SR>, OpSize16;
437 "rcr{l}\t$dst", [], IIC_SR>, OpSize32;
444438 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
445 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
439 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
446440 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
447441 "rcr{q}\t$dst", [], IIC_SR>;
448442 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
452446 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
453447 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
454448 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
455 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
449 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
456450 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
457 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
451 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
458452 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
459453 "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
460454
461455 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
462456 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
463457 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
464 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
458 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
465459 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
466 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
460 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
467461 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
468462 "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
469463 }
478472 [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
479473 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
480474 "rol{w}\t{%cl, $dst|$dst, cl}",
481 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize;
475 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize16;
482476 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
483477 "rol{l}\t{%cl, $dst|$dst, cl}",
484 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize16;
478 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize32;
485479 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
486480 "rol{q}\t{%cl, $dst|$dst, cl}",
487481 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
493487 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
494488 "rol{w}\t{$src2, $dst|$dst, $src2}",
495489 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))],
496 IIC_SR>,
497 OpSize;
490 IIC_SR>, OpSize16;
498491 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
499492 "rol{l}\t{$src2, $dst|$dst, $src2}",
500493 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
501 IIC_SR>, OpSize16;
494 IIC_SR>, OpSize32;
502495 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
503496 (ins GR64:$src1, i8imm:$src2),
504497 "rol{q}\t{$src2, $dst|$dst, $src2}",
513506 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
514507 "rol{w}\t$dst",
515508 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))],
516 IIC_SR>, OpSize;
509 IIC_SR>, OpSize16;
517510 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
518511 "rol{l}\t$dst",
519512 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))],
520 IIC_SR>, OpSize16;
513 IIC_SR>, OpSize32;
521514 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
522515 "rol{q}\t$dst",
523516 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
533526 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
534527 "rol{w}\t{%cl, $dst|$dst, cl}",
535528 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)],
536 IIC_SR>, OpSize;
529 IIC_SR>, OpSize16;
537530 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
538531 "rol{l}\t{%cl, $dst|$dst, cl}",
539532 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
540 IIC_SR>, OpSize16;
533 IIC_SR>, OpSize32;
541534 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
542535 "rol{q}\t{%cl, $dst|$dst, cl}",
543536 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
550543 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src1),
551544 "rol{w}\t{$src1, $dst|$dst, $src1}",
552545 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)],
553 IIC_SR>,
554 OpSize;
546 IIC_SR>, OpSize16;
555547 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1),
556548 "rol{l}\t{$src1, $dst|$dst, $src1}",
557549 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)],
558 IIC_SR>, OpSize16;
550 IIC_SR>, OpSize32;
559551 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1),
560552 "rol{q}\t{$src1, $dst|$dst, $src1}",
561553 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)],
569561 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
570562 "rol{w}\t$dst",
571563 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
572 IIC_SR>,
573 OpSize;
564 IIC_SR>, OpSize16;
574565 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
575566 "rol{l}\t$dst",
576567 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
577 IIC_SR>, OpSize16;
568 IIC_SR>, OpSize32;
578569 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
579570 "rol{q}\t$dst",
580571 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
588579 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
589580 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
590581 "ror{w}\t{%cl, $dst|$dst, cl}",
591 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize;
582 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize16;
592583 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
593584 "ror{l}\t{%cl, $dst|$dst, cl}",
594 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize16;
585 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize32;
595586 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
596587 "ror{q}\t{%cl, $dst|$dst, cl}",
597588 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
603594 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
604595 "ror{w}\t{$src2, $dst|$dst, $src2}",
605596 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))],
606 IIC_SR>,
607 OpSize;
597 IIC_SR>, OpSize16;
608598 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
609599 "ror{l}\t{$src2, $dst|$dst, $src2}",
610600 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))],
611 IIC_SR>, OpSize16;
601 IIC_SR>, OpSize32;
612602 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
613603 (ins GR64:$src1, i8imm:$src2),
614604 "ror{q}\t{$src2, $dst|$dst, $src2}",
623613 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
624614 "ror{w}\t$dst",
625615 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))],
626 IIC_SR>, OpSize;
616 IIC_SR>, OpSize16;
627617 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
628618 "ror{l}\t$dst",
629619 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))],
630 IIC_SR>, OpSize16;
620 IIC_SR>, OpSize32;
631621 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
632622 "ror{q}\t$dst",
633623 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],
643633 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
644634 "ror{w}\t{%cl, $dst|$dst, cl}",
645635 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)],
646 IIC_SR>, OpSize;
636 IIC_SR>, OpSize16;
647637 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
648638 "ror{l}\t{%cl, $dst|$dst, cl}",
649639 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
650 IIC_SR>, OpSize16;
640 IIC_SR>, OpSize32;
651641 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
652642 "ror{q}\t{%cl, $dst|$dst, cl}",
653643 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
660650 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
661651 "ror{w}\t{$src, $dst|$dst, $src}",
662652 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
663 IIC_SR>,
664 OpSize;
653 IIC_SR>, OpSize16;
665654 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
666655 "ror{l}\t{$src, $dst|$dst, $src}",
667656 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
668 IIC_SR>, OpSize16;
657 IIC_SR>, OpSize32;
669658 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
670659 "ror{q}\t{$src, $dst|$dst, $src}",
671660 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
679668 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
680669 "ror{w}\t$dst",
681670 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)],
682 IIC_SR>,
683 OpSize;
671 IIC_SR>, OpSize16;
684672 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
685673 "ror{l}\t$dst",
686674 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)],
687 IIC_SR>, OpSize16;
675 IIC_SR>, OpSize32;
688676 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
689677 "ror{q}\t$dst",
690678 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
704692 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
705693 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))],
706694 IIC_SHD16_REG_CL>,
707 TB, OpSize;
695 TB, OpSize16;
708696 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
709697 (ins GR16:$src1, GR16:$src2),
710698 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
711699 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))],
712700 IIC_SHD16_REG_CL>,
713 TB, OpSize;
701 TB, OpSize16;
714702 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
715703 (ins GR32:$src1, GR32:$src2),
716704 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
717705 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
718 IIC_SHD32_REG_CL>, TB, OpSize16;
706 IIC_SHD32_REG_CL>, TB, OpSize32;
719707 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
720708 (ins GR32:$src1, GR32:$src2),
721709 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
722710 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
723 IIC_SHD32_REG_CL>, TB, OpSize16;
711 IIC_SHD32_REG_CL>, TB, OpSize32;
724712 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
725713 (ins GR64:$src1, GR64:$src2),
726714 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
742730 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
743731 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
744732 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
745 TB, OpSize;
733 TB, OpSize16;
746734 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
747735 (outs GR16:$dst),
748736 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
749737 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
750738 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
751739 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
752 TB, OpSize;
740 TB, OpSize16;
753741 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
754742 (outs GR32:$dst),
755743 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
756744 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
757745 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
758746 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
759 TB, OpSize16;
747 TB, OpSize32;
760748 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
761749 (outs GR32:$dst),
762750 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
763751 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
764752 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
765753 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
766 TB, OpSize16;
754 TB, OpSize32;
767755 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
768756 (outs GR64:$dst),
769757 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
786774 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
787775 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
788776 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
789 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
777 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16;
790778 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
791779 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
792780 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
793 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
781 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16;
794782
795783 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
796784 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
797785 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
798 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize16;
786 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32;
799787 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
800788 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
801789 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
802 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize16;
790 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32;
803791
804792 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
805793 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
817805 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
818806 (i8 imm:$src3)), addr:$dst)],
819807 IIC_SHD16_MEM_IM>,
820 TB, OpSize;
808 TB, OpSize16;
821809 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
822810 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
823811 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
824812 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
825813 (i8 imm:$src3)), addr:$dst)],
826814 IIC_SHD16_MEM_IM>,
827 TB, OpSize;
815 TB, OpSize16;
828816
829817 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
830818 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
832820 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
833821 (i8 imm:$src3)), addr:$dst)],
834822 IIC_SHD32_MEM_IM>,
835 TB, OpSize16;
823 TB, OpSize32;
836824 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
837825 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
838826 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
839827 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
840828 (i8 imm:$src3)), addr:$dst)],
841829 IIC_SHD32_MEM_IM>,
842 TB, OpSize16;
830 TB, OpSize32;
843831
844832 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
845833 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
6363 def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", []>, TB,
6464 Requires<[In64BitMode]>;
6565
66 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize;
66 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize16;
6767 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>,
68 OpSize16;
68 OpSize32;
6969 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
7070 Requires<[In64BitMode]>;
7171 } // SchedRW
8080 "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
8181 let Defs = [AX], Uses = [DX] in
8282 def IN16rr : I<0xED, RawFrm, (outs), (ins),
83 "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize;
83 "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize16;
8484 let Defs = [EAX], Uses = [DX] in
8585 def IN32rr : I<0xED, RawFrm, (outs), (ins),
86 "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize16;
86 "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
8787
8888 let Defs = [AL] in
8989 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
9090 "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
9191 let Defs = [AX] in
9292 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
93 "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize;
93 "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
9494 let Defs = [EAX] in
9595 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
96 "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize16;
96 "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
9797
9898 let Uses = [DX, AL] in
9999 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
100100 "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
101101 let Uses = [DX, AX] in
102102 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
103 "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize;
103 "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
104104 let Uses = [DX, EAX] in
105105 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
106 "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize16;
106 "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
107107
108108 let Uses = [AL] in
109109 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
110110 "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
111111 let Uses = [AX] in
112112 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
113 "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize;
113 "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
114114 let Uses = [EAX] in
115115 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
116 "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize16;
116 "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
117117
118118 def IN8 : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
119119 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
120120 def IN16 : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
121 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize;
121 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
122122 def IN32 : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
123 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
123 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
124124 } // SchedRW
125125
126126 //===----------------------------------------------------------------------===//
178178
179179 let SchedRW = [WriteMove] in {
180180 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
181 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize;
181 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
182182 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
183 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
183 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
184184 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
185185 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
186186
187187 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
188 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize;
188 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
189189 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
190 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
190 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32;
191191 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
192192 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
193193
194194 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
195 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize;
195 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
196196 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
197 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
197 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
198198 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
199199 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
200200
201201 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
202 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize;
202 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
203203 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
204 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
204 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize32;
205205 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
206206 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
207207 } // SchedRW
213213 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
214214
215215 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
216 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB, OpSize;
216 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
217 OpSize16;
217218 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
218 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB, OpSize;
219 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
220 OpSize16;
219221
220222 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
221223 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
222224 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
223 OpSize16;
225 OpSize32;
224226 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
225227 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
226 OpSize16;
228 OpSize32;
227229 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
228230 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
229231 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
231233 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
232234
233235 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
234 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB, OpSize;
236 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
237 OpSize16;
235238 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
236 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB, OpSize;
239 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
240 OpSize16;
237241 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
238242 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
239 OpSize16;
243 OpSize32;
240244 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
241245 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
242 OpSize16;
246 OpSize32;
243247 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
244248 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
245249 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
249253 [], IIC_INVLPG>, TB;
250254
251255 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
252 "str{w}\t$dst", [], IIC_STR>, TB, OpSize;
256 "str{w}\t$dst", [], IIC_STR>, TB, OpSize16;
253257 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
254 "str{l}\t$dst", [], IIC_STR>, TB, OpSize16;
258 "str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
255259 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
256260 "str{q}\t$dst", [], IIC_STR>, TB;
257261 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
264268
265269 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
266270 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
267 OpSize, Requires<[Not64BitMode]>;
271 OpSize16, Requires<[Not64BitMode]>;
268272 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
269273 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
270 OpSize16, Requires<[Not64BitMode]>;
274 OpSize32, Requires<[Not64BitMode]>;
271275 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
272276 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
273 OpSize, Requires<[Not64BitMode]>;
277 OpSize16, Requires<[Not64BitMode]>;
274278 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
275279 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
276 OpSize16, Requires<[Not64BitMode]>;
280 OpSize32, Requires<[Not64BitMode]>;
277281 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
278282 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
279 OpSize, Requires<[Not64BitMode]>;
283 OpSize16, Requires<[Not64BitMode]>;
280284 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
281285 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
282 OpSize16, Requires<[Not64BitMode]>;
286 OpSize32, Requires<[Not64BitMode]>;
283287 def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
284288 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
285 OpSize, Requires<[Not64BitMode]>;
289 OpSize16, Requires<[Not64BitMode]>;
286290 def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
287291 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
288 OpSize16, Requires<[Not64BitMode]>;
292 OpSize32, Requires<[Not64BitMode]>;
289293 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
290 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize, TB;
294 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB;
291295 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
292296 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
293 OpSize16, Requires<[Not64BitMode]>;
297 OpSize32, Requires<[Not64BitMode]>;
294298 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
295 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize, TB;
299 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB;
296300 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
297301 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
298 OpSize16, Requires<[Not64BitMode]>;
302 OpSize32, Requires<[Not64BitMode]>;
299303 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
300304 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, Requires<[In64BitMode]>;
301305 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
304308 // No "pop cs" instruction.
305309 def POPSS16 : I<0x17, RawFrm, (outs), (ins),
306310 "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
307 OpSize, Requires<[Not64BitMode]>;
311 OpSize16, Requires<[Not64BitMode]>;
308312 def POPSS32 : I<0x17, RawFrm, (outs), (ins),
309313 "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
310 OpSize16, Requires<[Not64BitMode]>;
311
314 OpSize32, Requires<[Not64BitMode]>;
315
312316 def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
313317 "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
314 OpSize, Requires<[Not64BitMode]>;
318 OpSize16, Requires<[Not64BitMode]>;
315319 def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
316320 "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
317 OpSize16, Requires<[Not64BitMode]>;
318
321 OpSize32, Requires<[Not64BitMode]>;
322
319323 def POPES16 : I<0x07, RawFrm, (outs), (ins),
320324 "pop{w}\t{%es|es}", [], IIC_POP_SR>,
321 OpSize, Requires<[Not64BitMode]>;
325 OpSize16, Requires<[Not64BitMode]>;
322326 def POPES32 : I<0x07, RawFrm, (outs), (ins),
323327 "pop{l}\t{%es|es}", [], IIC_POP_SR>,
324 OpSize16, Requires<[Not64BitMode]>;
325
328 OpSize32, Requires<[Not64BitMode]>;
329
326330 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
327 "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize, TB;
331 "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB;
328332 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
329333 "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
330 OpSize16, Requires<[Not64BitMode]>;
334 OpSize32, Requires<[Not64BitMode]>;
331335 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
332336 "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB, Requires<[In64BitMode]>;
333337
334338 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
335 "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize, TB;
339 "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB;
336340 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
337341 "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
338 OpSize16, Requires<[Not64BitMode]>;
342 OpSize32, Requires<[Not64BitMode]>;
339343 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
340344 "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB, Requires<[In64BitMode]>;
341345
342346
343347 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
344 "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
348 "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
345349 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
346 "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
350 "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
347351
348352 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
349 "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
353 "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
350354 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
351 "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
355 "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
352356 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
353357 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
354358
355359 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
356 "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
360 "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
357361 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
358 "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
362 "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
359363
360364 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
361 "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
365 "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
362366 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
363 "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
367 "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
364368 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
365369 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
366370
367371 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
368 "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
372 "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
369373 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
370 "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
374 "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
371375
372376 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
373377 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
388392
389393 let SchedRW = [WriteSystem] in {
390394 def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
391 "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize, Requires<[Not64BitMode]>;
395 "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
392396 def SGDT32m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
393 "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize16, TB, Requires <[Not64BitMode]>;
397 "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
394398 def SGDT64m : I<0x01, MRM0m, (outs opaque80mem:$dst), (ins),
395399 "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
396400 def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
397 "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize, Requires<[Not64BitMode]>;
401 "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
398402 def SIDT32m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
399 "sidt{l}\t$dst", []>, OpSize16, TB, Requires <[Not64BitMode]>;
403 "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
400404 def SIDT64m : I<0x01, MRM1m, (outs opaque80mem:$dst), (ins),
401405 "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
402406 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
403 "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize;
407 "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
404408 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
405409 "sldt{w}\t$dst", [], IIC_SLDT>, TB;
406410 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
407 "sldt{l}\t$dst", [], IIC_SLDT>, OpSize16, TB;
411 "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
408412
409413 // LLDT is not interpreted specially in 64-bit mode because there is no sign
410414 // extension.
414418 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
415419
416420 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
417 "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize, Requires<[Not64BitMode]>;
421 "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
418422 def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
419 "lgdt{l}\t$src", [], IIC_LGDT>, OpSize16, TB, Requires<[Not64BitMode]>;
423 "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
420424 def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
421425 "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
422426 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
423 "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize, Requires<[Not64BitMode]>;
427 "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
424428 def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
425 "lidt{l}\t$src", [], IIC_LIDT>, OpSize16, TB, Requires<[Not64BitMode]>;
429 "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
426430 def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
427431 "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
428432 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
439443 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [], IIC_RDPMC>, TB;
440444
441445 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
442 "smsw{w}\t$dst", [], IIC_SMSW>, OpSize, TB;
446 "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB;
443447 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
444 "smsw{l}\t$dst", [], IIC_SMSW>, OpSize16, TB;
448 "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB;
445449 // no m form encodable; use SMSW16m
446450 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
447451 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
8888 enum {
8989 VEX = 1, XOP = 2, EVEX = 3
9090 };
91
92 enum {
93 OpSize16 = 1, OpSize32 = 2
94 };
9195 }
9296
9397 // If rows are added to the opcode extension tables, then corresponding entries
233237 Form = byteFromRec(Rec, "FormBits");
234238 Encoding = byteFromRec(Rec->getValueAsDef("OpEnc"), "Value");
235239
236 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
237 HasOpSize16Prefix = Rec->getValueAsBit("hasOpSize16Prefix");
240 OpSize = byteFromRec(Rec->getValueAsDef("OpSize"), "Value");
238241 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
239242 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
240243 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
405408 else
406409 insnContext = IC_VEX;
407410 } else if (Is64Bit || HasREX_WPrefix) {
408 if (HasREX_WPrefix && (HasOpSizePrefix || OpPrefix == X86Local::PD))
411 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
409412 insnContext = IC_64BIT_REXW_OPSIZE;
410 else if (HasOpSizePrefix && OpPrefix == X86Local::XD)
413 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
411414 insnContext = IC_64BIT_XD_OPSIZE;
412 else if (HasOpSizePrefix && OpPrefix == X86Local::XS)
415 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
413416 insnContext = IC_64BIT_XS_OPSIZE;
414 else if (HasOpSizePrefix || OpPrefix == X86Local::PD)
417 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
415418 insnContext = IC_64BIT_OPSIZE;
416419 else if (HasAdSizePrefix)
417420 insnContext = IC_64BIT_ADSIZE;
428431 else
429432 insnContext = IC_64BIT;
430433 } else {
431 if (HasOpSizePrefix && OpPrefix == X86Local::XD)
434 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
432435 insnContext = IC_XD_OPSIZE;
433 else if (HasOpSizePrefix && OpPrefix == X86Local::XS)
436 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
434437 insnContext = IC_XS_OPSIZE;
435 else if (HasOpSizePrefix || OpPrefix == X86Local::PD)
438 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
436439 insnContext = IC_OPSIZE;
437440 else if (HasAdSizePrefix)
438441 insnContext = IC_ADSIZE;
494497 const unsigned *operandMapping,
495498 OperandEncoding (*encodingFromString)
496499 (const std::string&,
497 bool hasOpSizePrefix)) {
500 uint8_t OpSize)) {
498501 if (optional) {
499502 if (physicalOperandIndex >= numPhysicalOperands)
500503 return;
512515 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
513516
514517 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
515 HasOpSizePrefix);
518 OpSize);
516519 Spec->operands[operandIndex].type = typeFromString(typeName,
517 HasREX_WPrefix,
518 HasOpSizePrefix,
519 HasOpSize16Prefix);
520 HasREX_WPrefix, OpSize);
520521
521522 ++operandIndex;
522523 ++physicalOperandIndex;
11501151 #define TYPE(str, type) if (s == str) return type;
11511152 OperandType RecognizableInstr::typeFromString(const std::string &s,
11521153 bool hasREX_WPrefix,
1153 bool hasOpSizePrefix,
1154 bool hasOpSize16Prefix) {
1154 uint8_t OpSize) {
11551155 if(hasREX_WPrefix) {
11561156 // For instructions with a REX_W prefix, a declared 32-bit register encoding
11571157 // is special.
11581158 TYPE("GR32", TYPE_R32)
11591159 }
1160 if(hasOpSizePrefix) {
1161 // For instructions with an OpSize prefix, a declared 16-bit register or
1160 if(OpSize == X86Local::OpSize16) {
1161 // For OpSize16 instructions, a declared 16-bit register or
11621162 // immediate encoding is special.
11631163 TYPE("GR16", TYPE_Rv)
11641164 TYPE("i16imm", TYPE_IMMv)
1165 }
1166 if(hasOpSize16Prefix) {
1167 // For instructions with an OpSize16 prefix, a declared 32-bit register or
1165 } else if(OpSize == X86Local::OpSize32) {
1166