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Add isel patterns for v2f32 / v4f32 neon.vbsl intrinsics. rdar://12471808 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165673 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 7 years ago
2 changed file(s) with 26 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
44994499 (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))),
45004500 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
45014501 Requires<[HasNEON]>;
4502 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 DPR:$src1),
4503 (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))),
4504 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4505 Requires<[HasNEON]>;
45024506
45034507 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
45044508 (and DPR:$Vm, (vnotd DPR:$Vd)))),
45224526 Requires<[HasNEON]>;
45234527 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1),
45244528 (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))),
4529 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4530 Requires<[HasNEON]>;
4531 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1),
4532 (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))),
45254533 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
45264534 Requires<[HasNEON]>;
45274535
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
1
2 ; rdar://12471808
13
24 define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
35 ;CHECK: v_bsli8:
124126 ret <2 x i32> %vbsl3.i
125127 }
126128
129 define <2 x float> @f4(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone optsize ssp {
130 ; CHECK: f4:
131 ; CHECK: vbsl
132 %vbsl4.i = tail call <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind
133 ret <2 x float> %vbsl4.i
134 }
135
127136 define <16 x i8> @g1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind readnone optsize ssp {
128137 ; CHECK: g1:
129138 ; CHECK: vbsl
145154 ret <4 x i32> %vbsl3.i
146155 }
147156
157 define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone optsize ssp {
158 ; CHECK: g4:
159 ; CHECK: vbsl
160 %vbsl4.i = tail call <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind
161 ret <4 x float> %vbsl4.i
162 }
163
148164 declare <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
149165 declare <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
150166 declare <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
151167 declare <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone
152168 declare <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone
153169 declare <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
170 declare <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
171 declare <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone