llvm.org GIT mirror llvm / 6b28d35
Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the lower half correctly. Missed in r155982. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156059 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 8 years ago
3 changed file(s) with 39 addition(s) and 24 deletion(s). Raw diff Collapse all Expand all
8181
8282 void DecodePSHUFHWMask(EVT VT, unsigned Imm,
8383 SmallVectorImpl &ShuffleMask) {
84 unsigned NumLanes = VT.getSizeInBits() / 128;
85 unsigned NumElts = 8 * NumLanes;
84 unsigned NumElts = VT.getVectorNumElements();
8685
8786 for (unsigned l = 0; l != NumElts; l += 8) {
8887 unsigned NewImm = Imm;
9897
9998 void DecodePSHUFLWMask(EVT VT, unsigned Imm,
10099 SmallVectorImpl &ShuffleMask) {
101 unsigned NumLanes = VT.getSizeInBits() / 128;
102 unsigned NumElts = 8 * NumLanes;
100 unsigned NumElts = VT.getVectorNumElements();
103101
104102 for (unsigned l = 0; l != NumElts; l += 8) {
105103 unsigned NewImm = Imm;
39033903 for (unsigned i = 0; i != NumElts; ++i) {
39043904 int Elt = N->getMaskElt(i);
39053905 if (Elt < 0) continue;
3906 Elt %= NumLaneElts;
3907 unsigned ShAmt = i << Shift;
3908 if (ShAmt >= 8) ShAmt -= 8;
3906 Elt &= NumLaneElts - 1;
3907 unsigned ShAmt = (i << Shift) % 8;
39093908 Mask |= Elt << ShAmt;
39103909 }
39113910
39153914 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
39163915 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
39173916 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3917 EVT VT = N->getValueType(0);
3918
3919 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
3920 "Unsupported vector type for PSHUFHW");
3921
3922 unsigned NumElts = VT.getVectorNumElements();
3923
39183924 unsigned Mask = 0;
3919 // 8 nodes, but we only care about the last 4.
3920 for (unsigned i = 7; i >= 4; --i) {
3921 int Val = N->getMaskElt(i);
3922 if (Val >= 0)
3923 Mask |= (Val - 4);
3924 if (i != 4)
3925 Mask <<= 2;
3926 }
3925 for (unsigned l = 0; l != NumElts; l += 8) {
3926 // 8 nodes per lane, but we only care about the last 4.
3927 for (unsigned i = 0; i < 4; ++i) {
3928 int Elt = N->getMaskElt(l+i+4);
3929 if (Elt < 0) continue;
3930 Elt &= 0x3; // only 2-bits.
3931 Mask |= Elt << (i * 2);
3932 }
3933 }
3934
39273935 return Mask;
39283936 }
39293937
39303938 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
39313939 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
39323940 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3941 EVT VT = N->getValueType(0);
3942
3943 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
3944 "Unsupported vector type for PSHUFHW");
3945
3946 unsigned NumElts = VT.getVectorNumElements();
3947
39333948 unsigned Mask = 0;
3934 // 8 nodes, but we only care about the first 4.
3935 for (int i = 3; i >= 0; --i) {
3936 int Val = N->getMaskElt(i);
3937 if (Val >= 0)
3938 Mask |= Val;
3939 if (i != 0)
3940 Mask <<= 2;
3941 }
3949 for (unsigned l = 0; l != NumElts; l += 8) {
3950 // 8 nodes per lane, but we only care about the first 4.
3951 for (unsigned i = 0; i < 4; ++i) {
3952 int Elt = N->getMaskElt(l+i);
3953 if (Elt < 0) continue;
3954 Elt &= 0x3; // only 2-bits
3955 Mask |= Elt << (i * 2);
3956 }
3957 }
3958
39423959 return Mask;
39433960 }
39443961
2222 ; CHECK: vpshuflw $27, %ymm
2323 define <16 x i16> @vpshuflw(<16 x i16> %src1) nounwind uwtable readnone ssp {
2424 entry:
25 %shuffle.i = shufflevector <16 x i16> %src1, <16 x i16> %src1, <16 x i32> 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7, i32 11, i32 10, i32 9, i32 8, i32 12, i32 13, i32 14, i32 15>
25 %shuffle.i = shufflevector <16 x i16> %src1, <16 x i16> %src1, <16 x i32> undef, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7, i32 11, i32 10, i32 9, i32 8, i32 12, i32 13, i32 14, i32 15>
2626 ret <16 x i16> %shuffle.i
2727 }