llvm.org GIT mirror llvm / 6b16eff
Add support for the PowerPC 64-bit SVR4 ABI. The Link Register is volatile when using the 32-bit SVR4 ABI. Make it possible to use the 64-bit SVR4 ABI. Add non-volatile registers for the 64-bit SVR4 ABI. Make sure r2 is a reserved register when using the 64-bit SVR4 ABI. Update PPCFrameInfo for the 64-bit SVR4 ABI. Add FIXME for 64-bit Darwin PPC. Insert NOP instruction after direct function calls. Emit official procedure descriptors. Create TOC entries for GlobalAddress references. Spill 64-bit non-volatile registers to the correct slots. Only custom lower VAARG when using the 32-bit SVR4 ABI. Use simple VASTART lowering for the 64-bit SVR4 ABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79091 91177308-0d34-0410-b5e6-96231b3b80d8 Tilmann Scheller 10 years ago
9 changed file(s) with 364 addition(s) and 75 deletion(s). Raw diff Collapse all Expand all
8080 };
8181
8282 StringMap FnStubs;
83 StringMap GVStubs, HiddenGVStubs;
83 StringMap GVStubs, HiddenGVStubs, TOC;
8484 const PPCSubtarget &Subtarget;
85 uint64_t LabelID;
8586 public:
8687 explicit PPCAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
8788 const TargetAsmInfo *T, bool V)
8889 : AsmPrinter(O, TM, T, V),
89 Subtarget(TM.getSubtarget()) {}
90 Subtarget(TM.getSubtarget()), LabelID(0) {}
9091
9192 virtual const char *getPassName() const {
9293 return "PowerPC Assembly Printer";
309310 printOperand(MI, OpNo+1);
310311 }
311312
313 void printTOCEntryLabel(const MachineInstr *MI, unsigned OpNo) {
314 const MachineOperand &MO = MI->getOperand(OpNo);
315
316 assert(MO.getType() == MachineOperand::MO_GlobalAddress);
317
318 GlobalValue *GV = MO.getGlobal();
319
320 std::string Name = Mang->getMangledName(GV);
321
322 // Map symbol -> label of TOC entry.
323 if (TOC.count(Name) == 0) {
324 std::string Label;
325 Label += TAI->getPrivateGlobalPrefix();
326 Label += "C";
327 Label += utostr(LabelID++);
328
329 TOC[Name] = Label;
330 }
331
332 O << TOC[Name] << "@toc";
333 }
334
312335 void printPredicateOperand(const MachineInstr *MI, unsigned OpNo,
313336 const char *Modifier);
314337
329352 }
330353
331354 bool runOnMachineFunction(MachineFunction &F);
355 bool doFinalization(Module &M);
332356
333357 void getAnalysisUsage(AnalysisUsage &AU) const {
334358 AU.setPreservesAll();
611635 printVisibility(CurrentFnName, F->getVisibility());
612636
613637 EmitAlignment(MF.getAlignment(), F);
614 O << CurrentFnName << ":\n";
638
639 if (Subtarget.isPPC64()) {
640 // Emit an official procedure descriptor.
641 // FIXME 64-bit SVR4: Use MCSection here?
642 O << "\t.section\t\".opd\",\"aw\"\n";
643 O << "\t.align 3\n";
644 O << CurrentFnName << ":\n";
645 O << "\t.quad .L." << CurrentFnName << ",.TOC.@tocbase\n";
646 O << "\t.previous\n";
647 O << ".L." << CurrentFnName << ":\n";
648 } else {
649 O << CurrentFnName << ":\n";
650 }
615651
616652 // Emit pre-function debug information.
617653 DW->BeginFunction(&MF);
730766 O << '\n';
731767 }
732768
769 bool PPCLinuxAsmPrinter::doFinalization(Module &M) {
770 const TargetData *TD = TM.getTargetData();
771
772 bool isPPC64 = TD->getPointerSizeInBits() == 64;
773
774 if (isPPC64 && !TOC.empty()) {
775 // FIXME 64-bit SVR4: Use MCSection here?
776 O << "\t.section\t\".toc\",\"aw\"\n";
777
778 for (StringMap::iterator I = TOC.begin(), E = TOC.end();
779 I != E; ++I) {
780 O << I->second << ":\n";
781 O << "\t.tc " << I->getKeyData() << "[TC]," << I->getKeyData() << '\n';
782 }
783 }
784
785 return AsmPrinter::doFinalization(M);
786 }
733787
734788 /// runOnMachineFunction - This uses the printMachineInstruction()
735789 /// method to print assembly for each instruction.
3030
3131 /// getReturnSaveOffset - Return the previous frame offset to save the
3232 /// return address.
33 static unsigned getReturnSaveOffset(bool LP64, bool isDarwinABI) {
33 static unsigned getReturnSaveOffset(bool isPPC64, bool isDarwinABI) {
3434 if (isDarwinABI)
35 return LP64 ? 16 : 8;
35 return isPPC64 ? 16 : 8;
3636 // SVR4 ABI:
37 return 4;
37 return isPPC64 ? 16 : 4;
3838 }
3939
4040 /// getFramePointerSaveOffset - Return the previous frame offset to save the
4141 /// frame pointer.
42 static unsigned getFramePointerSaveOffset(bool LP64, bool isDarwinABI) {
42 static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) {
4343 // For the Darwin ABI:
4444 // Use the TOC save slot in the PowerPC linkage area for saving the frame
4545 // pointer (if needed.) LLVM does not generate code that uses the TOC (R2
4646 // is treated as a caller saved register.)
4747 if (isDarwinABI)
48 return LP64 ? 40 : 20;
49
50 // SVR4 ABI:
51 // Save it right before the link register
48 return isPPC64 ? 40 : 20;
49
50 // SVR4 ABI: First slot in the general register save area.
5251 return -4U;
5352 }
5453
5554 /// getLinkageSize - Return the size of the PowerPC ABI linkage area.
5655 ///
57 static unsigned getLinkageSize(bool LP64, bool isDarwinABI) {
58 if (isDarwinABI)
59 return 6 * (LP64 ? 8 : 4);
56 static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI) {
57 if (isDarwinABI || isPPC64)
58 return 6 * (isPPC64 ? 8 : 4);
6059
6160 // SVR4 ABI:
6261 return 8;
6463
6564 /// getMinCallArgumentsSize - Return the size of the minium PowerPC ABI
6665 /// argument area.
67 static unsigned getMinCallArgumentsSize(bool LP64, bool isDarwinABI) {
68 // For the Darwin ABI:
66 static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI) {
67 // For the Darwin ABI / 64-bit SVR4 ABI:
6968 // The prolog code of the callee may store up to 8 GPR argument registers to
7069 // the stack, allowing va_start to index over them in memory if its varargs.
7170 // Because we cannot tell if this is needed on the caller side, we have to
7271 // conservatively assume that it is needed. As such, make sure we have at
7372 // least enough stack space for the caller to store the 8 GPRs.
74 if (isDarwinABI)
75 return 8 * (LP64 ? 8 : 4);
76
77 // SVR4 ABI:
73 if (isDarwinABI || isPPC64)
74 return 8 * (isPPC64 ? 8 : 4);
75
76 // 32-bit SVR4 ABI:
7877 // There is no default stack allocated for the 8 first GPR arguments.
7978 return 0;
8079 }
8180
8281 /// getMinCallFrameSize - Return the minimum size a call frame can be using
8382 /// the PowerPC ABI.
84 static unsigned getMinCallFrameSize(bool LP64, bool isDarwinABI) {
83 static unsigned getMinCallFrameSize(bool isPPC64, bool isDarwinABI) {
8584 // The call frame needs to be at least big enough for linkage and 8 args.
86 return getLinkageSize(LP64, isDarwinABI) +
87 getMinCallArgumentsSize(LP64, isDarwinABI);
85 return getLinkageSize(isPPC64, isDarwinABI) +
86 getMinCallArgumentsSize(isPPC64, isDarwinABI);
8887 }
8988
9089 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
173172 std::pair(PPC::V20, -192)
174173 };
175174
176 NumEntries = array_lengthof(Offsets);
177
178 return Offsets;
175 static const std::pair Offsets64[] = {
176 // Floating-point register save area offsets.
177 std::pair(PPC::F31, -8),
178 std::pair(PPC::F30, -16),
179 std::pair(PPC::F29, -24),
180 std::pair(PPC::F28, -32),
181 std::pair(PPC::F27, -40),
182 std::pair(PPC::F26, -48),
183 std::pair(PPC::F25, -56),
184 std::pair(PPC::F24, -64),
185 std::pair(PPC::F23, -72),
186 std::pair(PPC::F22, -80),
187 std::pair(PPC::F21, -88),
188 std::pair(PPC::F20, -96),
189 std::pair(PPC::F19, -104),
190 std::pair(PPC::F18, -112),
191 std::pair(PPC::F17, -120),
192 std::pair(PPC::F16, -128),
193 std::pair(PPC::F15, -136),
194 std::pair(PPC::F14, -144),
195
196 // General register save area offsets.
197 // FIXME 64-bit SVR4: Are 32-bit registers actually allocated in 64-bit
198 // mode?
199 std::pair(PPC::R31, -4),
200 std::pair(PPC::R30, -12),
201 std::pair(PPC::R29, -20),
202 std::pair(PPC::R28, -28),
203 std::pair(PPC::R27, -36),
204 std::pair(PPC::R26, -44),
205 std::pair(PPC::R25, -52),
206 std::pair(PPC::R24, -60),
207 std::pair(PPC::R23, -68),
208 std::pair(PPC::R22, -76),
209 std::pair(PPC::R21, -84),
210 std::pair(PPC::R20, -92),
211 std::pair(PPC::R19, -100),
212 std::pair(PPC::R18, -108),
213 std::pair(PPC::R17, -116),
214 std::pair(PPC::R16, -124),
215 std::pair(PPC::R15, -132),
216 std::pair(PPC::R14, -140),
217
218 std::pair(PPC::X31, -8),
219 std::pair(PPC::X30, -16),
220 std::pair(PPC::X29, -24),
221 std::pair(PPC::X28, -32),
222 std::pair(PPC::X27, -40),
223 std::pair(PPC::X26, -48),
224 std::pair(PPC::X25, -56),
225 std::pair(PPC::X24, -64),
226 std::pair(PPC::X23, -72),
227 std::pair(PPC::X22, -80),
228 std::pair(PPC::X21, -88),
229 std::pair(PPC::X20, -96),
230 std::pair(PPC::X19, -104),
231 std::pair(PPC::X18, -112),
232 std::pair(PPC::X17, -120),
233 std::pair(PPC::X16, -128),
234 std::pair(PPC::X15, -136),
235 std::pair(PPC::X14, -144),
236
237 // CR save area offset.
238 // FIXME SVR4: Disable CR save area for now.
239 // std::pair(PPC::CR2, -4),
240 // std::pair(PPC::CR3, -4),
241 // std::pair(PPC::CR4, -4),
242 // std::pair(PPC::CR2LT, -4),
243 // std::pair(PPC::CR2GT, -4),
244 // std::pair(PPC::CR2EQ, -4),
245 // std::pair(PPC::CR2UN, -4),
246 // std::pair(PPC::CR3LT, -4),
247 // std::pair(PPC::CR3GT, -4),
248 // std::pair(PPC::CR3EQ, -4),
249 // std::pair(PPC::CR3UN, -4),
250 // std::pair(PPC::CR4LT, -4),
251 // std::pair(PPC::CR4GT, -4),
252 // std::pair(PPC::CR4EQ, -4),
253 // std::pair(PPC::CR4UN, -4),
254
255 // VRSAVE save area offset.
256 std::pair(PPC::VRSAVE, -4),
257
258 // Vector register save area
259 std::pair(PPC::V31, -16),
260 std::pair(PPC::V30, -32),
261 std::pair(PPC::V29, -48),
262 std::pair(PPC::V28, -64),
263 std::pair(PPC::V27, -80),
264 std::pair(PPC::V26, -96),
265 std::pair(PPC::V25, -112),
266 std::pair(PPC::V24, -128),
267 std::pair(PPC::V23, -144),
268 std::pair(PPC::V22, -160),
269 std::pair(PPC::V21, -176),
270 std::pair(PPC::V20, -192)
271 };
272
273 if (TM.getSubtarget().isPPC64()) {
274 NumEntries = array_lengthof(Offsets64);
275
276 return Offsets64;
277 } else {
278 NumEntries = array_lengthof(Offsets);
279
280 return Offsets;
281 }
179282 }
180283 };
181284
211211 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
212212 setOperationAction(ISD::VASTART , MVT::Other, Custom);
213213
214 // VAARG is custom lowered with the SVR4 ABI
215 if (TM.getSubtarget().isSVR4ABI())
214 // VAARG is custom lowered with the 32-bit SVR4 ABI.
215 if ( TM.getSubtarget().isSVR4ABI()
216 && !TM.getSubtarget().isPPC64())
216217 setOperationAction(ISD::VAARG, MVT::Other, Custom);
217218 else
218219 setOperationAction(ISD::VAARG, MVT::Other, Expand);
418419 case PPCISD::VPERM: return "PPCISD::VPERM";
419420 case PPCISD::Hi: return "PPCISD::Hi";
420421 case PPCISD::Lo: return "PPCISD::Lo";
422 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
421423 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
422424 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
423425 case PPCISD::SRL: return "PPCISD::SRL";
427429 case PPCISD::STD_32: return "PPCISD::STD_32";
428430 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
429431 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
432 case PPCISD::NOP: return "PPCISD::NOP";
430433 case PPCISD::MTCTR: return "PPCISD::MTCTR";
431434 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
432435 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
11751178
11761179 const TargetMachine &TM = DAG.getTarget();
11771180
1181 // 64-bit SVR4 ABI code is always position-independent.
1182 // The actual address of the GlobalValue is stored in the TOC.
1183 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1184 return DAG.getNode(PPCISD::TOC_ENTRY, dl, MVT::i64, GA,
1185 DAG.getRegister(PPC::X2, MVT::i64));
1186 }
1187
11781188 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero);
11791189 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero);
11801190
13071317 const PPCSubtarget &Subtarget) {
13081318 DebugLoc dl = Op.getDebugLoc();
13091319
1310 if (Subtarget.isDarwinABI()) {
1320 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
13111321 // vastart just stores the address of the VarArgsFrameIndex slot into the
13121322 // memory location argument.
13131323 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
13161326 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
13171327 }
13181328
1319 // For the SVR4 ABI we follow the layout of the va_list struct.
1329 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
13201330 // We suppose the given va_list is already allocated.
13211331 //
13221332 // typedef struct {
14491459 }
14501460
14511461 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1452 /// depending on which subtarget is selected.
1453 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1454 if (Subtarget.isDarwinABI()) {
1455 static const unsigned FPR[] = {
1456 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1457 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1458 };
1459 return FPR;
1460 }
1461
1462
1462 /// on Darwin.
1463 static const unsigned *GetFPR() {
14631464 static const unsigned FPR[] = {
14641465 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1465 PPC::F8
1466 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
14661467 };
1468
14671469 return FPR;
14681470 }
14691471
14861488 &Ins,
14871489 DebugLoc dl, SelectionDAG &DAG,
14881490 SmallVectorImpl &InVals) {
1489 if (PPCSubTarget.isSVR4ABI()) {
1491 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
14901492 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
14911493 dl, DAG, InVals);
14921494 } else {
15041506 DebugLoc dl, SelectionDAG &DAG,
15051507 SmallVectorImpl &InVals) {
15061508
1507 // SVR4 ABI Stack Frame Layout:
1509 // 32-bit SVR4 ABI Stack Frame Layout:
15081510 // +-----------------------------------+
15091511 // +--> | Back chain |
15101512 // | +-----------------------------------+
16861688 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
16871689 }
16881690
1689 // FIXME SVR4: We only need to save FP argument registers if CR bit 6 is
1690 // set.
1691 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
1692 // is set.
16911693
16921694 // The double arguments are stored to the VarArgsFrameIndex
16931695 // on the stack.
17301732 &Ins,
17311733 DebugLoc dl, SelectionDAG &DAG,
17321734 SmallVectorImpl &InVals) {
1733
17341735 // TODO: add description of PPC stack frame format, or at least some docs.
17351736 //
17361737 MachineFunction &MF = DAG.getMachineFunction();
17551756 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
17561757 };
17571758
1758 static const unsigned *FPR = GetFPR(PPCSubTarget);
1759 static const unsigned *FPR = GetFPR();
17591760
17601761 static const unsigned VR[] = {
17611762 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
19851986 GPR_idx++;
19861987 }
19871988 ArgOffset += 16;
1988 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs);
1989 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
19891990 }
19901991 ++VR_idx;
19911992 } else {
22612262 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
22622263 PseudoSourceValue::getFixedStack(NewRetAddr), 0);
22632264
2264 // When using the SVR4 ABI there is no need to move the FP stack slot
2265 // as the FP is never overwritten.
2265 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2266 // slot as the FP is never overwritten.
22662267 if (isDarwinABI) {
22672268 int NewFPLoc =
22682269 SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
23102311 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0);
23112312 Chain = SDValue(LROpOut.getNode(), 1);
23122313
2313 // When using the SVR4 ABI there is no need to load the FP stack slot
2314 // as the FP is never overwritten.
2314 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2315 // slot as the FP is never overwritten.
23152316 if (isDarwinABI) {
23162317 FPOpOut = getFramePointerFrameIndex(DAG);
23172318 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0);
24862487 int SPDiff, unsigned NumBytes,
24872488 const SmallVectorImpl &Ins,
24882489 SmallVectorImpl &InVals) {
2489
24902490 std::vector NodeTys;
24912491 SmallVector Ops;
24922492 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
25282528 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
25292529 InFlag = Chain.getValue(1);
25302530
2531 // Add a NOP immediately after the branch instruction when using the 64-bit
2532 // SVR4 ABI. At link time, if caller and callee are in a different module and
2533 // thus have a different TOC, the call will be replaced with a call to a stub
2534 // function which saves the current TOC, loads the TOC of the callee and
2535 // branches to the callee. The NOP will be replaced with a load instruction
2536 // which restores the TOC of the caller from the TOC save slot of the current
2537 // stack frame. If caller and callee belong to the same module (and have the
2538 // same TOC), the NOP will remain unchanged.
2539 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
2540 // Insert NOP.
2541 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Flag, InFlag);
2542 }
2543
25312544 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
25322545 DAG.getIntPtrConstant(BytesCalleePops, true),
25332546 InFlag);
25462559 const SmallVectorImpl &Ins,
25472560 DebugLoc dl, SelectionDAG &DAG,
25482561 SmallVectorImpl &InVals) {
2549 if (PPCSubTarget.isSVR4ABI()) {
2562 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
25502563 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
25512564 isTailCall, Outs, Ins,
25522565 dl, DAG, InVals);
25662579 DebugLoc dl, SelectionDAG &DAG,
25672580 SmallVectorImpl &InVals) {
25682581 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2569 // of the SVR4 ABI stack frame layout.
2582 // of the 32-bit SVR4 ABI stack frame layout.
25702583
25712584 assert((!isTailCall ||
25722585 (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
28452858 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
28462859 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
28472860 };
2848 static const unsigned *FPR = GetFPR(PPCSubTarget);
2861 static const unsigned *FPR = GetFPR();
28492862
28502863 static const unsigned VR[] = {
28512864 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5959 /// though these are usually folded into other nodes.
6060 Hi, Lo,
6161
62 TOC_ENTRY,
63
6264 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
6365 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
6466 /// compute an allocation on the stack.
8385 /// CALL - A direct function call.
8486 CALL_Darwin, CALL_SVR4,
8587
88 /// NOP - Special NOP which follows 64-bit SVR4 calls.
89 NOP,
90
8691 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
8792 /// MTCTR instruction.
8893 MTCTR,
122122 (BL8_ELF tglobaladdr:$dst)>;
123123 def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)),
124124 (BL8_ELF texternalsym:$dst)>;
125 def : Pat<(PPCnop),
126 (NOP)>;
125127
126128 // Atomic operations
127129 let usesCustomDAGSchedInserter = 1 in {
542544 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
543545 "ld $rD, $src", LdStLD,
544546 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
547 def LDtoc: DSForm_1<58, 0, (outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
548 "ld $rD, $disp($reg)", LdStLD,
549 [(set G8RC:$rD,
550 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
545551 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
546552 "ldx $rD, $src", LdStLD,
547553 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
5151 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
5252 SDTCisPtrTy<0>, SDTCisVT<1, i32>
5353 ]>;
54
55 def SDT_PPCnop : SDTypeProfile<0, 0, []>;
5456
5557 //===----------------------------------------------------------------------===//
5658 // PowerPC specific DAG Nodes.
8486
8587 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
8688 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
89 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
8790 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
8891 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
8992
110113 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
111114 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
112115 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
116 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInFlag, SDNPOutFlag]>;
113117 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
114118 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
115119 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
304308 def memrix : Operand { // memri where the imm is shifted 2 bits.
305309 let PrintMethod = "printMemRegImmShifted";
306310 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
311 }
312 def tocentry : Operand {
313 let PrintMethod = "printTOCEntryLabel";
314 let MIOperandInfo = (ops i32imm:$imm);
307315 }
308316
309317 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
173173
174174 PPC::LR, 0
175175 };
176
176
177 // 32-bit SVR4 calling convention.
177178 static const unsigned SVR4_CalleeSavedRegs[] = {
178179 PPC::R14, PPC::R15,
179180 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
199200 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
200201 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
201202
202 PPC::LR, 0
203 0
203204 };
204205 // 64-bit Darwin calling convention.
205206 static const unsigned Darwin64_CalleeSavedRegs[] = {
226227
227228 PPC::LR8, 0
228229 };
230
231 // 64-bit SVR4 calling convention.
232 static const unsigned SVR4_64_CalleeSavedRegs[] = {
233 PPC::X14, PPC::X15,
234 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
235 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
236 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
237 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
238
239 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
240 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
241 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
242 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
243 PPC::F30, PPC::F31,
244
245 PPC::CR2, PPC::CR3, PPC::CR4,
246
247 PPC::VRSAVE,
248
249 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
250 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
251 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
252
253 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
254 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
255 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
256
257 0
258 };
229259
230260 if (Subtarget.isDarwinABI())
231261 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
232262 Darwin32_CalleeSavedRegs;
233
234 return SVR4_CalleeSavedRegs;
263
264 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs;
235265 }
236266
237267 const TargetRegisterClass* const*
266296 &PPC::GPRCRegClass, 0
267297 };
268298
299 // 32-bit SVR4 calling convention.
269300 static const TargetRegisterClass * const SVR4_CalleeSavedRegClasses[] = {
270301 &PPC::GPRCRegClass,&PPC::GPRCRegClass,
271302 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
294325 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
295326 &PPC::CRBITRCRegClass,
296327
297 &PPC::GPRCRegClass, 0
328 0
298329 };
299330
300331 // 64-bit Darwin calling convention.
326357
327358 &PPC::G8RCRegClass, 0
328359 };
360
361 // 64-bit SVR4 calling convention.
362 static const TargetRegisterClass * const SVR4_64_CalleeSavedRegClasses[] = {
363 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
364 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
365 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
366 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
367 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
368
369 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
370 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
371 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
372 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
373 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
374
375 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
376
377 &PPC::VRSAVERCRegClass,
378
379 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
380 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
381 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
382
383 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
384 &PPC::CRBITRCRegClass,
385 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
386 &PPC::CRBITRCRegClass,
387 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
388 &PPC::CRBITRCRegClass,
389
390 0
391 };
329392
330393 if (Subtarget.isDarwinABI())
331394 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
332395 Darwin32_CalleeSavedRegClasses;
333396
334 return SVR4_CalleeSavedRegClasses;
397 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegClasses
398 : SVR4_CalleeSavedRegClasses;
335399 }
336400
337401 // needsFP - Return true if the specified function should have a dedicated frame
363427 Reserved.set(PPC::R13); // Small Data Area pointer register
364428 }
365429
366 // On PPC64, r13 is the thread pointer. Never allocate this register. Note
367 // that this is over conservative, as it also prevents allocation of R31 when
368 // the FP is not needed.
430 // On PPC64, r13 is the thread pointer. Never allocate this register.
431 // Note that this is over conservative, as it also prevents allocation of R31
432 // when the FP is not needed.
369433 if (Subtarget.isPPC64()) {
370434 Reserved.set(PPC::R13);
371435 Reserved.set(PPC::R31);
377441 Reserved.set(PPC::X1);
378442 Reserved.set(PPC::X13);
379443 Reserved.set(PPC::X31);
444
445 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
446 if (Subtarget.isSVR4ABI()) {
447 Reserved.set(PPC::X2);
448 }
380449 }
381450
382451 if (needsFP(MF))
910979 // don't have a frame pointer, calls, or dynamic alloca then we do not need
911980 // to adjust the stack pointer (we fit in the Red Zone).
912981 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone);
913 // FIXME SVR4 The SVR4 ABI has no red zone.
982 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone.
914983 if (!DisableRedZone &&
915984 FrameSize <= 224 && // Fits in red zone.
916985 !MFI->hasVarSizedObjects() && // No dynamic alloca.
10051074 if (!Subtarget.isSVR4ABI()) {
10061075 return;
10071076 }
1008
1077
10091078 // Get callee saved register information.
10101079 MachineFrameInfo *FFI = MF.getFrameInfo();
10111080 const std::vector &CSI = FFI->getCalleeSavedInfo();
10161085 }
10171086
10181087 unsigned MinGPR = PPC::R31;
1088 unsigned MinG8R = PPC::X31;
10191089 unsigned MinFPR = PPC::F31;
10201090 unsigned MinVR = PPC::V31;
10211091
10221092 bool HasGPSaveArea = false;
1093 bool HasG8SaveArea = false;
10231094 bool HasFPSaveArea = false;
10241095 bool HasCRSaveArea = false;
10251096 bool HasVRSAVESaveArea = false;
10261097 bool HasVRSaveArea = false;
10271098
10281099 SmallVector GPRegs;
1100 SmallVector G8Regs;
10291101 SmallVector FPRegs;
10301102 SmallVector VRegs;
10311103
10401112
10411113 if (Reg < MinGPR) {
10421114 MinGPR = Reg;
1115 }
1116 } else if (RC == PPC::G8RCRegisterClass) {
1117 HasG8SaveArea = true;
1118
1119 G8Regs.push_back(CSI[i]);
1120
1121 if (Reg < MinG8R) {
1122 MinG8R = Reg;
10431123 }
10441124 } else if (RC == PPC::F8RCRegisterClass) {
10451125 HasFPSaveArea = true;
11031183
11041184 // General register save area starts right below the Floating-point
11051185 // register save area.
1106 if (HasGPSaveArea) {
1186 if (HasGPSaveArea || HasG8SaveArea) {
11071187 // Move general register save area spill slots down, taking into account
11081188 // the size of the Floating-point register save area.
11091189 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
11121192 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
11131193 }
11141194
1115 LowerBound -= (31 - getRegisterNumbering(MinGPR) + 1) * 4;
1195 // Move general register save area spill slots down, taking into account
1196 // the size of the Floating-point register save area.
1197 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1198 int FI = G8Regs[i].getFrameIdx();
1199
1200 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1201 }
1202
1203 unsigned MinReg = std::min(getRegisterNumbering(MinGPR),
1204 getRegisterNumbering(MinG8R));
1205
1206 if (Subtarget.isPPC64()) {
1207 LowerBound -= (31 - MinReg + 1) * 8;
1208 } else {
1209 LowerBound -= (31 - MinReg + 1) * 4;
1210 }
11161211 }
11171212
11181213 // The CR save area is below the general register save area.
279279 let MethodBodies = [{
280280 GPRCClass::iterator
281281 GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
282 // In Linux, r2 is reserved for the OS.
282 // 32-bit SVR4 ABI: r2 is reserved for the OS.
283 // 64-bit SVR4 ABI: r2 is reserved for the TOC pointer.
283284 if (!MF.getTarget().getSubtarget().isDarwin())
284285 return begin()+1;
285286
290291 // On PPC64, r13 is the thread pointer. Never allocate this register.
291292 // Note that this is overconservative, as it also prevents allocation of
292293 // R31 when the FP is not needed.
293 // When using the SVR4 ABI, r13 is reserved for the Small Data Area
294 // When using the 32-bit SVR4 ABI, r13 is reserved for the Small Data Area
294295 // pointer.
295296 const PPCSubtarget &Subtarget
296297 = MF.getTarget().getSubtarget();
317318 let MethodBodies = [{
318319 G8RCClass::iterator
319320 G8RCClass::allocation_order_begin(const MachineFunction &MF) const {
321 // 64-bit SVR4 ABI: r2 is reserved for the TOC pointer.
322 if (!MF.getTarget().getSubtarget().isDarwin())
323 return begin()+1;
324
320325 return begin();
321326 }
322327 G8RCClass::iterator
371376 def CTRRC : RegisterClass<"PPC", [i32], 32, [CTR]>;
372377 def CTRRC8 : RegisterClass<"PPC", [i64], 64, [CTR8]>;
373378 def VRSAVERC : RegisterClass<"PPC", [i32], 32, [VRSAVE]>;
374
137137 /// getDarwinVers - Return the darwin version number, 8 = tiger, 9 = leopard.
138138 unsigned getDarwinVers() const { return DarwinVers; }
139139
140 bool isDarwinABI() const { return isDarwin() || IsPPC64; }
141 bool isSVR4ABI() const { return !isDarwin() && !IsPPC64; }
140 bool isDarwinABI() const { return isDarwin(); }
141 bool isSVR4ABI() const { return !isDarwin(); }
142
142143 };
143144 } // End llvm namespace
144145