llvm.org GIT mirror llvm / 6ab1b05
[ARM] Remove MVE masked loads/stores These were never enabled correctly and are causing other problems. Taking them out for the moment, whilst we work on the issues. This reverts r370329. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370607 91177308-0d34-0410-b5e6-96231b3b80d8 David Green 1 year, 23 days ago
6 changed file(s) with 5300 addition(s) and 570 deletion(s). Raw diff Collapse all Expand all
258258 setOperationAction(ISD::UMAX, VT, Legal);
259259 setOperationAction(ISD::ABS, VT, Legal);
260260 setOperationAction(ISD::SETCC, VT, Custom);
261 setOperationAction(ISD::MLOAD, VT, Custom);
262 setOperationAction(ISD::MSTORE, VT, Legal);
263261
264262 // No native support for these.
265263 setOperationAction(ISD::UDIV, VT, Expand);
301299 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
302300 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
303301 setOperationAction(ISD::SETCC, VT, Custom);
304 setOperationAction(ISD::MLOAD, VT, Custom);
305 setOperationAction(ISD::MSTORE, VT, Legal);
306302
307303 // Pre and Post inc are supported on loads and stores
308304 for (unsigned im = (unsigned)ISD::PRE_INC;
87298725 Results.push_back(Upper);
87308726 }
87318727
8732 static SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG) {
8733 MaskedLoadSDNode *N = cast(Op.getNode());
8734 MVT VT = Op.getSimpleValueType();
8735 SDValue Mask = N->getMask();
8736 SDValue PassThru = N->getPassThru();
8737 SDLoc dl(Op);
8738
8739 if (ISD::isBuildVectorAllZeros(PassThru.getNode()) ||
8740 (PassThru->getOpcode() == ARMISD::VMOVIMM &&
8741 isNullConstant(PassThru->getOperand(0))))
8742 return Op;
8743
8744 // MVE Masked loads use zero as the passthru value. Here we convert undef to
8745 // zero too, and other values are lowered to a select.
8746 SDValue ZeroVec = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
8747 DAG.getTargetConstant(0, dl, MVT::i32));
8748 SDValue NewLoad = DAG.getMaskedLoad(
8749 VT, dl, N->getChain(), N->getBasePtr(), Mask, ZeroVec, N->getMemoryVT(),
8750 N->getMemOperand(), N->getExtensionType(), N->isExpandingLoad());
8751 SDValue Combo = NewLoad;
8752 if (!PassThru.isUndef())
8753 Combo = DAG.getNode(ISD::VSELECT, dl, VT, Mask, NewLoad, PassThru);
8754 return DAG.getMergeValues({Combo, NewLoad.getValue(1)}, dl);
8755 }
8756
87578728 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
87588729 if (isStrongerThanMonotonic(cast(Op)->getOrdering()))
87598730 // Acquire/Release load/store is not legal for targets without a dmb or
89538924 case ISD::UADDO:
89548925 case ISD::USUBO:
89558926 return LowerUnsignedALUO(Op, DAG);
8956 case ISD::MLOAD:
8957 return LowerMLOAD(Op, DAG);
89588927 case ISD::ATOMIC_LOAD:
89598928 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
89608929 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
48094809 PatFrag StoreKind, int shift>
48104810 : Pat<(StoreKind (Ty MQPR:$val), t2addrmode_imm7:$addr),
48114811 (RegImmInst (Ty MQPR:$val), t2addrmode_imm7:$addr)>;
4812 class MVE_vector_maskedstore_typed
4813 PatFrag StoreKind, int shift>
4814 : Pat<(StoreKind (Ty MQPR:$val), t2addrmode_imm7:$addr, VCCR:$pred),
4815 (RegImmInst (Ty MQPR:$val), t2addrmode_imm7:$addr, (i32 1), VCCR:$pred)>;
48164812
48174813 multiclass MVE_vector_store
48184814 int shift> {
48294825 PatFrag LoadKind, int shift>
48304826 : Pat<(Ty (LoadKind t2addrmode_imm7:$addr)),
48314827 (Ty (RegImmInst t2addrmode_imm7:$addr))>;
4832 class MVE_vector_maskedload_typed
4833 PatFrag LoadKind, int shift>
4834 : Pat<(Ty (LoadKind t2addrmode_imm7:$addr, VCCR:$pred, (Ty NEONimmAllZerosV))),
4835 (Ty (RegImmInst t2addrmode_imm7:$addr, (i32 1), VCCR:$pred))>;
48364828
48374829 multiclass MVE_vector_load
48384830 int shift> {
48784870 return cast(N)->getAlignment() >= 2;
48794871 }]>;
48804872
4881 def alignedmaskedload32 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
4882 (masked_ld node:$ptr, node:$pred, node:$passthru), [{
4883 return cast(N)->getAlignment() >= 4;
4884 }]>;
4885 def alignedmaskedload16 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
4886 (masked_ld node:$ptr, node:$pred, node:$passthru), [{
4887 return cast(N)->getAlignment() >= 2;
4888 }]>;
4889 def maskedload : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
4890 (masked_ld node:$ptr, node:$pred, node:$passthru)>;
4891
4892 def alignedmaskedstore32 : PatFrag<(ops node:$val, node:$ptr, node:$pred),
4893 (masked_st node:$val, node:$ptr, node:$pred), [{
4894 return cast(N)->getAlignment() >= 4;
4895 }]>;
4896 def alignedmaskedstore16 : PatFrag<(ops node:$val, node:$ptr, node:$pred),
4897 (masked_st node:$val, node:$ptr, node:$pred), [{
4898 return cast(N)->getAlignment() >= 2;
4899 }]>;
4900 def maskedstore : PatFrag<(ops node:$val, node:$ptr, node:$pred),
4901 (masked_st node:$val, node:$ptr, node:$pred)>;
4902
49034873 let Predicates = [HasMVEInt, IsLE] in {
49044874 // Stores
49054875 defm : MVE_vector_store;
49184888 defm : MVE_vector_offset_store;
49194889 defm : MVE_vector_offset_store;
49204890 defm : MVE_vector_offset_store;
4921
4922 // Unaligned masked stores (aligned are below)
4923 def : Pat<(maskedstore (v4i32 MQPR:$val), t2addrmode_imm7<0>:$addr, VCCR:$pred),
4924 (MVE_VSTRBU8 MQPR:$val, t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred)>;
4925 def : Pat<(maskedstore (v4f32 MQPR:$val), t2addrmode_imm7<0>:$addr, VCCR:$pred),
4926 (MVE_VSTRBU8 MQPR:$val, t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred)>;
4927 def : Pat<(maskedstore (v8i16 MQPR:$val), t2addrmode_imm7<0>:$addr, VCCR:$pred),
4928 (MVE_VSTRBU8 MQPR:$val, t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred)>;
4929 def : Pat<(maskedstore (v8f16 MQPR:$val), t2addrmode_imm7<0>:$addr, VCCR:$pred),
4930 (MVE_VSTRBU8 MQPR:$val, t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred)>;
4931
4932 // Unaligned masked loads
4933 def : Pat<(v4i32 (maskedload t2addrmode_imm7<0>:$addr, VCCR:$pred, (v4i32 NEONimmAllZerosV))),
4934 (v4i32 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred))>;
4935 def : Pat<(v4f32 (maskedload t2addrmode_imm7<0>:$addr, VCCR:$pred, (v4f32 NEONimmAllZerosV))),
4936 (v4f32 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred))>;
4937 def : Pat<(v8i16 (maskedload t2addrmode_imm7<0>:$addr, VCCR:$pred, (v8i16 NEONimmAllZerosV))),
4938 (v8i16 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred))>;
4939 def : Pat<(v8f16 (maskedload t2addrmode_imm7<0>:$addr, VCCR:$pred, (v8f16 NEONimmAllZerosV))),
4940 (v8f16 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred))>;
49414891 }
49424892
49434893 let Predicates = [HasMVEInt, IsBE] in {
49924942 def : MVE_vector_offset_store_typed;
49934943 def : MVE_vector_offset_store_typed;
49944944 def : MVE_vector_offset_store_typed;
4995
4996 // Unaligned masked stores (aligned are below)
4997 def : Pat<(maskedstore (v4i32 MQPR:$val), t2addrmode_imm7<0>:$addr, VCCR:$pred),
4998 (MVE_VSTRBU8 (MVE_VREV32_8 MQPR:$val), t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred)>;
4999 def : Pat<(maskedstore (v4f32 MQPR:$val), t2addrmode_imm7<0>:$addr, VCCR:$pred),
5000 (MVE_VSTRBU8 (MVE_VREV32_8 MQPR:$val), t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred)>;
5001 def : Pat<(maskedstore (v8i16 MQPR:$val), t2addrmode_imm7<0>:$addr, VCCR:$pred),
5002 (MVE_VSTRBU8 (MVE_VREV16_8 MQPR:$val), t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred)>;
5003 def : Pat<(maskedstore (v8f16 MQPR:$val), t2addrmode_imm7<0>:$addr, VCCR:$pred),
5004 (MVE_VSTRBU8 (MVE_VREV16_8 MQPR:$val), t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred)>;
5005 // Unaligned masked loads
5006 def : Pat<(v4i32 (maskedload t2addrmode_imm7<0>:$addr, VCCR:$pred, (v4i32 NEONimmAllZerosV))),
5007 (v4i32 (MVE_VREV32_8 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred)))>;
5008 def : Pat<(v4f32 (maskedload t2addrmode_imm7<0>:$addr, VCCR:$pred, (v4f32 NEONimmAllZerosV))),
5009 (v4f32 (MVE_VREV32_8 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred)))>;
5010 def : Pat<(v8i16 (maskedload t2addrmode_imm7<0>:$addr, VCCR:$pred, (v8i16 NEONimmAllZerosV))),
5011 (v8i16 (MVE_VREV16_8 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred)))>;
5012 def : Pat<(v8f16 (maskedload t2addrmode_imm7<0>:$addr, VCCR:$pred, (v8f16 NEONimmAllZerosV))),
5013 (v8f16 (MVE_VREV16_8 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr, (i32 1), VCCR:$pred)))>;
50144945 }
50154946
50164947 let Predicates = [HasMVEInt] in {
5017 // Aligned masked store, shared between LE and BE
5018 def : MVE_vector_maskedstore_typed;
5019 def : MVE_vector_maskedstore_typed;
5020 def : MVE_vector_maskedstore_typed;
5021 def : MVE_vector_maskedstore_typed;
5022 def : MVE_vector_maskedstore_typed;
5023 // Aligned masked loads
5024 def : MVE_vector_maskedload_typed;
5025 def : MVE_vector_maskedload_typed;
5026 def : MVE_vector_maskedload_typed;
5027 def : MVE_vector_maskedload_typed;
5028 def : MVE_vector_maskedload_typed;
5029
50304948 // Predicate loads
50314949 def : Pat<(v16i1 (load t2addrmode_imm7<2>:$addr)),
50324950 (v16i1 (VLDR_P0_off t2addrmode_imm7<2>:$addr))>;
105105 return !ST->isTargetDarwin() && !ST->hasMVEFloatOps();
106106 }
107107
108 bool isLegalMaskedLoad(Type *DataTy) {
109 if (!ST->hasMVEIntegerOps())
110 return false;
111
112 unsigned VecWidth = DataTy->getPrimitiveSizeInBits();
113 if (VecWidth != 128)
114 return false;
115
116 unsigned EltWidth = DataTy->getScalarSizeInBits();
117 return EltWidth == 32 || EltWidth == 16 || EltWidth == 8;
118 }
119
120 bool isLegalMaskedStore(Type *DataTy) { return isLegalMaskedLoad(DataTy); }
121
122108 /// \name Scalar TTI Implementations
123109 /// @{
124110
44 define void @foo_v4i32_v4i32(<4 x i32> *%dest, <4 x i32> *%mask, <4 x i32> *%src) {
55 ; CHECK-LABEL: foo_v4i32_v4i32:
66 ; CHECK: @ %bb.0: @ %entry
7 ; CHECK-NEXT: .pad #8
8 ; CHECK-NEXT: sub sp, #8
79 ; CHECK-NEXT: vldrw.u32 q0, [r1]
10 ; CHECK-NEXT: add r3, sp, #4
811 ; CHECK-NEXT: vcmp.s32 gt, q0, zr
9 ; CHECK-NEXT: vpstt
10 ; CHECK-NEXT: vldrwt.u32 q0, [r2]
11 ; CHECK-NEXT: vstrwt.32 q0, [r0]
12 ; CHECK-NEXT: @ implicit-def: $q0
13 ; CHECK-NEXT: vstr p0, [r3]
14 ; CHECK-NEXT: ldrb.w r1, [sp, #4]
15 ; CHECK-NEXT: lsls r3, r1, #31
16 ; CHECK-NEXT: itt ne
17 ; CHECK-NEXT: ldrne r3, [r2]
18 ; CHECK-NEXT: vmovne.32 q0[0], r3
19 ; CHECK-NEXT: lsls r3, r1, #30
20 ; CHECK-NEXT: itt mi
21 ; CHECK-NEXT: ldrmi r3, [r2, #4]
22 ; CHECK-NEXT: vmovmi.32 q0[1], r3
23 ; CHECK-NEXT: lsls r3, r1, #29
24 ; CHECK-NEXT: itt mi
25 ; CHECK-NEXT: ldrmi r3, [r2, #8]
26 ; CHECK-NEXT: vmovmi.32 q0[2], r3
27 ; CHECK-NEXT: lsls r1, r1, #28
28 ; CHECK-NEXT: itt mi
29 ; CHECK-NEXT: ldrmi r1, [r2, #12]
30 ; CHECK-NEXT: vmovmi.32 q0[3], r1
31 ; CHECK-NEXT: mov r1, sp
32 ; CHECK-NEXT: vstr p0, [r1]
33 ; CHECK-NEXT: ldrb.w r1, [sp]
34 ; CHECK-NEXT: lsls r2, r1, #31
35 ; CHECK-NEXT: itt ne
36 ; CHECK-NEXT: vmovne r2, s0
37 ; CHECK-NEXT: strne r2, [r0]
38 ; CHECK-NEXT: lsls r2, r1, #30
39 ; CHECK-NEXT: itt mi
40 ; CHECK-NEXT: vmovmi r2, s1
41 ; CHECK-NEXT: strmi r2, [r0, #4]
42 ; CHECK-NEXT: lsls r2, r1, #29
43 ; CHECK-NEXT: itt mi
44 ; CHECK-NEXT: vmovmi r2, s2
45 ; CHECK-NEXT: strmi r2, [r0, #8]
46 ; CHECK-NEXT: lsls r1, r1, #28
47 ; CHECK-NEXT: itt mi
48 ; CHECK-NEXT: vmovmi r1, s3
49 ; CHECK-NEXT: strmi r1, [r0, #12]
50 ; CHECK-NEXT: add sp, #8
1251 ; CHECK-NEXT: bx lr
1352 entry:
1453 %0 = load <4 x i32>, <4 x i32>* %mask, align 4
2160 define void @foo_sext_v4i32_v4i8(<4 x i32> *%dest, <4 x i32> *%mask, <4 x i8> *%src) {
2261 ; CHECK-LABEL: foo_sext_v4i32_v4i8:
2362 ; CHECK: @ %bb.0: @ %entry
24 ; CHECK-NEXT: .pad #4
25 ; CHECK-NEXT: sub sp, #4
63 ; CHECK-NEXT: .pad #8
64 ; CHECK-NEXT: sub sp, #8
2665 ; CHECK-NEXT: vldrw.u32 q0, [r1]
27 ; CHECK-NEXT: mov r3, sp
66 ; CHECK-NEXT: add r3, sp, #4
2867 ; CHECK-NEXT: vcmp.s32 gt, q0, zr
2968 ; CHECK-NEXT: @ implicit-def: $q0
3069 ; CHECK-NEXT: vstr p0, [r3]
31 ; CHECK-NEXT: ldrb.w r1, [sp]
70 ; CHECK-NEXT: ldrb.w r1, [sp, #4]
3271 ; CHECK-NEXT: lsls r3, r1, #31
3372 ; CHECK-NEXT: itt ne
3473 ; CHECK-NEXT: ldrbne r3, [r2]
4584 ; CHECK-NEXT: itt mi
4685 ; CHECK-NEXT: ldrbmi r1, [r2, #3]
4786 ; CHECK-NEXT: vmovmi.32 q0[3], r1
87 ; CHECK-NEXT: mov r1, sp
4888 ; CHECK-NEXT: vmovlb.s8 q0, q0
89 ; CHECK-NEXT: vstr p0, [r1]
4990 ; CHECK-NEXT: vmovlb.s16 q0, q0
50 ; CHECK-NEXT: vpst
51 ; CHECK-NEXT: vstrwt.32 q0, [r0]
52 ; CHECK-NEXT: add sp, #4
91 ; CHECK-NEXT: ldrb.w r1, [sp]
92 ; CHECK-NEXT: lsls r2, r1, #31
93 ; CHECK-NEXT: itt ne
94 ; CHECK-NEXT: vmovne r2, s0
95 ; CHECK-NEXT: strne r2, [r0]
96 ; CHECK-NEXT: lsls r2, r1, #30
97 ; CHECK-NEXT: itt mi
98 ; CHECK-NEXT: vmovmi r2, s1
99 ; CHECK-NEXT: strmi r2, [r0, #4]
100 ; CHECK-NEXT: lsls r2, r1, #29
101 ; CHECK-NEXT: itt mi
102 ; CHECK-NEXT: vmovmi r2, s2
103 ; CHECK-NEXT: strmi r2, [r0, #8]
104 ; CHECK-NEXT: lsls r1, r1, #28
105 ; CHECK-NEXT: itt mi
106 ; CHECK-NEXT: vmovmi r1, s3
107 ; CHECK-NEXT: strmi r1, [r0, #12]
108 ; CHECK-NEXT: add sp, #8
53109 ; CHECK-NEXT: bx lr
54110 entry:
55111 %0 = load <4 x i32>, <4 x i32>* %mask, align 4
63119 define void @foo_sext_v4i32_v4i16(<4 x i32> *%dest, <4 x i32> *%mask, <4 x i16> *%src) {
64120 ; CHECK-LABEL: foo_sext_v4i32_v4i16:
65121 ; CHECK: @ %bb.0: @ %entry
66 ; CHECK-NEXT: .pad #4
67 ; CHECK-NEXT: sub sp, #4
122 ; CHECK-NEXT: .pad #8
123 ; CHECK-NEXT: sub sp, #8
68124 ; CHECK-NEXT: vldrw.u32 q0, [r1]
69 ; CHECK-NEXT: mov r3, sp
125 ; CHECK-NEXT: add r3, sp, #4
70126 ; CHECK-NEXT: vcmp.s32 gt, q0, zr
71127 ; CHECK-NEXT: @ implicit-def: $q0
72128 ; CHECK-NEXT: vstr p0, [r3]
73 ; CHECK-NEXT: ldrb.w r1, [sp]
129 ; CHECK-NEXT: ldrb.w r1, [sp, #4]
74130 ; CHECK-NEXT: lsls r3, r1, #31
75131 ; CHECK-NEXT: itt ne
76132 ; CHECK-NEXT: ldrhne r3, [r2]
87143 ; CHECK-NEXT: itt mi
88144 ; CHECK-NEXT: ldrhmi r1, [r2, #6]
89145 ; CHECK-NEXT: vmovmi.32 q0[3], r1
146 ; CHECK-NEXT: mov r1, sp
90147 ; CHECK-NEXT: vmovlb.s16 q0, q0
91 ; CHECK-NEXT: vpst
92 ; CHECK-NEXT: vstrwt.32 q0, [r0]
93 ; CHECK-NEXT: add sp, #4
148 ; CHECK-NEXT: vstr p0, [r1]
149 ; CHECK-NEXT: ldrb.w r1, [sp]
150 ; CHECK-NEXT: lsls r2, r1, #31
151 ; CHECK-NEXT: itt ne
152 ; CHECK-NEXT: vmovne r2, s0
153 ; CHECK-NEXT: strne r2, [r0]
154 ; CHECK-NEXT: lsls r2, r1, #30
155 ; CHECK-NEXT: itt mi
156 ; CHECK-NEXT: vmovmi r2, s1
157 ; CHECK-NEXT: strmi r2, [r0, #4]
158 ; CHECK-NEXT: lsls r2, r1, #29
159 ; CHECK-NEXT: itt mi
160 ; CHECK-NEXT: vmovmi r2, s2
161 ; CHECK-NEXT: strmi r2, [r0, #8]
162 ; CHECK-NEXT: lsls r1, r1, #28
163 ; CHECK-NEXT: itt mi
164 ; CHECK-NEXT: vmovmi r1, s3
165 ; CHECK-NEXT: strmi r1, [r0, #12]
166 ; CHECK-NEXT: add sp, #8
94167 ; CHECK-NEXT: bx lr
95168 entry:
96169 %0 = load <4 x i32>, <4 x i32>* %mask, align 4
104177 define void @foo_zext_v4i32_v4i8(<4 x i32> *%dest, <4 x i32> *%mask, <4 x i8> *%src) {
105178 ; CHECK-LABEL: foo_zext_v4i32_v4i8:
106179 ; CHECK: @ %bb.0: @ %entry
107 ; CHECK-NEXT: .pad #4
108 ; CHECK-NEXT: sub sp, #4
180 ; CHECK-NEXT: .pad #8
181 ; CHECK-NEXT: sub sp, #8
109182 ; CHECK-NEXT: vldrw.u32 q0, [r1]
110 ; CHECK-NEXT: mov r3, sp
183 ; CHECK-NEXT: add r3, sp, #4
111184 ; CHECK-NEXT: vmov.i32 q1, #0xff
112185 ; CHECK-NEXT: vcmp.s32 gt, q0, zr
113186 ; CHECK-NEXT: @ implicit-def: $q0
114187 ; CHECK-NEXT: vstr p0, [r3]
115 ; CHECK-NEXT: ldrb.w r1, [sp]
188 ; CHECK-NEXT: ldrb.w r1, [sp, #4]
116189 ; CHECK-NEXT: lsls r3, r1, #31
117190 ; CHECK-NEXT: itt ne
118191 ; CHECK-NEXT: ldrbne r3, [r2]
129202 ; CHECK-NEXT: itt mi
130203 ; CHECK-NEXT: ldrbmi r1, [r2, #3]
131204 ; CHECK-NEXT: vmovmi.32 q0[3], r1
205 ; CHECK-NEXT: mov r1, sp
132206 ; CHECK-NEXT: vand q0, q0, q1
133 ; CHECK-NEXT: vpst
134 ; CHECK-NEXT: vstrwt.32 q0, [r0]
135 ; CHECK-NEXT: add sp, #4
207 ; CHECK-NEXT: vstr p0, [r1]
208 ; CHECK-NEXT: ldrb.w r1, [sp]
209 ; CHECK-NEXT: lsls r2, r1, #31
210 ; CHECK-NEXT: itt ne
211 ; CHECK-NEXT: vmovne r2, s0
212 ; CHECK-NEXT: strne r2, [r0]
213 ; CHECK-NEXT: lsls r2, r1, #30
214 ; CHECK-NEXT: itt mi
215 ; CHECK-NEXT: vmovmi r2, s1
216 ; CHECK-NEXT: strmi r2, [r0, #4]
217 ; CHECK-NEXT: lsls r2, r1, #29
218 ; CHECK-NEXT: itt mi
219 ; CHECK-NEXT: vmovmi r2, s2
220 ; CHECK-NEXT: strmi r2, [r0, #8]
221 ; CHECK-NEXT: lsls r1, r1, #28
222 ; CHECK-NEXT: itt mi
223 ; CHECK-NEXT: vmovmi r1, s3
224 ; CHECK-NEXT: strmi r1, [r0, #12]
225 ; CHECK-NEXT: add sp, #8
136226 ; CHECK-NEXT: bx lr
137227 entry:
138228 %0 = load <4 x i32>, <4 x i32>* %mask, align 4
146236 define void @foo_zext_v4i32_v4i16(<4 x i32> *%dest, <4 x i32> *%mask, <4 x i16> *%src) {
147237 ; CHECK-LABEL: foo_zext_v4i32_v4i16:
148238 ; CHECK: @ %bb.0: @ %entry
149 ; CHECK-NEXT: .pad #4
150 ; CHECK-NEXT: sub sp, #4
239 ; CHECK-NEXT: .pad #8
240 ; CHECK-NEXT: sub sp, #8
151241 ; CHECK-NEXT: vldrw.u32 q0, [r1]
152 ; CHECK-NEXT: mov r3, sp
242 ; CHECK-NEXT: add r3, sp, #4
153243 ; CHECK-NEXT: vcmp.s32 gt, q0, zr
154244 ; CHECK-NEXT: @ implicit-def: $q0
155245 ; CHECK-NEXT: vstr p0, [r3]
156 ; CHECK-NEXT: ldrb.w r1, [sp]
246 ; CHECK-NEXT: ldrb.w r1, [sp, #4]
157247 ; CHECK-NEXT: lsls r3, r1, #31
158248 ; CHECK-NEXT: itt ne
159249 ; CHECK-NEXT: ldrhne r3, [r2]
170260 ; CHECK-NEXT: itt mi
171261 ; CHECK-NEXT: ldrhmi r1, [r2, #6]
172262 ; CHECK-NEXT: vmovmi.32 q0[3], r1
263 ; CHECK-NEXT: mov r1, sp
173264 ; CHECK-NEXT: vmovlb.u16 q0, q0
174 ; CHECK-NEXT: vpst
175 ; CHECK-NEXT: vstrwt.32 q0, [r0]
176 ; CHECK-NEXT: add sp, #4
265 ; CHECK-NEXT: vstr p0, [r1]
266 ; CHECK-NEXT: ldrb.w r1, [sp]
267 ; CHECK-NEXT: lsls r2, r1, #31
268 ; CHECK-NEXT: itt ne
269 ; CHECK-NEXT: vmovne r2, s0
270 ; CHECK-NEXT: strne r2, [r0]
271 ; CHECK-NEXT: lsls r2, r1, #30
272 ; CHECK-NEXT: itt mi
273 ; CHECK-NEXT: vmovmi r2, s1
274 ; CHECK-NEXT: strmi r2, [r0, #4]
275 ; CHECK-NEXT: lsls r2, r1, #29
276 ; CHECK-NEXT: itt mi
277 ; CHECK-NEXT: vmovmi r2, s2
278 ; CHECK-NEXT: strmi r2, [r0, #8]
279 ; CHECK-NEXT: lsls r1, r1, #28
280 ; CHECK-NEXT: itt mi
281 ; CHECK-NEXT: vmovmi r1, s3
282 ; CHECK-NEXT: strmi r1, [r0, #12]
283 ; CHECK-NEXT: add sp, #8
177284 ; CHECK-NEXT: bx lr
178285 entry:
179286 %0 = load <4 x i32>, <4 x i32>* %mask, align 4
187294 define void @foo_v8i16_v8i16(<8 x i16> *%dest, <8 x i16> *%mask, <8 x i16> *%src) {
188295 ; CHECK-LABEL: foo_v8i16_v8i16:
189296 ; CHECK: @ %bb.0: @ %entry
297 ; CHECK-NEXT: .pad #16
298 ; CHECK-NEXT: sub sp, #16
190299 ; CHECK-NEXT: vldrh.u16 q0, [r1]
300 ; CHECK-NEXT: add r3, sp, #8
191301 ; CHECK-NEXT: vcmp.s16 gt, q0, zr
192 ; CHECK-NEXT: vpstt
193 ; CHECK-NEXT: vldrht.u16 q0, [r2]
194 ; CHECK-NEXT: vstrht.16 q0, [r0]
302 ; CHECK-NEXT: @ implicit-def: $q0
303 ; CHECK-NEXT: vstr p0, [r3]
304 ; CHECK-NEXT: ldrb.w r1, [sp, #8]
305 ; CHECK-NEXT: lsls r3, r1, #31
306 ; CHECK-NEXT: itt ne
307 ; CHECK-NEXT: ldrhne r3, [r2]
308 ; CHECK-NEXT: vmovne.16 q0[0], r3
309 ; CHECK-NEXT: lsls r3, r1, #30
310 ; CHECK-NEXT: itt mi
311 ; CHECK-NEXT: ldrhmi r3, [r2, #2]
312 ; CHECK-NEXT: vmovmi.16 q0[1], r3
313 ; CHECK-NEXT: lsls r3, r1, #29
314 ; CHECK-NEXT: itt mi
315 ; CHECK-NEXT: ldrhmi r3, [r2, #4]
316 ; CHECK-NEXT: vmovmi.16 q0[2], r3
317 ; CHECK-NEXT: lsls r3, r1, #28
318 ; CHECK-NEXT: itt mi
319 ; CHECK-NEXT: ldrhmi r3, [r2, #6]
320 ; CHECK-NEXT: vmovmi.16 q0[3], r3
321 ; CHECK-NEXT: lsls r3, r1, #27
322 ; CHECK-NEXT: itt mi
323 ; CHECK-NEXT: ldrhmi r3, [r2, #8]
324 ; CHECK-NEXT: vmovmi.16 q0[4], r3
325 ; CHECK-NEXT: lsls r3, r1, #26
326 ; CHECK-NEXT: itt mi
327 ; CHECK-NEXT: ldrhmi r3, [r2, #10]
328 ; CHECK-NEXT: vmovmi.16 q0[5], r3
329 ; CHECK-NEXT: lsls r3, r1, #25
330 ; CHECK-NEXT: itt mi
331 ; CHECK-NEXT: ldrhmi r3, [r2, #12]
332 ; CHECK-NEXT: vmovmi.16 q0[6], r3
333 ; CHECK-NEXT: lsls r1, r1, #24
334 ; CHECK-NEXT: itt mi
335 ; CHECK-NEXT: ldrhmi r1, [r2, #14]
336 ; CHECK-NEXT: vmovmi.16 q0[7], r1
337 ; CHECK-NEXT: mov r1, sp
338 ; CHECK-NEXT: vstr p0, [r1]
339 ; CHECK-NEXT: ldrb.w r1, [sp]
340 ; CHECK-NEXT: lsls r2, r1, #31
341 ; CHECK-NEXT: itt ne
342 ; CHECK-NEXT: vmovne.u16 r2, q0[0]
343 ; CHECK-NEXT: strhne r2, [r0]
344 ; CHECK-NEXT: lsls r2, r1, #30
345 ; CHECK-NEXT: itt mi
346 ; CHECK-NEXT: vmovmi.u16 r2, q0[1]
347 ; CHECK-NEXT: strhmi r2, [r0, #2]
348 ; CHECK-NEXT: lsls r2, r1, #29
349 ; CHECK-NEXT: itt mi
350 ; CHECK-NEXT: vmovmi.u16 r2, q0[2]
351 ; CHECK-NEXT: strhmi r2, [r0, #4]
352 ; CHECK-NEXT: lsls r2, r1, #28
353 ; CHECK-NEXT: itt mi
354 ; CHECK-NEXT: vmovmi.u16 r2, q0[3]
355 ; CHECK-NEXT: strhmi r2, [r0, #6]
356 ; CHECK-NEXT: lsls r2, r1, #27
357 ; CHECK-NEXT: itt mi
358 ; CHECK-NEXT: vmovmi.u16 r2, q0[4]
359 ; CHECK-NEXT: strhmi r2, [r0, #8]
360 ; CHECK-NEXT: lsls r2, r1, #26
361 ; CHECK-NEXT: itt mi
362 ; CHECK-NEXT: vmovmi.u16 r2, q0[5]
363 ; CHECK-NEXT: strhmi r2, [r0, #10]
364 ; CHECK-NEXT: lsls r2, r1, #25
365 ; CHECK-NEXT: itt mi
366 ; CHECK-NEXT: vmovmi.u16 r2, q0[6]
367 ; CHECK-NEXT: strhmi r2, [r0, #12]
368 ; CHECK-NEXT: lsls r1, r1, #24
369 ; CHECK-NEXT: itt mi
370 ; CHECK-NEXT: vmovmi.u16 r1, q0[7]
371 ; CHECK-NEXT: strhmi r1, [r0, #14]
372 ; CHECK-NEXT: add sp, #16
195373 ; CHECK-NEXT: bx lr
196374 entry:
197375 %0 = load <8 x i16>, <8 x i16>* %mask, align 2
204382 define void @foo_sext_v8i16_v8i8(<8 x i16> *%dest, <8 x i16> *%mask, <8 x i8> *%src) {
205383 ; CHECK-LABEL: foo_sext_v8i16_v8i8:
206384 ; CHECK: @ %bb.0: @ %entry
207 ; CHECK-NEXT: .pad #8
208 ; CHECK-NEXT: sub sp, #8
385 ; CHECK-NEXT: .pad #16
386 ; CHECK-NEXT: sub sp, #16
209387 ; CHECK-NEXT: vldrh.u16 q0, [r1]
210 ; CHECK-NEXT: mov r3, sp
388 ; CHECK-NEXT: add r3, sp, #8
211389 ; CHECK-NEXT: vcmp.s16 gt, q0, zr
212390 ; CHECK-NEXT: @ implicit-def: $q0
213391 ; CHECK-NEXT: vstr p0, [r3]
214 ; CHECK-NEXT: ldrb.w r1, [sp]
392 ; CHECK-NEXT: ldrb.w r1, [sp, #8]
215393 ; CHECK-NEXT: lsls r3, r1, #31
216394 ; CHECK-NEXT: itt ne
217395 ; CHECK-NEXT: ldrbne r3, [r2]
244422 ; CHECK-NEXT: itt mi
245423 ; CHECK-NEXT: ldrbmi r1, [r2, #7]
246424 ; CHECK-NEXT: vmovmi.16 q0[7], r1
425 ; CHECK-NEXT: mov r1, sp
247426 ; CHECK-NEXT: vmovlb.s8 q0, q0
248 ; CHECK-NEXT: vpst
249 ; CHECK-NEXT: vstrht.16 q0, [r0]
250 ; CHECK-NEXT: add sp, #8
427 ; CHECK-NEXT: vstr p0, [r1]
428 ; CHECK-NEXT: ldrb.w r1, [sp]
429 ; CHECK-NEXT: lsls r2, r1, #31
430 ; CHECK-NEXT: itt ne
431 ; CHECK-NEXT: vmovne.u16 r2, q0[0]
432 ; CHECK-NEXT: strhne r2, [r0]
433 ; CHECK-NEXT: lsls r2, r1, #30
434 ; CHECK-NEXT: itt mi
435 ; CHECK-NEXT: vmovmi.u16 r2, q0[1]
436 ; CHECK-NEXT: strhmi r2, [r0, #2]
437 ; CHECK-NEXT: lsls r2, r1, #29
438 ; CHECK-NEXT: itt mi
439 ; CHECK-NEXT: vmovmi.u16 r2, q0[2]
440 ; CHECK-NEXT: strhmi r2, [r0, #4]
441 ; CHECK-NEXT: lsls r2, r1, #28
442 ; CHECK-NEXT: itt mi
443 ; CHECK-NEXT: vmovmi.u16 r2, q0[3]
444 ; CHECK-NEXT: strhmi r2, [r0, #6]
445 ; CHECK-NEXT: lsls r2, r1, #27
446 ; CHECK-NEXT: itt mi
447 ; CHECK-NEXT: vmovmi.u16 r2, q0[4]
448 ; CHECK-NEXT: strhmi r2, [r0, #8]
449 ; CHECK-NEXT: lsls r2, r1, #26
450 ; CHECK-NEXT: itt mi
451 ; CHECK-NEXT: vmovmi.u16 r2, q0[5]
452 ; CHECK-NEXT: strhmi r2, [r0, #10]
453 ; CHECK-NEXT: lsls r2, r1, #25
454 ; CHECK-NEXT: itt mi
455 ; CHECK-NEXT: vmovmi.u16 r2, q0[6]
456 ; CHECK-NEXT: strhmi r2, [r0, #12]
457 ; CHECK-NEXT: lsls r1, r1, #24
458 ; CHECK-NEXT: itt mi
459 ; CHECK-NEXT: vmovmi.u16 r1, q0[7]
460 ; CHECK-NEXT: strhmi r1, [r0, #14]
461 ; CHECK-NEXT: add sp, #16
251462 ; CHECK-NEXT: bx lr
252463 entry:
253464 %0 = load <8 x i16>, <8 x i16>* %mask, align 2
261472 define void @foo_zext_v8i16_v8i8(<8 x i16> *%dest, <8 x i16> *%mask, <8 x i8> *%src) {
262473 ; CHECK-LABEL: foo_zext_v8i16_v8i8:
263474 ; CHECK: @ %bb.0: @ %entry
264 ; CHECK-NEXT: .pad #8
265 ; CHECK-NEXT: sub sp, #8
475 ; CHECK-NEXT: .pad #16
476 ; CHECK-NEXT: sub sp, #16
266477 ; CHECK-NEXT: vldrh.u16 q0, [r1]
267 ; CHECK-NEXT: mov r3, sp
478 ; CHECK-NEXT: add r3, sp, #8
268479 ; CHECK-NEXT: vcmp.s16 gt, q0, zr
269480 ; CHECK-NEXT: @ implicit-def: $q0
270481 ; CHECK-NEXT: vstr p0, [r3]
271 ; CHECK-NEXT: ldrb.w r1, [sp]
482 ; CHECK-NEXT: ldrb.w r1, [sp, #8]
272483 ; CHECK-NEXT: lsls r3, r1, #31
273484 ; CHECK-NEXT: itt ne
274485 ; CHECK-NEXT: ldrbne r3, [r2]
301512 ; CHECK-NEXT: itt mi
302513 ; CHECK-NEXT: ldrbmi r1, [r2, #7]
303514 ; CHECK-NEXT: vmovmi.16 q0[7], r1
515 ; CHECK-NEXT: mov r1, sp
304516 ; CHECK-NEXT: vmovlb.u8 q0, q0
305 ; CHECK-NEXT: vpst
306 ; CHECK-NEXT: vstrht.16 q0, [r0]
307 ; CHECK-NEXT: add sp, #8
517 ; CHECK-NEXT: vstr p0, [r1]
518 ; CHECK-NEXT: ldrb.w r1, [sp]
519 ; CHECK-NEXT: lsls r2, r1, #31
520 ; CHECK-NEXT: itt ne
521 ; CHECK-NEXT: vmovne.u16 r2, q0[0]
522 ; CHECK-NEXT: strhne r2, [r0]
523 ; CHECK-NEXT: lsls r2, r1, #30
524 ; CHECK-NEXT: itt mi
525 ; CHECK-NEXT: vmovmi.u16 r2, q0[1]
526 ; CHECK-NEXT: strhmi r2, [r0, #2]
527 ; CHECK-NEXT: lsls r2, r1, #29
528 ; CHECK-NEXT: itt mi
529 ; CHECK-NEXT: vmovmi.u16 r2, q0[2]
530 ; CHECK-NEXT: strhmi r2, [r0, #4]
531 ; CHECK-NEXT: lsls r2, r1, #28
532 ; CHECK-NEXT: itt mi
533 ; CHECK-NEXT: vmovmi.u16 r2, q0[3]
534 ; CHECK-NEXT: strhmi r2, [r0, #6]
535 ; CHECK-NEXT: lsls r2, r1, #27
536 ; CHECK-NEXT: itt mi
537 ; CHECK-NEXT: vmovmi.u16 r2, q0[4]
538 ; CHECK-NEXT: strhmi r2, [r0, #8]
539 ; CHECK-NEXT: lsls r2, r1, #26
540 ; CHECK-NEXT: itt mi
541 ; CHECK-NEXT: vmovmi.u16 r2, q0[5]
542 ; CHECK-NEXT: strhmi r2, [r0, #10]
543 ; CHECK-NEXT: lsls r2, r1, #25
544 ; CHECK-NEXT: itt mi
545 ; CHECK-NEXT: vmovmi.u16 r2, q0[6]
546 ; CHECK-NEXT: strhmi r2, [r0, #12]
547 ; CHECK-NEXT: lsls r1, r1, #24
548 ; CHECK-NEXT: itt mi
549 ; CHECK-NEXT: vmovmi.u16 r1, q0[7]
550 ; CHECK-NEXT: strhmi r1, [r0, #14]
551 ; CHECK-NEXT: add sp, #16
308552 ; CHECK-NEXT: bx lr
309553 entry:
310554 %0 = load <8 x i16>, <8 x i16>* %mask, align 2
318562 define void @foo_v16i8_v16i8(<16 x i8> *%dest, <16 x i8> *%mask, <16 x i8> *%src) {
319563 ; CHECK-LABEL: foo_v16i8_v16i8:
320564 ; CHECK: @ %bb.0: @ %entry
565 ; CHECK-NEXT: .save {r4, r6, r7, lr}
566 ; CHECK-NEXT: push {r4, r6, r7, lr}
567 ; CHECK-NEXT: .setfp r7, sp, #8
568 ; CHECK-NEXT: add r7, sp, #8
569 ; CHECK-NEXT: .pad #32
570 ; CHECK-NEXT: sub sp, #32
571 ; CHECK-NEXT: mov r4, sp
572 ; CHECK-NEXT: bfc r4, #0, #4
573 ; CHECK-NEXT: mov sp, r4
321574 ; CHECK-NEXT: vldrb.u8 q0, [r1]
575 ; CHECK-NEXT: add r3, sp, #16
576 ; CHECK-NEXT: sub.w r4, r7, #8
322577 ; CHECK-NEXT: vcmp.s8 gt, q0, zr
323 ; CHECK-NEXT: vpstt
324 ; CHECK-NEXT: vldrbt.u8 q0, [r2]
325 ; CHECK-NEXT: vstrbt.8 q0, [r0]
326 ; CHECK-NEXT: bx lr
578 ; CHECK-NEXT: @ implicit-def: $q0
579 ; CHECK-NEXT: vstr p0, [r3]
580 ; CHECK-NEXT: ldrh.w r1, [sp, #16]
581 ; CHECK-NEXT: lsls r3, r1, #31
582 ; CHECK-NEXT: itt ne
583 ; CHECK-NEXT: ldrbne r3, [r2]
584 ; CHECK-NEXT: vmovne.8 q0[0], r3
585 ; CHECK-NEXT: lsls r3, r1, #30
586 ; CHECK-NEXT: itt mi
587 ; CHECK-NEXT: ldrbmi r3, [r2, #1]
588 ; CHECK-NEXT: vmovmi.8 q0[1], r3
589 ; CHECK-NEXT: lsls r3, r1, #29
590 ; CHECK-NEXT: itt mi
591 ; CHECK-NEXT: ldrbmi r3, [r2, #2]
592 ; CHECK-NEXT: vmovmi.8 q0[2], r3
593 ; CHECK-NEXT: lsls r3, r1, #28
594 ; CHECK-NEXT: itt mi
595 ; CHECK-NEXT: ldrbmi r3, [r2, #3]
596 ; CHECK-NEXT: vmovmi.8 q0[3], r3
597 ; CHECK-NEXT: lsls r3, r1, #27
598 ; CHECK-NEXT: itt mi
599 ; CHECK-NEXT: ldrbmi r3, [r2, #4]
600 ; CHECK-NEXT: vmovmi.8 q0[4], r3
601 ; CHECK-NEXT: lsls r3, r1, #26
602 ; CHECK-NEXT: itt mi
603 ; CHECK-NEXT: ldrbmi r3, [r2, #5]
604 ; CHECK-NEXT: vmovmi.8 q0[5], r3
605 ; CHECK-NEXT: lsls r3, r1, #25
606 ; CHECK-NEXT: itt mi
607 ; CHECK-NEXT: ldrbmi r3, [r2, #6]
608 ; CHECK-NEXT: vmovmi.8 q0[6], r3
609 ; CHECK-NEXT: lsls r3, r1, #24
610 ; CHECK-NEXT: itt mi
611 ; CHECK-NEXT: ldrbmi r3, [r2, #7]
612 ; CHECK-NEXT: vmovmi.8 q0[7], r3
613 ; CHECK-NEXT: lsls r3, r1, #23
614 ; CHECK-NEXT: itt mi
615 ; CHECK-NEXT: ldrbmi r3, [r2, #8]
616 ; CHECK-NEXT: vmovmi.8 q0[8], r3
617 ; CHECK-NEXT: lsls r3, r1, #22
618 ; CHECK-NEXT: itt mi
619 ; CHECK-NEXT: ldrbmi r3, [r2, #9]
620 ; CHECK-NEXT: vmovmi.8 q0[9], r3
621 ; CHECK-NEXT: lsls r3, r1, #21
622 ; CHECK-NEXT: itt mi
623 ; CHECK-NEXT: ldrbmi r3, [r2, #10]
624 ; CHECK-NEXT: vmovmi.8 q0[10], r3
625 ; CHECK-NEXT: lsls r3, r1, #20
626 ; CHECK-NEXT: itt mi
627 ; CHECK-NEXT: ldrbmi r3, [r2, #11]
628 ; CHECK-NEXT: vmovmi.8 q0[11], r3
629 ; CHECK-NEXT: lsls r3, r1, #19
630 ; CHECK-NEXT: itt mi
631 ; CHECK-NEXT: ldrbmi r3, [r2, #12]
632 ; CHECK-NEXT: vmovmi.8 q0[12], r3
633 ; CHECK-NEXT: lsls r3, r1, #18
634 ; CHECK-NEXT: itt mi
635 ; CHECK-NEXT: ldrbmi r3, [r2, #13]
636 ; CHECK-NEXT: vmovmi.8 q0[13], r3
637 ; CHECK-NEXT: lsls r3, r1, #17
638 ; CHECK-NEXT: itt mi
639 ; CHECK-NEXT: ldrbmi r3, [r2, #14]
640 ; CHECK-NEXT: vmovmi.8 q0[14], r3
641 ; CHECK-NEXT: lsls r1, r1, #16
642 ; CHECK-NEXT: itt mi
643 ; CHECK-NEXT: ldrbmi r1, [r2, #15]
644 ; CHECK-NEXT: vmovmi.8 q0[15], r1
645 ; CHECK-NEXT: mov r1, sp
646 ; CHECK-NEXT: vstr p0, [r1]
647 ; CHECK-NEXT: ldrh.w r1, [sp]
648 ; CHECK-NEXT: lsls r2, r1, #31
649 ; CHECK-NEXT: itt ne
650 ; CHECK-NEXT: vmovne.u8 r2, q0[0]
651 ; CHECK-NEXT: strbne r2, [r0]
652 ; CHECK-NEXT: lsls r2, r1, #30
653 ; CHECK-NEXT: itt mi
654 ; CHECK-NEXT: vmovmi.u8 r2, q0[1]
655 ; CHECK-NEXT: strbmi r2, [r0, #1]
656 ; CHECK-NEXT: lsls r2, r1, #29
657 ; CHECK-NEXT: itt mi
658 ; CHECK-NEXT: vmovmi.u8 r2, q0[2]
659 ; CHECK-NEXT: strbmi r2, [r0, #2]
660 ; CHECK-NEXT: lsls r2, r1, #28
661 ; CHECK-NEXT: itt mi
662 ; CHECK-NEXT: vmovmi.u8 r2, q0[3]
663 ; CHECK-NEXT: strbmi r2, [r0, #3]
664 ; CHECK-NEXT: lsls r2, r1, #27
665 ; CHECK-NEXT: itt mi
666 ; CHECK-NEXT: vmovmi.u8 r2, q0[4]
667 ; CHECK-NEXT: strbmi r2, [r0, #4]
668 ; CHECK-NEXT: lsls r2, r1, #26
669 ; CHECK-NEXT: itt mi
670 ; CHECK-NEXT: vmovmi.u8 r2, q0[5]
671 ; CHECK-NEXT: strbmi r2, [r0, #5]
672 ; CHECK-NEXT: lsls r2, r1, #25
673 ; CHECK-NEXT: itt mi
674 ; CHECK-NEXT: vmovmi.u8 r2, q0[6]
675 ; CHECK-NEXT: strbmi r2, [r0, #6]
676 ; CHECK-NEXT: lsls r2, r1, #24
677 ; CHECK-NEXT: itt mi
678 ; CHECK-NEXT: vmovmi.u8 r2, q0[7]
679 ; CHECK-NEXT: strbmi r2, [r0, #7]
680 ; CHECK-NEXT: lsls r2, r1, #23
681 ; CHECK-NEXT: itt mi
682 ; CHECK-NEXT: vmovmi.u8 r2, q0[8]
683 ; CHECK-NEXT: strbmi r2, [r0, #8]
684 ; CHECK-NEXT: lsls r2, r1, #22
685 ; CHECK-NEXT: itt mi
686 ; CHECK-NEXT: vmovmi.u8 r2, q0[9]
687 ; CHECK-NEXT: strbmi r2, [r0, #9]
688 ; CHECK-NEXT: lsls r2, r1, #21
689 ; CHECK-NEXT: itt mi
690 ; CHECK-NEXT: vmovmi.u8 r2, q0[10]
691 ; CHECK-NEXT: strbmi r2, [r0, #10]
692 ; CHECK-NEXT: lsls r2, r1, #20
693 ; CHECK-NEXT: itt mi
694 ; CHECK-NEXT: vmovmi.u8 r2, q0[11]
695 ; CHECK-NEXT: strbmi r2, [r0, #11]
696 ; CHECK-NEXT: lsls r2, r1, #19
697 ; CHECK-NEXT: itt mi
698 ; CHECK-NEXT: vmovmi.u8 r2, q0[12]
699 ; CHECK-NEXT: strbmi r2, [r0, #12]
700 ; CHECK-NEXT: lsls r2, r1, #18
701 ; CHECK-NEXT: itt mi
702 ; CHECK-NEXT: vmovmi.u8 r2, q0[13]
703 ; CHECK-NEXT: strbmi r2, [r0, #13]
704 ; CHECK-NEXT: lsls r2, r1, #17
705 ; CHECK-NEXT: itt mi
706 ; CHECK-NEXT: vmovmi.u8 r2, q0[14]
707 ; CHECK-NEXT: strbmi r2, [r0, #14]
708 ; CHECK-NEXT: lsls r1, r1, #16
709 ; CHECK-NEXT: itt mi
710 ; CHECK-NEXT: vmovmi.u8 r1, q0[15]
711 ; CHECK-NEXT: strbmi r1, [r0, #15]
712 ; CHECK-NEXT: mov sp, r4
713 ; CHECK-NEXT: pop {r4, r6, r7, pc}
327714 entry:
328715 %0 = load <16 x i8>, <16 x i8>* %mask, align 1
329716 %1 = icmp sgt <16 x i8> %0, zeroinitializer
335722 define void @foo_trunc_v8i8_v8i16(<8 x i8> *%dest, <8 x i16> *%mask, <8 x i16> *%src) {
336723 ; CHECK-LABEL: foo_trunc_v8i8_v8i16:
337724 ; CHECK: @ %bb.0: @ %entry
338 ; CHECK-NEXT: .pad #8
339 ; CHECK-NEXT: sub sp, #8
725 ; CHECK-NEXT: .pad #16
726 ; CHECK-NEXT: sub sp, #16
340727 ; CHECK-NEXT: vldrh.u16 q0, [r1]
341 ; CHECK-NEXT: mov r3, sp
728 ; CHECK-NEXT: add r3, sp, #8
342729 ; CHECK-NEXT: vcmp.s16 gt, q0, zr
343 ; CHECK-NEXT: vstr p0, [r3]
344 ; CHECK-NEXT: vpst
345 ; CHECK-NEXT: vldrht.u16 q0, [r2]
730 ; CHECK-NEXT: @ implicit-def: $q0
731 ; CHECK-NEXT: vstr p0, [r3]
732 ; CHECK-NEXT: ldrb.w r1, [sp, #8]
733 ; CHECK-NEXT: lsls r3, r1, #31
734 ; CHECK-NEXT: itt ne
735 ; CHECK-NEXT: ldrhne r3, [r2]
736 ; CHECK-NEXT: vmovne.16 q0[0], r3
737 ; CHECK-NEXT: lsls r3, r1, #30
738 ; CHECK-NEXT: itt mi
739 ; CHECK-NEXT: ldrhmi r3, [r2, #2]
740 ; CHECK-NEXT: vmovmi.16 q0[1], r3
741 ; CHECK-NEXT: lsls r3, r1, #29
742 ; CHECK-NEXT: itt mi
743 ; CHECK-NEXT: ldrhmi r3, [r2, #4]
744 ; CHECK-NEXT: vmovmi.16 q0[2], r3
745 ; CHECK-NEXT: lsls r3, r1, #28
746 ; CHECK-NEXT: itt mi
747 ; CHECK-NEXT: ldrhmi r3, [r2, #6]
748 ; CHECK-NEXT: vmovmi.16 q0[3], r3
749 ; CHECK-NEXT: lsls r3, r1, #27
750 ; CHECK-NEXT: itt mi
751 ; CHECK-NEXT: ldrhmi r3, [r2, #8]
752 ; CHECK-NEXT: vmovmi.16 q0[4], r3
753 ; CHECK-NEXT: lsls r3, r1, #26
754 ; CHECK-NEXT: itt mi
755 ; CHECK-NEXT: ldrhmi r3, [r2, #10]
756 ; CHECK-NEXT: vmovmi.16 q0[5], r3
757 ; CHECK-NEXT: lsls r3, r1, #25
758 ; CHECK-NEXT: itt mi
759 ; CHECK-NEXT: ldrhmi r3, [r2, #12]
760 ; CHECK-NEXT: vmovmi.16 q0[6], r3
761 ; CHECK-NEXT: lsls r1, r1, #24
762 ; CHECK-NEXT: itt mi
763 ; CHECK-NEXT: ldrhmi r1, [r2, #14]
764 ; CHECK-NEXT: vmovmi.16 q0[7], r1
765 ; CHECK-NEXT: mov r1, sp
766 ; CHECK-NEXT: vstr p0, [r1]
346767 ; CHECK-NEXT: ldrb.w r1, [sp]
347768 ; CHECK-NEXT: lsls r2, r1, #31
348769 ; CHECK-NEXT: itt ne
376797 ; CHECK-NEXT: itt mi
377798 ; CHECK-NEXT: vmovmi.u16 r1, q0[7]
378799 ; CHECK-NEXT: strbmi r1, [r0, #7]
379 ; CHECK-NEXT: add sp, #8
800 ; CHECK-NEXT: add sp, #16
380801 ; CHECK-NEXT: bx lr
381802 entry:
382803 %0 = load <8 x i16>, <8 x i16>* %mask, align 2
390811 define void @foo_trunc_v4i8_v4i32(<4 x i8> *%dest, <4 x i32> *%mask, <4 x i32> *%src) {
391812 ; CHECK-LABEL: foo_trunc_v4i8_v4i32:
392813 ; CHECK: @ %bb.0: @ %entry
393 ; CHECK-NEXT: .pad #4
394 ; CHECK-NEXT: sub sp, #4
814 ; CHECK-NEXT: .pad #8
815 ; CHECK-NEXT: sub sp, #8
395816 ; CHECK-NEXT: vldrw.u32 q0, [r1]
396 ; CHECK-NEXT: mov r3, sp
817 ; CHECK-NEXT: add r3, sp, #4
397818 ; CHECK-NEXT: vcmp.s32 gt, q0, zr
398 ; CHECK-NEXT: vstr p0, [r3]
399 ; CHECK-NEXT: vpst
400 ; CHECK-NEXT: vldrwt.u32 q0, [r2]
819 ; CHECK-NEXT: @ implicit-def: $q0
820 ; CHECK-NEXT: vstr p0, [r3]
821 ; CHECK-NEXT: ldrb.w r1, [sp, #4]
822 ; CHECK-NEXT: lsls r3, r1, #31
823 ; CHECK-NEXT: itt ne
824 ; CHECK-NEXT: ldrne r3, [r2]
825 ; CHECK-NEXT: vmovne.32 q0[0], r3
826 ; CHECK-NEXT: lsls r3, r1, #30
827 ; CHECK-NEXT: itt mi
828 ; CHECK-NEXT: ldrmi r3, [r2, #4]
829 ; CHECK-NEXT: vmovmi.32 q0[1], r3
830 ; CHECK-NEXT: lsls r3, r1, #29
831 ; CHECK-NEXT: itt mi
832 ; CHECK-NEXT: ldrmi r3, [r2, #8]
833 ; CHECK-NEXT: vmovmi.32 q0[2], r3
834 ; CHECK-NEXT: lsls r1, r1, #28
835 ; CHECK-NEXT: itt mi
836 ; CHECK-NEXT: ldrmi r1, [r2, #12]
837 ; CHECK-NEXT: vmovmi.32 q0[3], r1
838 ; CHECK-NEXT: mov r1, sp
839 ; CHECK-NEXT: vstr p0, [r1]
401840 ; CHECK-NEXT: ldrb.w r1, [sp]
402841 ; CHECK-NEXT: lsls r2, r1, #31
403842 ; CHECK-NEXT: itt ne
415854 ; CHECK-NEXT: itt mi
416855 ; CHECK-NEXT: vmovmi r1, s3
417856 ; CHECK-NEXT: strbmi r1, [r0, #3]
418 ; CHECK-NEXT: add sp, #4
857 ; CHECK-NEXT: add sp, #8
419858 ; CHECK-NEXT: bx lr
420859 entry:
421860 %0 = load <4 x i32>, <4 x i32>* %mask, align 4
429868 define void @foo_trunc_v4i16_v4i32(<4 x i16> *%dest, <4 x i32> *%mask, <4 x i32> *%src) {
430869 ; CHECK-LABEL: foo_trunc_v4i16_v4i32:
431870 ; CHECK: @ %bb.0: @ %entry
432 ; CHECK-NEXT: .pad #4
433 ; CHECK-NEXT: sub sp, #4
871 ; CHECK-NEXT: .pad #8
872 ; CHECK-NEXT: sub sp, #8
434873 ; CHECK-NEXT: vldrw.u32 q0, [r1]
435 ; CHECK-NEXT: mov r3, sp
874 ; CHECK-NEXT: add r3, sp, #4
436875 ; CHECK-NEXT: vcmp.s32 gt, q0, zr
437 ; CHECK-NEXT: vstr p0, [r3]
438 ; CHECK-NEXT: vpst
439 ; CHECK-NEXT: vldrwt.u32 q0, [r2]
876 ; CHECK-NEXT: @ implicit-def: $q0
877 ; CHECK-NEXT: vstr p0, [r3]
878 ; CHECK-NEXT: ldrb.w r1, [sp, #4]
879 ; CHECK-NEXT: lsls r3, r1, #31
880 ; CHECK-NEXT: itt ne
881 ; CHECK-NEXT: ldrne r3, [r2]
882 ; CHECK-NEXT: vmovne.32 q0[0], r3
883 ; CHECK-NEXT: lsls r3, r1, #30
884 ; CHECK-NEXT: itt mi
885 ; CHECK-NEXT: ldrmi r3, [r2, #4]
886 ; CHECK-NEXT: vmovmi.32 q0[1], r3
887 ; CHECK-NEXT: lsls r3, r1, #29
888 ; CHECK-NEXT: itt mi
889 ; CHECK-NEXT: ldrmi r3, [r2, #8]
890 ; CHECK-NEXT: vmovmi.32 q0[2], r3
891 ; CHECK-NEXT: lsls r1, r1, #28
892 ; CHECK-NEXT: itt mi
893 ; CHECK-NEXT: ldrmi r1, [r2, #12]
894 ; CHECK-NEXT: vmovmi.32 q0[3], r1
895 ; CHECK-NEXT: mov r1, sp
896 ; CHECK-NEXT: vstr p0, [r1]
440897 ; CHECK-NEXT: ldrb.w r1, [sp]
441898 ; CHECK-NEXT: lsls r2, r1, #31
442899 ; CHECK-NEXT: itt ne
454911 ; CHECK-NEXT: itt mi
455912 ; CHECK-NEXT: vmovmi r1, s3
456913 ; CHECK-NEXT: strhmi r1, [r0, #6]
457 ; CHECK-NEXT: add sp, #4
914 ; CHECK-NEXT: add sp, #8
458915 ; CHECK-NEXT: bx lr
459916 entry:
460917 %0 = load <4 x i32>, <4 x i32>* %mask, align 4
468925 define void @foo_v4f32_v4f32(<4 x float> *%dest, <4 x i32> *%mask, <4 x float> *%src) {
469926 ; CHECK-LABEL: foo_v4f32_v4f32:
470927 ; CHECK: @ %bb.0: @ %entry
928 ; CHECK-NEXT: .pad #8
929 ; CHECK-NEXT: sub sp, #8
471930 ; CHECK-NEXT: vldrw.u32 q0, [r1]
931 ; CHECK-NEXT: add r3, sp, #4
472932 ; CHECK-NEXT: vcmp.s32 gt, q0, zr
473 ; CHECK-NEXT: vpstt
474 ; CHECK-NEXT: vldrwt.u32 q0, [r2]
475 ; CHECK-NEXT: vstrwt.32 q0, [r0]
933 ; CHECK-NEXT: @ implicit-def: $q0
934 ; CHECK-NEXT: vstr p0, [r3]
935 ; CHECK-NEXT: ldrb.w r1, [sp, #4]
936 ; CHECK-NEXT: lsls r3, r1, #31
937 ; CHECK-NEXT: it ne
938 ; CHECK-NEXT: vldrne s0, [r2]
939 ; CHECK-NEXT: lsls r3, r1, #30
940 ; CHECK-NEXT: it mi
941 ; CHECK-NEXT: vldrmi s1, [r2, #4]
942 ; CHECK-NEXT: lsls r3, r1, #29
943 ; CHECK-NEXT: it mi
944 ; CHECK-NEXT: vldrmi s2, [r2, #8]
945 ; CHECK-NEXT: lsls r1, r1, #28
946 ; CHECK-NEXT: it mi
947 ; CHECK-NEXT: vldrmi s3, [r2, #12]
948 ; CHECK-NEXT: mov r1, sp
949 ; CHECK-NEXT: vstr p0, [r1]
950 ; CHECK-NEXT: ldrb.w r1, [sp]
951 ; CHECK-NEXT: lsls r2, r1, #31
952 ; CHECK-NEXT: it ne
953 ; CHECK-NEXT: vstrne s0, [r0]
954 ; CHECK-NEXT: lsls r2, r1, #30
955 ; CHECK-NEXT: it mi
956 ; CHECK-NEXT: vstrmi s1, [r0, #4]
957 ; CHECK-NEXT: lsls r2, r1, #29
958 ; CHECK-NEXT: it mi
959 ; CHECK-NEXT: vstrmi s2, [r0, #8]
960 ; CHECK-NEXT: lsls r1, r1, #28
961 ; CHECK-NEXT: it mi
962 ; CHECK-NEXT: vstrmi s3, [r0, #12]
963 ; CHECK-NEXT: add sp, #8
476964 ; CHECK-NEXT: bx lr
477965 entry:
478966 %0 = load <4 x i32>, <4 x i32>* %mask, align 4
485973 define void @foo_v8f16_v8f16(<8 x half> *%dest, <8 x i16> *%mask, <8 x half> *%src) {
486974 ; CHECK-LABEL: foo_v8f16_v8f16:
487975 ; CHECK: @ %bb.0: @ %entry
976 ; CHECK-NEXT: .pad #16
977 ; CHECK-NEXT: sub sp, #16
488978 ; CHECK-NEXT: vldrh.u16 q0, [r1]
979 ; CHECK-NEXT: add r3, sp, #8
489980 ; CHECK-NEXT: vcmp.s16 gt, q0, zr
490 ; CHECK-NEXT: vpstt
491 ; CHECK-NEXT: vldrht.u16 q0, [r2]
492 ; CHECK-NEXT: vstrht.16 q0, [r0]
981 ; CHECK-NEXT: @ implicit-def: $q0
982 ; CHECK-NEXT: vstr p0, [r3]
983 ; CHECK-NEXT: ldrb.w r1, [sp, #8]
984 ; CHECK-NEXT: lsls r3, r1, #31
985 ; CHECK-NEXT: bne .LBB13_18
986 ; CHECK-NEXT: @ %bb.1: @ %else
987 ; CHECK-NEXT: lsls r3, r1, #30
988 ; CHECK-NEXT: bmi .LBB13_19
989 ; CHECK-NEXT: .LBB13_2: @ %else2
990 ; CHECK-NEXT: lsls r3, r1, #29
991 ; CHECK-NEXT: bmi .LBB13_20
992 ; CHECK-NEXT: .LBB13_3: @ %else5
993 ; CHECK-NEXT: lsls r3, r1, #28
994 ; CHECK-NEXT: bmi .LBB13_21
995 ; CHECK-NEXT: .LBB13_4: @ %else8
996 ; CHECK-NEXT: lsls r3, r1, #27
997 ; CHECK-NEXT: bmi .LBB13_22
998 ; CHECK-NEXT: .LBB13_5: @ %else11
999 ; CHECK-NEXT: lsls r3, r1, #26
1000 ; CHECK-NEXT: bmi .LBB13_23
1001 ; CHECK-NEXT: .LBB13_6: @ %else14
1002 ; CHECK-NEXT: lsls r3, r1, #25
1003 ; CHECK-NEXT: bmi .LBB13_24
1004 ; CHECK-NEXT: .LBB13_7: @ %else17
1005 ; CHECK-NEXT: lsls r1, r1, #24
1006 ; CHECK-NEXT: bpl .LBB13_9
1007 ; CHECK-NEXT: .LBB13_8: @ %cond.load19
1008 ; CHECK-NEXT: vldr.16 s4, [r2, #14]
1009 ; CHECK-NEXT: vmov r1, s4
1010 ; CHECK-NEXT: vmov.16 q0[7], r1
1011 ; CHECK-NEXT: .LBB13_9: @ %else20
1012 ; CHECK-NEXT: mov r1, sp
1013 ; CHECK-NEXT: vstr p0, [r1]
1014 ; CHECK-NEXT: ldrb.w r1, [sp]
1015 ; CHECK-NEXT: lsls r2, r1, #31
1016 ; CHECK-NEXT: bne .LBB13_25
1017 ; CHECK-NEXT: @ %bb.10: @ %else23
1018 ; CHECK-NEXT: lsls r2, r1, #30
1019 ; CHECK-NEXT: bmi .LBB13_26
1020 ; CHECK-NEXT: .LBB13_11: @ %else25
1021 ; CHECK-NEXT: lsls r2, r1, #29
1022 ; CHECK-NEXT: bmi .LBB13_27
1023 ; CHECK-NEXT: .LBB13_12: @ %else27
1024 ; CHECK-NEXT: lsls r2, r1, #28
1025 ; CHECK-NEXT: bmi .LBB13_28
1026 ; CHECK-NEXT: .LBB13_13: @ %else29
1027 ; CHECK-NEXT: lsls r2, r1, #27
1028 ; CHECK-NEXT: bmi .LBB13_29
1029 ; CHECK-NEXT: .LBB13_14: @ %else31
1030 ; CHECK-NEXT: lsls r2, r1, #26
1031 ; CHECK-NEXT: bmi .LBB13_30
1032 ; CHECK-NEXT: .LBB13_15: @ %else33
1033 ; CHECK-NEXT: lsls r2, r1, #25
1034 ; CHECK-NEXT: bmi .LBB13_31
1035 ; CHECK-NEXT: .LBB13_16: @ %else35
1036 ; CHECK-NEXT: lsls r1, r1, #24
1037 ; CHECK-NEXT: bmi .LBB13_32
1038 ; CHECK-NEXT: .LBB13_17: @ %else37
1039 ; CHECK-NEXT: add sp, #16
1040 ; CHECK-NEXT: bx lr
1041 ; CHECK-NEXT: .LBB13_18: @ %cond.load
1042 ; CHECK-NEXT: vldr.16 s0, [r2]
1043 ; CHECK-NEXT: lsls r3, r1, #30
1044 ; CHECK-NEXT: bpl .LBB13_2
1045 ; CHECK-NEXT: .LBB13_19: @ %cond.load1
1046 ; CHECK-NEXT: vldr.16 s4, [r2, #2]
1047 ; CHECK-NEXT: vmov r3, s4
1048 ; CHECK-NEXT: vmov.16 q0[1], r3
1049 ; CHECK-NEXT: lsls r3, r1, #29
1050 ; CHECK-NEXT: bpl .LBB13_3
1051 ; CHECK-NEXT: .LBB13_20: @ %cond.load4
1052 ; CHECK-NEXT: vldr.16 s4, [r2, #4]
1053 ; CHECK-NEXT: vmov r3, s4
1054 ; CHECK-NEXT: vmov.16 q0[2], r3
1055 ; CHECK-NEXT: lsls r3, r1, #28
1056 ; CHECK-NEXT: bpl .LBB13_4
1057 ; CHECK-NEXT: .LBB13_21: @ %cond.load7
1058 ; CHECK-NEXT: vldr.16 s4, [r2, #6]
1059 ; CHECK-NEXT: vmov r3, s4
1060 ; CHECK-NEXT: vmov.16 q0[3], r3
1061 ; CHECK-NEXT: lsls r3, r1, #27
1062 ; CHECK-NEXT: bpl .LBB13_5
1063 ; CHECK-NEXT: .LBB13_22: @ %cond.load10
1064 ; CHECK-NEXT: vldr.16 s4, [r2, #8]
1065 ; CHECK-NEXT: vmov r3, s4
1066 ; CHECK-NEXT: vmov.16 q0[4], r3
1067 ; CHECK-NEXT: lsls r3, r1, #26
1068 ; CHECK-NEXT: bpl .LBB13_6
1069 ; CHECK-NEXT: .LBB13_23: @ %cond.load13
1070 ; CHECK-NEXT: vldr.16 s4, [r2, #10]
1071 ; CHECK-NEXT: vmov r3, s4
1072 ; CHECK-NEXT: vmov.16 q0[5], r3
1073 ; CHECK-NEXT: lsls r3, r1, #25
1074 ; CHECK-NEXT: bpl .LBB13_7
1075 ; CHECK-NEXT: .LBB13_24: @ %cond.load16
1076 ; CHECK-NEXT: vldr.16 s4, [r2, #12]
1077 ; CHECK-NEXT: vmov r3, s4
1078 ; CHECK-NEXT: vmov.16 q0[6], r3
1079 ; CHECK-NEXT: lsls r1, r1, #24
1080 ; CHECK-NEXT: bmi .LBB13_8
1081 ; CHECK-NEXT: b .LBB13_9
1082 ; CHECK-NEXT: .LBB13_25: @ %cond.store
1083 ; CHECK-NEXT: vstr.16 s0, [r0]
1084 ; CHECK-NEXT: lsls r2, r1, #30
1085 ; CHECK-NEXT: bpl .LBB13_11
1086 ; CHECK-NEXT: .LBB13_26: @ %cond.store24
1087 ; CHECK-NEXT: vmovx.f16 s4, s0
1088 ; CHECK-NEXT: vstr.16 s4, [r0, #2]
1089 ; CHECK-NEXT: lsls r2, r1, #29
1090 ; CHECK-NEXT: bpl .LBB13_12
1091 ; CHECK-NEXT: .LBB13_27: @ %cond.store26
1092 ; CHECK-NEXT: vstr.16 s1, [r0, #4]
1093 ; CHECK-NEXT: lsls r2, r1, #28
1094 ; CHECK-NEXT: bpl .LBB13_13
1095 ; CHECK-NEXT: .LBB13_28: @ %cond.store28
1096 ; CHECK-NEXT: vmovx.f16 s4, s1
1097 ; CHECK-NEXT: vstr.16 s4, [r0, #6]
1098 ; CHECK-NEXT: lsls r2, r1, #27
1099 ; CHECK-NEXT: bpl .LBB13_14
1100 ; CHECK-NEXT: .LBB13_29: @ %cond.store30
1101 ; CHECK-NEXT: vstr.16 s2, [r0, #8]
1102 ; CHECK-NEXT: lsls r2, r1, #26
1103 ; CHECK-NEXT: bpl .LBB13_15
1104 ; CHECK-NEXT: .LBB13_30: @ %cond.store32
1105 ; CHECK-NEXT: vmovx.f16 s4, s2
1106 ; CHECK-NEXT: vstr.16 s4, [r0, #10]
1107 ; CHECK-NEXT: lsls r2, r1, #25
1108 ; CHECK-NEXT: bpl .LBB13_16
1109 ; CHECK-NEXT: .LBB13_31: @ %cond.store34
1110 ; CHECK-NEXT: vstr.16 s3, [r0, #12]
1111 ; CHECK-NEXT: lsls r1, r1, #24
1112 ; CHECK-NEXT: bpl .LBB13_17
1113 ; CHECK-NEXT: .LBB13_32: @ %cond.store36
1114 ; CHECK-NEXT: vmovx.f16 s0, s3
1115 ; CHECK-NEXT: vstr.16 s0, [r0, #14]
1116 ; CHECK-NEXT: add sp, #16
4931117 ; CHECK-NEXT: bx lr
4941118 entry:
4951119 %0 = load <8 x i16>, <8 x i16>* %mask, align 2
44 define arm_aapcs_vfpcc <4 x i32> @masked_v4i32_align4_zero(<4 x i32> *%dest, <4 x i32> %a) {
55 ; CHECK-LE-LABEL: masked_v4i32_align4_zero:
66 ; CHECK-LE: @ %bb.0: @ %entry
7 ; CHECK-LE-NEXT: .pad #4
8 ; CHECK-LE-NEXT: sub sp, #4
9 ; CHECK-LE-NEXT: mov r1, sp
710 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
8 ; CHECK-LE-NEXT: vpst
9 ; CHECK-LE-NEXT: vldrwt.u32 q0, [r0]
11 ; CHECK-LE-NEXT: vstr p0, [r1]
12 ; CHECK-LE-NEXT: ldrb.w r1, [sp]
13 ; CHECK-LE-NEXT: lsls r2, r1, #31
14 ; CHECK-LE-NEXT: beq .LBB0_2
15 ; CHECK-LE-NEXT: @ %bb.1: @ %cond.load
16 ; CHECK-LE-NEXT: movs r2, #0
17 ; CHECK-LE-NEXT: ldr r3, [r0]
18 ; CHECK-LE-NEXT: vdup.32 q0, r2
19 ; CHECK-LE-NEXT: vmov.32 q0[0], r3
20 ; CHECK-LE-NEXT: b .LBB0_3
21 ; CHECK-LE-NEXT: .LBB0_2:
22 ; CHECK-LE-NEXT: vmov.i32 q0, #0x0
23 ; CHECK-LE-NEXT: .LBB0_3: @ %else
24 ; CHECK-LE-NEXT: lsls r2, r1, #30
25 ; CHECK-LE-NEXT: itt mi
26 ; CHECK-LE-NEXT: ldrmi r2, [r0, #4]
27 ; CHECK-LE-NEXT: vmovmi.32 q0[1], r2
28 ; CHECK-LE-NEXT: lsls r2, r1, #29
29 ; CHECK-LE-NEXT: itt mi
30 ; CHECK-LE-NEXT: ldrmi r2, [r0, #8]
31 ; CHECK-LE-NEXT: vmovmi.32 q0[2], r2
32 ; CHECK-LE-NEXT: lsls r1, r1, #28
33 ; CHECK-LE-NEXT: itt mi
34 ; CHECK-LE-NEXT: ldrmi r0, [r0, #12]
35 ; CHECK-LE-NEXT: vmovmi.32 q0[3], r0
36 ; CHECK-LE-NEXT: add sp, #4
1037 ; CHECK-LE-NEXT: bx lr
1138 ;
1239 ; CHECK-BE-LABEL: masked_v4i32_align4_zero:
1340 ; CHECK-BE: @ %bb.0: @ %entry
41 ; CHECK-BE-NEXT: .pad #4
42 ; CHECK-BE-NEXT: sub sp, #4
1443 ; CHECK-BE-NEXT: vrev64.32 q1, q0
44 ; CHECK-BE-NEXT: mov r1, sp
1545 ; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr
16 ; CHECK-BE-NEXT: vpst
17 ; CHECK-BE-NEXT: vldrwt.u32 q1, [r0]
46 ; CHECK-BE-NEXT: vstr p0, [r1]
47 ; CHECK-BE-NEXT: ldrb.w r1, [sp]
48 ; CHECK-BE-NEXT: lsls r2, r1, #31
49 ; CHECK-BE-NEXT: beq .LBB0_2
50 ; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
51 ; CHECK-BE-NEXT: movs r2, #0
52 ; CHECK-BE-NEXT: ldr r3, [r0]
53 ; CHECK-BE-NEXT: vdup.32 q1, r2
54 ; CHECK-BE-NEXT: vmov.32 q1[0], r3
55 ; CHECK-BE-NEXT: b .LBB0_3
56 ; CHECK-BE-NEXT: .LBB0_2:
57 ; CHECK-BE-NEXT: vmov.i32 q1, #0x0
58 ; CHECK-BE-NEXT: .LBB0_3: @ %else
59 ; CHECK-BE-NEXT: lsls r2, r1, #30
60 ; CHECK-BE-NEXT: itt mi
61 ; CHECK-BE-NEXT: ldrmi r2, [r0, #4]
62 ; CHECK-BE-NEXT: vmovmi.32 q1[1], r2
63 ; CHECK-BE-NEXT: lsls r2, r1, #29
64 ; CHECK-BE-NEXT: itt mi
65 ; CHECK-BE-NEXT: ldrmi r2, [r0, #8]
66 ; CHECK-BE-NEXT: vmovmi.32 q1[2], r2
67 ; CHECK-BE-NEXT: lsls r1, r1, #28
68 ; CHECK-BE-NEXT: itt mi
69 ; CHECK-BE-NEXT: ldrmi r0, [r0, #12]
70 ; CHECK-BE-NEXT: vmovmi.32 q1[3], r0
1871 ; CHECK-BE-NEXT: vrev64.32 q0, q1
72 ; CHECK-BE-NEXT: add sp, #4
1973 ; CHECK-BE-NEXT: bx lr
2074 entry:
2175 %c = icmp sgt <4 x i32> %a, zeroinitializer
2680 define arm_aapcs_vfpcc <4 x i32> @masked_v4i32_align4_undef(<4 x i32> *%dest, <4 x i32> %a) {
2781 ; CHECK-LE-LABEL: masked_v4i32_align4_undef:
2882 ; CHECK-LE: @ %bb.0: @ %entry
83 ; CHECK-LE-NEXT: .pad #4
84 ; CHECK-LE-NEXT: sub sp, #4
2985 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
30 ; CHECK-LE-NEXT: vpst
31 ; CHECK-LE-NEXT: vldrwt.u32 q0, [r0]
86 ; CHECK-LE-NEXT: mov r1, sp
87 ; CHECK-LE-NEXT: vstr p0, [r1]
88 ; CHECK-LE-NEXT: @ implicit-def: $q0
89 ; CHECK-LE-NEXT: ldrb.w r1, [sp]
90 ; CHECK-LE-NEXT: lsls r2, r1, #31
91 ; CHECK-LE-NEXT: itt ne
92 ; CHECK-LE-NEXT: ldrne r2, [r0]
93 ; CHECK-LE-NEXT: vmovne.32 q0[0], r2
94 ; CHECK-LE-NEXT: lsls r2, r1, #30
95 ; CHECK-LE-NEXT: itt mi
96 ; CHECK-LE-NEXT: ldrmi r2, [r0, #4]
97 ; CHECK-LE-NEXT: vmovmi.32 q0[1], r2
98 ; CHECK-LE-NEXT: lsls r2, r1, #29
99 ; CHECK-LE-NEXT: itt mi
100 ; CHECK-LE-NEXT: ldrmi r2, [r0, #8]
101 ; CHECK-LE-NEXT: vmovmi.32 q0[2], r2
102 ; CHECK-LE-NEXT: lsls r1, r1, #28
103 ; CHECK-LE-NEXT: itt mi
104 ; CHECK-LE-NEXT: ldrmi r0, [r0, #12]
105 ; CHECK-LE-NEXT: vmovmi.32 q0[3], r0
106 ; CHECK-LE-NEXT: add sp, #4
32107 ; CHECK-LE-NEXT: bx lr
33108 ;
34109 ; CHECK-BE-LABEL: masked_v4i32_align4_undef:
35110 ; CHECK-BE: @ %bb.0: @ %entry
111 ; CHECK-BE-NEXT: .pad #4
112 ; CHECK-BE-NEXT: sub sp, #4
36113 ; CHECK-BE-NEXT: vrev64.32 q1, q0
114 ; CHECK-BE-NEXT: mov r1, sp
37115 ; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr
38 ; CHECK-BE-NEXT: vpst
39 ; CHECK-BE-NEXT: vldrwt.u32 q1, [r0]
116 ; CHECK-BE-NEXT: @ implicit-def: $q1
117 ; CHECK-BE-NEXT: vstr p0, [r1]
118 ; CHECK-BE-NEXT: ldrb.w r1, [sp]
119 ; CHECK-BE-NEXT: lsls r2, r1, #31
120 ; CHECK-BE-NEXT: itt ne
121 ; CHECK-BE-NEXT: ldrne r2, [r0]
122 ; CHECK-BE-NEXT: vmovne.32 q1[0], r2
123 ; CHECK-BE-NEXT: lsls r2, r1, #30
124 ; CHECK-BE-NEXT: itt mi
125 ; CHECK-BE-NEXT: ldrmi r2, [r0, #4]
126 ; CHECK-BE-NEXT: vmovmi.32 q1[1], r2
127 ; CHECK-BE-NEXT: lsls r2, r1, #29
128 ; CHECK-BE-NEXT: itt mi
129 ; CHECK-BE-NEXT: ldrmi r2, [r0, #8]
130 ; CHECK-BE-NEXT: vmovmi.32 q1[2], r2
131 ; CHECK-BE-NEXT: lsls r1, r1, #28
132 ; CHECK-BE-NEXT: itt mi
133 ; CHECK-BE-NEXT: ldrmi r0, [r0, #12]
134 ; CHECK-BE-NEXT: vmovmi.32 q1[3], r0
40135 ; CHECK-BE-NEXT: vrev64.32 q0, q1
136 ; CHECK-BE-NEXT: add sp, #4
41137 ; CHECK-BE-NEXT: bx lr
42138 entry:
43139 %c = icmp sgt <4 x i32> %a, zeroinitializer
48144 define arm_aapcs_vfpcc <4 x i32> @masked_v4i32_align1_undef(<4 x i32> *%dest, <4 x i32> %a) {
49145 ; CHECK-LE-LABEL: masked_v4i32_align1_undef:
50146 ; CHECK-LE: @ %bb.0: @ %entry
147 ; CHECK-LE-NEXT: .pad #4
148 ; CHECK-LE-NEXT: sub sp, #4
51149 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
52 ; CHECK-LE-NEXT: vpst
53 ; CHECK-LE-NEXT: vldrbt.u8 q0, [r0]
150 ; CHECK-LE-NEXT: mov r1, sp
151 ; CHECK-LE-NEXT: vstr p0, [r1]
152 ; CHECK-LE-NEXT: @ implicit-def: $q0
153 ; CHECK-LE-NEXT: ldrb.w r1, [sp]
154 ; CHECK-LE-NEXT: lsls r2, r1, #31
155 ; CHECK-LE-NEXT: itt ne
156 ; CHECK-LE-NEXT: ldrne r2, [r0]
157 ; CHECK-LE-NEXT: vmovne.32 q0[0], r2
158 ; CHECK-LE-NEXT: lsls r2, r1, #30
159 ; CHECK-LE-NEXT: itt mi
160 ; CHECK-LE-NEXT: ldrmi r2, [r0, #4]
161 ; CHECK-LE-NEXT: vmovmi.32 q0[1], r2
162 ; CHECK-LE-NEXT: lsls r2, r1, #29
163 ; CHECK-LE-NEXT: itt mi
164 ; CHECK-LE-NEXT: ldrmi r2, [r0, #8]
165 ; CHECK-LE-NEXT: vmovmi.32 q0[2], r2
166 ; CHECK-LE-NEXT: lsls r1, r1, #28
167 ; CHECK-LE-NEXT: itt mi
168 ; CHECK-LE-NEXT: ldrmi r0, [r0, #12]
169 ; CHECK-LE-NEXT: vmovmi.32 q0[3], r0
170 ; CHECK-LE-NEXT: add sp, #4
54171 ; CHECK-LE-NEXT: bx lr
55172 ;
56173 ; CHECK-BE-LABEL: masked_v4i32_align1_undef:
57174 ; CHECK-BE: @ %bb.0: @ %entry
175 ; CHECK-BE-NEXT: .pad #4
176 ; CHECK-BE-NEXT: sub sp, #4
58177 ; CHECK-BE-NEXT: vrev64.32 q1, q0
178 ; CHECK-BE-NEXT: mov r1, sp
59179 ; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr
60 ; CHECK-BE-NEXT: vpst
61 ; CHECK-BE-NEXT: vldrbt.u8 q0, [r0]
62 ; CHECK-BE-NEXT: vrev32.8 q1, q0
180 ; CHECK-BE-NEXT: @ implicit-def: $q1
181 ; CHECK-BE-NEXT: vstr p0, [r1]
182 ; CHECK-BE-NEXT: ldrb.w r1, [sp]
183 ; CHECK-BE-NEXT: lsls r2, r1, #31
184 ; CHECK-BE-NEXT: itt ne
185 ; CHECK-BE-NEXT: ldrne r2, [r0]
186 ; CHECK-BE-NEXT: vmovne.32 q1[0], r2
187 ; CHECK-BE-NEXT: lsls r2, r1, #30
188 ; CHECK-BE-NEXT: itt mi
189 ; CHECK-BE-NEXT: ldrmi r2, [r0, #4]
190 ; CHECK-BE-NEXT: vmovmi.32 q1[1], r2
191 ; CHECK-BE-NEXT: lsls r2, r1, #29
192 ; CHECK-BE-NEXT: itt mi
193 ; CHECK-BE-NEXT: ldrmi r2, [r0, #8]
194 ; CHECK-BE-NEXT: vmovmi.32 q1[2], r2
195 ; CHECK-BE-NEXT: lsls r1, r1, #28
196 ; CHECK-BE-NEXT: itt mi
197 ; CHECK-BE-NEXT: ldrmi r0, [r0, #12]
198 ; CHECK-BE-NEXT: vmovmi.32 q1[3], r0
63199 ; CHECK-BE-NEXT: vrev64.32 q0, q1
200 ; CHECK-BE-NEXT: add sp, #4
64201 ; CHECK-BE-NEXT: bx lr
65202 entry:
66203 %c = icmp sgt <4 x i32> %a, zeroinitializer
71208 define arm_aapcs_vfpcc <4 x i32> @masked_v4i32_align4_other(<4 x i32> *%dest, <4 x i32> %a) {
72209 ; CHECK-LE-LABEL: masked_v4i32_align4_other:
73210 ; CHECK-LE: @ %bb.0: @ %entry
211 ; CHECK-LE-NEXT: .pad #4
212 ; CHECK-LE-NEXT: sub sp, #4
213 ; CHECK-LE-NEXT: mov r1, sp
74214 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
75 ; CHECK-LE-NEXT: vpst
76 ; CHECK-LE-NEXT: vldrwt.u32 q1, [r0]
77 ; CHECK-LE-NEXT: vpsel q0, q1, q0
215 ; CHECK-LE-NEXT: vstr p0, [r1]
216 ; CHECK-LE-NEXT: ldrb.w r1, [sp]
217 ; CHECK-LE-NEXT: lsls r2, r1, #31
218 ; CHECK-LE-NEXT: itt ne
219 ; CHECK-LE-NEXT: ldrne r2, [r0]
220 ; CHECK-LE-NEXT: vmovne.32 q0[0], r2
221 ; CHECK-LE-NEXT: lsls r2, r1, #30
222 ; CHECK-LE-NEXT: itt mi
223 ; CHECK-LE-NEXT: ldrmi r2, [r0, #4]
224 ; CHECK-LE-NEXT: vmovmi.32 q0[1], r2
225 ; CHECK-LE-NEXT: lsls r2, r1, #29
226 ; CHECK-LE-NEXT: itt mi
227 ; CHECK-LE-NEXT: ldrmi r2, [r0, #8]
228 ; CHECK-LE-NEXT: vmovmi.32 q0[2], r2
229 ; CHECK-LE-NEXT: lsls r1, r1, #28
230 ; CHECK-LE-NEXT: itt mi
231 ; CHECK-LE-NEXT: ldrmi r0, [r0, #12]
232 ; CHECK-LE-NEXT: vmovmi.32 q0[3], r0
233 ; CHECK-LE-NEXT: add sp, #4
78234 ; CHECK-LE-NEXT: bx lr
79235 ;
80236 ; CHECK-BE-LABEL: masked_v4i32_align4_other:
81237 ; CHECK-BE: @ %bb.0: @ %entry
238 ; CHECK-BE-NEXT: .pad #4
239 ; CHECK-BE-NEXT: sub sp, #4
82240 ; CHECK-BE-NEXT: vrev64.32 q1, q0
241 ; CHECK-BE-NEXT: mov r1, sp
83242 ; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr
84 ; CHECK-BE-NEXT: vpst
85 ; CHECK-BE-NEXT: vldrwt.u32 q0, [r0]
86 ; CHECK-BE-NEXT: vpsel q1, q0, q1
243 ; CHECK-BE-NEXT: vstr p0, [r1]
244 ; CHECK-BE-NEXT: ldrb.w r1, [sp]
245 ; CHECK-BE-NEXT: lsls r2, r1, #31
246 ; CHECK-BE-NEXT: itt ne
247 ; CHECK-BE-NEXT: ldrne r2, [r0]
248 ; CHECK-BE-NEXT: vmovne.32 q1[0], r2
249 ; CHECK-BE-NEXT: lsls r2, r1, #30
250 ; CHECK-BE-NEXT: itt mi
251 ; CHECK-BE-NEXT: ldrmi r2, [r0, #4]
252 ; CHECK-BE-NEXT: vmovmi.32 q1[1], r2
253 ; CHECK-BE-NEXT: lsls r2, r1, #29
254 ; CHECK-BE-NEXT: itt mi
255 ; CHECK-BE-NEXT: ldrmi r2, [r0, #8]
256 ; CHECK-BE-NEXT: vmovmi.32 q1[2], r2
257 ; CHECK-BE-NEXT: lsls r1, r1, #28
258 ; CHECK-BE-NEXT: itt mi
259 ; CHECK-BE-NEXT: ldrmi r0, [r0, #12]
260 ; CHECK-BE-NEXT: vmovmi.32 q1[3], r0
87261 ; CHECK-BE-NEXT: vrev64.32 q0, q1
262 ; CHECK-BE-NEXT: add sp, #4
88263 ; CHECK-BE-NEXT: bx lr
89264 entry:
90265 %c = icmp sgt <4 x i32> %a, zeroinitializer
95270 define arm_aapcs_vfpcc i8* @masked_v4i32_preinc(i8* %x, i8* %y, <4 x i32> %a) {
96271 ; CHECK-LE-LABEL: masked_v4i32_preinc:
97272 ; CHECK-LE: @ %bb.0: @ %entry
273 ; CHECK-LE-NEXT: .pad #4
274 ; CHECK-LE-NEXT: sub sp, #4
98275 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
99 ; CHECK-LE-NEXT: vpst
100 ; CHECK-LE-NEXT: vldrwt.u32 q0, [r0, #4]
276 ; CHECK-LE-NEXT: mov r2, sp
277 ; CHECK-LE-NEXT: vstr p0, [r2]
278 ; CHECK-LE-NEXT: @ implicit-def: $q0
279 ; CHECK-LE-NEXT: adds r0, #4
280 ; CHECK-LE-NEXT: ldrb.w r2, [sp]
281 ; CHECK-LE-NEXT: lsls r3, r2, #31
282 ; CHECK-LE-NEXT: itt ne
283 ; CHECK-LE-NEXT: ldrne r3, [r0]
284 ; CHECK-LE-NEXT: vmovne.32 q0[0], r3
285 ; CHECK-LE-NEXT: lsls r3, r2, #30
286 ; CHECK-LE-NEXT: itt mi
287 ; CHECK-LE-NEXT: ldrmi r3, [r0, #4]
288 ; CHECK-LE-NEXT: vmovmi.32 q0[1], r3
289 ; CHECK-LE-NEXT: lsls r3, r2, #29
290 ; CHECK-LE-NEXT: itt mi
291 ; CHECK-LE-NEXT: ldrmi r3, [r0, #8]
292 ; CHECK-LE-NEXT: vmovmi.32 q0[2], r3
293 ; CHECK-LE-NEXT: lsls r2, r2, #28
294 ; CHECK-LE-NEXT: itt mi
295 ; CHECK-LE-NEXT: ldrmi r2, [r0, #12]
296 ; CHECK-LE-NEXT: vmovmi.32 q0[3], r2
101297 ; CHECK-LE-NEXT: vstrw.32 q0, [r1]
102 ; CHECK-LE-NEXT: adds r0, #4
298 ; CHECK-LE-NEXT: add sp, #4
103299 ; CHECK-LE-NEXT: bx lr
104300 ;
105301 ; CHECK-BE-LABEL: masked_v4i32_preinc:
106302 ; CHECK-BE: @ %bb.0: @ %entry
303 ; CHECK-BE-NEXT: .pad #4
304 ; CHECK-BE-NEXT: sub sp, #4
107305 ; CHECK-BE-NEXT: vrev64.32 q1, q0
306 ; CHECK-BE-NEXT: mov r2, sp
108307 ; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr
109 ; CHECK-BE-NEXT: vpst
110 ; CHECK-BE-NEXT: vldrwt.u32 q0, [r0, #4]
308 ; CHECK-BE-NEXT: @ implicit-def: $q0
309 ; CHECK-BE-NEXT: adds r0, #4
310 ; CHECK-BE-NEXT: vstr p0, [r2]
311 ; CHECK-BE-NEXT: ldrb.w r2, [sp]
312 ; CHECK-BE-NEXT: lsls r3, r2, #31
313 ; CHECK-BE-NEXT: itt ne
314 ; CHECK-BE-NEXT: ldrne r3, [r0]
315 ; CHECK-BE-NEXT: vmovne.32 q0[0], r3
316 ; CHECK-BE-NEXT: lsls r3, r2, #30
317 ; CHECK-BE-NEXT: itt mi
318 ; CHECK-BE-NEXT: ldrmi r3, [r0, #4]
319 ; CHECK-BE-NEXT: vmovmi.32 q0[1], r3
320 ; CHECK-BE-NEXT: lsls r3, r2, #29
321 ; CHECK-BE-NEXT: itt mi
322 ; CHECK-BE-NEXT: ldrmi r3, [r0, #8]
323 ; CHECK-BE-NEXT: vmovmi.32 q0[2], r3
324 ; CHECK-BE-NEXT: lsls r2, r2, #28
325 ; CHECK-BE-NEXT: itt mi
326 ; CHECK-BE-NEXT: ldrmi r2, [r0, #12]
327 ; CHECK-BE-NEXT: vmovmi.32 q0[3], r2
111328 ; CHECK-BE-NEXT: vstrw.32 q0, [r1]
112 ; CHECK-BE-NEXT: adds r0, #4
329 ; CHECK-BE-NEXT: add sp, #4
113330 ; CHECK-BE-NEXT: bx lr
114331 entry:
115332 %z = getelementptr inbounds i8, i8* %x, i32 4
124341 define arm_aapcs_vfpcc i8* @masked_v4i32_postinc(i8* %x, i8* %y, <4 x i32> %a) {
125342 ; CHECK-LE-LABEL: masked_v4i32_postinc:
126343 ; CHECK-LE: @ %bb.0: @ %entry
344 ; CHECK-LE-NEXT: .pad #4
345 ; CHECK-LE-NEXT: sub sp, #4
127346 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
128 ; CHECK-LE-NEXT: vpst
129 ; CHECK-LE-NEXT: vldrwt.u32 q0, [r0]
347 ; CHECK-LE-NEXT: mov r2, sp
348 ; CHECK-LE-NEXT: vstr p0, [r2]
349 ; CHECK-LE-NEXT: @ implicit-def: $q0
350 ; CHECK-LE-NEXT: add.w r12, r0, #4
351 ; CHECK-LE-NEXT: ldrb.w r3, [sp]
352 ; CHECK-LE-NEXT: lsls r2, r3, #31
353 ; CHECK-LE-NEXT: itt ne
354 ; CHECK-LE-NEXT: ldrne r2, [r0]
355 ; CHECK-LE-NEXT: vmovne.32 q0[0], r2
356 ; CHECK-LE-NEXT: lsls r2, r3, #30
357 ; CHECK-LE-NEXT: itt mi
358 ; CHECK-LE-NEXT: ldrmi r2, [r0, #4]
359 ; CHECK-LE-NEXT: vmovmi.32 q0[1], r2
360 ; CHECK-LE-NEXT: lsls r2, r3, #29
361 ; CHECK-LE-NEXT: itt mi
362 ; CHECK-LE-NEXT: ldrmi r2, [r0, #8]
363 ; CHECK-LE-NEXT: vmovmi.32 q0[2], r2
364 ; CHECK-LE-NEXT: lsls r2, r3, #28
365 ; CHECK-LE-NEXT: itt mi
366 ; CHECK-LE-NEXT: ldrmi r0, [r0, #12]
367 ; CHECK-LE-NEXT: vmovmi.32 q0[3], r0
130368 ; CHECK-LE-NEXT: vstrw.32 q0, [r1]
131 ; CHECK-LE-NEXT: adds r0, #4
369 ; CHECK-LE-NEXT: mov r0, r12
370 ; CHECK-LE-NEXT: add sp, #4
132371 ; CHECK-LE-NEXT: bx lr
133372 ;
134373 ; CHECK-BE-LABEL: masked_v4i32_postinc:
135374 ; CHECK-BE: @ %bb.0: @ %entry
375 ; CHECK-BE-NEXT: .pad #4
376 ; CHECK-BE-NEXT: sub sp, #4
136377 ; CHECK-BE-NEXT: vrev64.32 q1, q0
378 ; CHECK-BE-NEXT: mov r2, sp
137379 ; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr
138 ; CHECK-BE-NEXT: vpst
139 ; CHECK-BE-NEXT: vldrwt.u32 q0, [r0]
380 ; CHECK-BE-NEXT: @ implicit-def: $q0
381 ; CHECK-BE-NEXT: add.w r12, r0, #4
382 ; CHECK-BE-NEXT: vstr p0, [r2]
383 ; CHECK-BE-NEXT: ldrb.w r3, [sp]
384 ; CHECK-BE-NEXT: lsls r2, r3, #31
385 ; CHECK-BE-NEXT: itt ne
386 ; CHECK-BE-NEXT: ldrne r2, [r0]
387 ; CHECK-BE-NEXT: vmovne.32 q0[0], r2
388 ; CHECK-BE-NEXT: lsls r2, r3, #30
389 ; CHECK-BE-NEXT: itt mi
390 ; CHECK-BE-NEXT: ldrmi r2, [r0, #4]
391 ; CHECK-BE-NEXT: vmovmi.32 q0[1], r2
392 ; CHECK-BE-NEXT: lsls r2, r3, #29
393 ; CHECK-BE-NEXT: itt mi
394 ; CHECK-BE-NEXT: ldrmi r2, [r0, #8]
395 ; CHECK-BE-NEXT: vmovmi.32 q0[2], r2
396 ; CHECK-BE-NEXT: lsls r2, r3, #28
397 ; CHECK-BE-NEXT: itt mi
398 ; CHECK-BE-NEXT: ldrmi r0, [r0, #12]
399 ; CHECK-BE-NEXT: vmovmi.32 q0[3], r0
140400 ; CHECK-BE-NEXT: vstrw.32 q0, [r1]
141 ; CHECK-BE-NEXT: adds r0, #4
401 ; CHECK-BE-NEXT: mov r0, r12
402 ; CHECK-BE-NEXT: add sp, #4
142403 ; CHECK-BE-NEXT: bx lr
143404 entry:
144405 %z = getelementptr inbounds i8, i8* %x, i32 4
155416 define arm_aapcs_vfpcc <8 x i16> @masked_v8i16_align4_zero(<8 x i16> *%dest, <8 x i16> %a) {
156417 ; CHECK-LE-LABEL: masked_v8i16_align4_zero:
157418 ; CHECK-LE: @ %bb.0: @ %entry
158 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
419 ; CHECK-LE-NEXT: .pad #8
420 ; CHECK-LE-NEXT: sub sp, #8
421 ; CHECK-LE-NEXT: mov r1, sp
159422 ; CHECK-LE-NEXT: vcmp.s16 gt, q0, zr
160 ; CHECK-LE-NEXT: vpst
161 ; CHECK-LE-NEXT: vldrht.u16 q0, [r0]
162 ; CHECK-LE-NEXT: vpsel q0, q0, q1
423 ; CHECK-LE-NEXT: vstr p0, [r1]
424 ; CHECK-LE-NEXT: ldrb.w r1, [sp]
425 ; CHECK-LE-NEXT: lsls r2, r1, #31
426 ; CHECK-LE-NEXT: beq .LBB6_2
427 ; CHECK-LE-NEXT: @ %bb.1: @ %cond.load
428 ; CHECK-LE-NEXT: movs r2, #0
429 ; CHECK-LE-NEXT: ldrh r3, [r0]
430 ; CHECK-LE-NEXT: vdup.16 q0, r2
431 ; CHECK-LE-NEXT: vmov.16 q0[0], r3
432 ; CHECK-LE-NEXT: b .LBB6_3
433 ; CHECK-LE-NEXT: .LBB6_2:
434 ; CHECK-LE-NEXT: vmov.i32 q0, #0x0
435 ; CHECK-LE-NEXT: .LBB6_3: @ %else
436 ; CHECK-LE-NEXT: lsls r2, r1, #30
437 ; CHECK-LE-NEXT: itt mi
438 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #2]
439 ; CHECK-LE-NEXT: vmovmi.16 q0[1], r2
440 ; CHECK-LE-NEXT: lsls r2, r1, #29
441 ; CHECK-LE-NEXT: itt mi
442 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #4]
443 ; CHECK-LE-NEXT: vmovmi.16 q0[2], r2
444 ; CHECK-LE-NEXT: lsls r2, r1, #28
445 ; CHECK-LE-NEXT: itt mi
446 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #6]
447 ; CHECK-LE-NEXT: vmovmi.16 q0[3], r2
448 ; CHECK-LE-NEXT: lsls r2, r1, #27
449 ; CHECK-LE-NEXT: itt mi
450 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #8]
451 ; CHECK-LE-NEXT: vmovmi.16 q0[4], r2
452 ; CHECK-LE-NEXT: lsls r2, r1, #26
453 ; CHECK-LE-NEXT: itt mi
454 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #10]
455 ; CHECK-LE-NEXT: vmovmi.16 q0[5], r2
456 ; CHECK-LE-NEXT: lsls r2, r1, #25
457 ; CHECK-LE-NEXT: itt mi
458 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #12]
459 ; CHECK-LE-NEXT: vmovmi.16 q0[6], r2
460 ; CHECK-LE-NEXT: lsls r1, r1, #24
461 ; CHECK-LE-NEXT: itt mi
462 ; CHECK-LE-NEXT: ldrhmi r0, [r0, #14]
463 ; CHECK-LE-NEXT: vmovmi.16 q0[7], r0
464 ; CHECK-LE-NEXT: add sp, #8
163465 ; CHECK-LE-NEXT: bx lr
164466 ;
165467 ; CHECK-BE-LABEL: masked_v8i16_align4_zero:
166468 ; CHECK-BE: @ %bb.0: @ %entry
167 ; CHECK-BE-NEXT: vmov.i32 q1, #0x0
168 ; CHECK-BE-NEXT: vrev64.16 q2, q0
169 ; CHECK-BE-NEXT: vrev32.16 q1, q1
170 ; CHECK-BE-NEXT: vcmp.s16 gt, q2, zr
171 ; CHECK-BE-NEXT: vpst
172 ; CHECK-BE-NEXT: vldrht.u16 q0, [r0]
173 ; CHECK-BE-NEXT: vpsel q1, q0, q1
469 ; CHECK-BE-NEXT: .pad #8
470 ; CHECK-BE-NEXT: sub sp, #8
471 ; CHECK-BE-NEXT: vrev64.16 q1, q0
472 ; CHECK-BE-NEXT: mov r1, sp
473 ; CHECK-BE-NEXT: vcmp.s16 gt, q1, zr
474 ; CHECK-BE-NEXT: vstr p0, [r1]
475 ; CHECK-BE-NEXT: ldrb.w r1, [sp]
476 ; CHECK-BE-NEXT: lsls r2, r1, #31
477 ; CHECK-BE-NEXT: beq .LBB6_2
478 ; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
479 ; CHECK-BE-NEXT: movs r2, #0
480 ; CHECK-BE-NEXT: ldrh r3, [r0]
481 ; CHECK-BE-NEXT: vdup.16 q1, r2
482 ; CHECK-BE-NEXT: vmov.16 q1[0], r3
483 ; CHECK-BE-NEXT: b .LBB6_3
484 ; CHECK-BE-NEXT: .LBB6_2:
485 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
486 ; CHECK-BE-NEXT: vrev32.16 q1, q0
487 ; CHECK-BE-NEXT: .LBB6_3: @ %else
488 ; CHECK-BE-NEXT: lsls r2, r1, #30
489 ; CHECK-BE-NEXT: itt mi
490 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #2]
491 ; CHECK-BE-NEXT: vmovmi.16 q1[1], r2
492 ; CHECK-BE-NEXT: lsls r2, r1, #29
493 ; CHECK-BE-NEXT: itt mi
494 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #4]
495 ; CHECK-BE-NEXT: vmovmi.16 q1[2], r2
496 ; CHECK-BE-NEXT: lsls r2, r1, #28
497 ; CHECK-BE-NEXT: itt mi
498 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #6]
499 ; CHECK-BE-NEXT: vmovmi.16 q1[3], r2
500 ; CHECK-BE-NEXT: lsls r2, r1, #27
501 ; CHECK-BE-NEXT: itt mi
502 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #8]
503 ; CHECK-BE-NEXT: vmovmi.16 q1[4], r2
504 ; CHECK-BE-NEXT: lsls r2, r1, #26
505 ; CHECK-BE-NEXT: itt mi
506 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #10]
507 ; CHECK-BE-NEXT: vmovmi.16 q1[5], r2
508 ; CHECK-BE-NEXT: lsls r2, r1, #25
509 ; CHECK-BE-NEXT: itt mi
510 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #12]
511 ; CHECK-BE-NEXT: vmovmi.16 q1[6], r2
512 ; CHECK-BE-NEXT: lsls r1, r1, #24
513 ; CHECK-BE-NEXT: itt mi
514 ; CHECK-BE-NEXT: ldrhmi r0, [r0, #14]
515 ; CHECK-BE-NEXT: vmovmi.16 q1[7], r0
174516 ; CHECK-BE-NEXT: vrev64.16 q0, q1
517 ; CHECK-BE-NEXT: add sp, #8
175518 ; CHECK-BE-NEXT: bx lr
176519 entry:
177520 %c = icmp sgt <8 x i16> %a, zeroinitializer
182525 define arm_aapcs_vfpcc <8 x i16> @masked_v8i16_align4_undef(<8 x i16> *%dest, <8 x i16> %a) {
183526 ; CHECK-LE-LABEL: masked_v8i16_align4_undef:
184527 ; CHECK-LE: @ %bb.0: @ %entry
528 ; CHECK-LE-NEXT: .pad #8
529 ; CHECK-LE-NEXT: sub sp, #8
185530 ; CHECK-LE-NEXT: vcmp.s16 gt, q0, zr
186 ; CHECK-LE-NEXT: vpst
187 ; CHECK-LE-NEXT: vldrht.u16 q0, [r0]
531 ; CHECK-LE-NEXT: mov r1, sp
532 ; CHECK-LE-NEXT: vstr p0, [r1]
533 ; CHECK-LE-NEXT: @ implicit-def: $q0
534 ; CHECK-LE-NEXT: ldrb.w r1, [sp]
535 ; CHECK-LE-NEXT: lsls r2, r1, #31
536 ; CHECK-LE-NEXT: itt ne
537 ; CHECK-LE-NEXT: ldrhne r2, [r0]
538 ; CHECK-LE-NEXT: vmovne.16 q0[0], r2
539 ; CHECK-LE-NEXT: lsls r2, r1, #30
540 ; CHECK-LE-NEXT: itt mi
541 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #2]
542 ; CHECK-LE-NEXT: vmovmi.16 q0[1], r2
543 ; CHECK-LE-NEXT: lsls r2, r1, #29
544 ; CHECK-LE-NEXT: itt mi
545 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #4]
546 ; CHECK-LE-NEXT: vmovmi.16 q0[2], r2
547 ; CHECK-LE-NEXT: lsls r2, r1, #28
548 ; CHECK-LE-NEXT: itt mi
549 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #6]
550 ; CHECK-LE-NEXT: vmovmi.16 q0[3], r2
551 ; CHECK-LE-NEXT: lsls r2, r1, #27
552 ; CHECK-LE-NEXT: itt mi
553 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #8]
554 ; CHECK-LE-NEXT: vmovmi.16 q0[4], r2
555 ; CHECK-LE-NEXT: lsls r2, r1, #26
556 ; CHECK-LE-NEXT: itt mi
557 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #10]
558 ; CHECK-LE-NEXT: vmovmi.16 q0[5], r2
559 ; CHECK-LE-NEXT: lsls r2, r1, #25
560 ; CHECK-LE-NEXT: itt mi
561 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #12]
562 ; CHECK-LE-NEXT: vmovmi.16 q0[6], r2
563 ; CHECK-LE-NEXT: lsls r1, r1, #24
564 ; CHECK-LE-NEXT: itt mi
565 ; CHECK-LE-NEXT: ldrhmi r0, [r0, #14]
566 ; CHECK-LE-NEXT: vmovmi.16 q0[7], r0
567 ; CHECK-LE-NEXT: add sp, #8
188568 ; CHECK-LE-NEXT: bx lr
189569 ;
190570 ; CHECK-BE-LABEL: masked_v8i16_align4_undef:
191571 ; CHECK-BE: @ %bb.0: @ %entry
572 ; CHECK-BE-NEXT: .pad #8
573 ; CHECK-BE-NEXT: sub sp, #8
192574 ; CHECK-BE-NEXT: vrev64.16 q1, q0
575 ; CHECK-BE-NEXT: mov r1, sp
193576 ; CHECK-BE-NEXT: vcmp.s16 gt, q1, zr
194 ; CHECK-BE-NEXT: vpst
195 ; CHECK-BE-NEXT: vldrht.u16 q1, [r0]
577 ; CHECK-BE-NEXT: @ implicit-def: $q1
578 ; CHECK-BE-NEXT: vstr p0, [r1]
579 ; CHECK-BE-NEXT: ldrb.w r1, [sp]
580 ; CHECK-BE-NEXT: lsls r2, r1, #31
581 ; CHECK-BE-NEXT: itt ne
582 ; CHECK-BE-NEXT: ldrhne r2, [r0]
583 ; CHECK-BE-NEXT: vmovne.16 q1[0], r2
584 ; CHECK-BE-NEXT: lsls r2, r1, #30
585 ; CHECK-BE-NEXT: itt mi
586 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #2]
587 ; CHECK-BE-NEXT: vmovmi.16 q1[1], r2
588 ; CHECK-BE-NEXT: lsls r2, r1, #29
589 ; CHECK-BE-NEXT: itt mi
590 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #4]
591 ; CHECK-BE-NEXT: vmovmi.16 q1[2], r2
592 ; CHECK-BE-NEXT: lsls r2, r1, #28
593 ; CHECK-BE-NEXT: itt mi
594 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #6]
595 ; CHECK-BE-NEXT: vmovmi.16 q1[3], r2
596 ; CHECK-BE-NEXT: lsls r2, r1, #27
597 ; CHECK-BE-NEXT: itt mi
598 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #8]
599 ; CHECK-BE-NEXT: vmovmi.16 q1[4], r2
600 ; CHECK-BE-NEXT: lsls r2, r1, #26
601 ; CHECK-BE-NEXT: itt mi
602 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #10]
603 ; CHECK-BE-NEXT: vmovmi.16 q1[5], r2
604 ; CHECK-BE-NEXT: lsls r2, r1, #25
605 ; CHECK-BE-NEXT: itt mi
606 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #12]
607 ; CHECK-BE-NEXT: vmovmi.16 q1[6], r2
608 ; CHECK-BE-NEXT: lsls r1, r1, #24
609 ; CHECK-BE-NEXT: itt mi
610 ; CHECK-BE-NEXT: ldrhmi r0, [r0, #14]
611 ; CHECK-BE-NEXT: vmovmi.16 q1[7], r0
196612 ; CHECK-BE-NEXT: vrev64.16 q0, q1
613 ; CHECK-BE-NEXT: add sp, #8
197614 ; CHECK-BE-NEXT: bx lr
198615 entry:
199616 %c = icmp sgt <8 x i16> %a, zeroinitializer
204621 define arm_aapcs_vfpcc <8 x i16> @masked_v8i16_align1_undef(<8 x i16> *%dest, <8 x i16> %a) {
205622 ; CHECK-LE-LABEL: masked_v8i16_align1_undef:
206623 ; CHECK-LE: @ %bb.0: @ %entry
624 ; CHECK-LE-NEXT: .pad #8
625 ; CHECK-LE-NEXT: sub sp, #8
207626 ; CHECK-LE-NEXT: vcmp.s16 gt, q0, zr
208 ; CHECK-LE-NEXT: vpst
209 ; CHECK-LE-NEXT: vldrbt.u8 q0, [r0]
627 ; CHECK-LE-NEXT: mov r1, sp
628 ; CHECK-LE-NEXT: vstr p0, [r1]
629 ; CHECK-LE-NEXT: @ implicit-def: $q0
630 ; CHECK-LE-NEXT: ldrb.w r1, [sp]
631 ; CHECK-LE-NEXT: lsls r2, r1, #31
632 ; CHECK-LE-NEXT: itt ne
633 ; CHECK-LE-NEXT: ldrhne r2, [r0]
634 ; CHECK-LE-NEXT: vmovne.16 q0[0], r2
635 ; CHECK-LE-NEXT: lsls r2, r1, #30
636 ; CHECK-LE-NEXT: itt mi
637 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #2]
638 ; CHECK-LE-NEXT: vmovmi.16 q0[1], r2
639 ; CHECK-LE-NEXT: lsls r2, r1, #29
640 ; CHECK-LE-NEXT: itt mi
641 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #4]
642 ; CHECK-LE-NEXT: vmovmi.16 q0[2], r2
643 ; CHECK-LE-NEXT: lsls r2, r1, #28
644 ; CHECK-LE-NEXT: itt mi
645 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #6]
646 ; CHECK-LE-NEXT: vmovmi.16 q0[3], r2
647 ; CHECK-LE-NEXT: lsls r2, r1, #27
648 ; CHECK-LE-NEXT: itt mi
649 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #8]
650 ; CHECK-LE-NEXT: vmovmi.16 q0[4], r2
651 ; CHECK-LE-NEXT: lsls r2, r1, #26
652 ; CHECK-LE-NEXT: itt mi
653 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #10]
654 ; CHECK-LE-NEXT: vmovmi.16 q0[5], r2
655 ; CHECK-LE-NEXT: lsls r2, r1, #25
656 ; CHECK-LE-NEXT: itt mi
657 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #12]
658 ; CHECK-LE-NEXT: vmovmi.16 q0[6], r2
659 ; CHECK-LE-NEXT: lsls r1, r1, #24
660 ; CHECK-LE-NEXT: itt mi
661 ; CHECK-LE-NEXT: ldrhmi r0, [r0, #14]
662 ; CHECK-LE-NEXT: vmovmi.16 q0[7], r0
663 ; CHECK-LE-NEXT: add sp, #8
210664 ; CHECK-LE-NEXT: bx lr
211665 ;
212666 ; CHECK-BE-LABEL: masked_v8i16_align1_undef:
213667 ; CHECK-BE: @ %bb.0: @ %entry
668 ; CHECK-BE-NEXT: .pad #8
669 ; CHECK-BE-NEXT: sub sp, #8
214670 ; CHECK-BE-NEXT: vrev64.16 q1, q0
671 ; CHECK-BE-NEXT: mov r1, sp
215672 ; CHECK-BE-NEXT: vcmp.s16 gt, q1, zr
216 ; CHECK-BE-NEXT: vpst
217 ; CHECK-BE-NEXT: vldrbt.u8 q0, [r0]
218 ; CHECK-BE-NEXT: vrev16.8 q1, q0
673 ; CHECK-BE-NEXT: @ implicit-def: $q1
674 ; CHECK-BE-NEXT: vstr p0, [r1]
675 ; CHECK-BE-NEXT: ldrb.w r1, [sp]
676 ; CHECK-BE-NEXT: lsls r2, r1, #31
677 ; CHECK-BE-NEXT: itt ne
678 ; CHECK-BE-NEXT: ldrhne r2, [r0]
679 ; CHECK-BE-NEXT: vmovne.16 q1[0], r2
680 ; CHECK-BE-NEXT: lsls r2, r1, #30
681 ; CHECK-BE-NEXT: itt mi
682 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #2]
683 ; CHECK-BE-NEXT: vmovmi.16 q1[1], r2
684 ; CHECK-BE-NEXT: lsls r2, r1, #29
685 ; CHECK-BE-NEXT: itt mi
686 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #4]
687 ; CHECK-BE-NEXT: vmovmi.16 q1[2], r2
688 ; CHECK-BE-NEXT: lsls r2, r1, #28
689 ; CHECK-BE-NEXT: itt mi
690 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #6]
691 ; CHECK-BE-NEXT: vmovmi.16 q1[3], r2
692 ; CHECK-BE-NEXT: lsls r2, r1, #27
693 ; CHECK-BE-NEXT: itt mi
694 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #8]
695 ; CHECK-BE-NEXT: vmovmi.16 q1[4], r2
696 ; CHECK-BE-NEXT: lsls r2, r1, #26
697 ; CHECK-BE-NEXT: itt mi
698 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #10]
699 ; CHECK-BE-NEXT: vmovmi.16 q1[5], r2
700 ; CHECK-BE-NEXT: lsls r2, r1, #25
701 ; CHECK-BE-NEXT: itt mi
702 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #12]
703 ; CHECK-BE-NEXT: vmovmi.16 q1[6], r2
704 ; CHECK-BE-NEXT: lsls r1, r1, #24
705 ; CHECK-BE-NEXT: itt mi
706 ; CHECK-BE-NEXT: ldrhmi r0, [r0, #14]
707 ; CHECK-BE-NEXT: vmovmi.16 q1[7], r0
219708 ; CHECK-BE-NEXT: vrev64.16 q0, q1
709 ; CHECK-BE-NEXT: add sp, #8
220710 ; CHECK-BE-NEXT: bx lr
221711 entry:
222712 %c = icmp sgt <8 x i16> %a, zeroinitializer
227717 define arm_aapcs_vfpcc <8 x i16> @masked_v8i16_align4_other(<8 x i16> *%dest, <8 x i16> %a) {
228718 ; CHECK-LE-LABEL: masked_v8i16_align4_other:
229719 ; CHECK-LE: @ %bb.0: @ %entry
720 ; CHECK-LE-NEXT: .pad #8
721 ; CHECK-LE-NEXT: sub sp, #8
722 ; CHECK-LE-NEXT: mov r1, sp
230723 ; CHECK-LE-NEXT: vcmp.s16 gt, q0, zr
231 ; CHECK-LE-NEXT: vpst
232 ; CHECK-LE-NEXT: vldrht.u16 q1, [r0]
233 ; CHECK-LE-NEXT: vpsel q0, q1, q0
724 ; CHECK-LE-NEXT: vstr p0, [r1]
725 ; CHECK-LE-NEXT: ldrb.w r1, [sp]
726 ; CHECK-LE-NEXT: lsls r2, r1, #31
727 ; CHECK-LE-NEXT: itt ne
728 ; CHECK-LE-NEXT: ldrhne r2, [r0]
729 ; CHECK-LE-NEXT: vmovne.16 q0[0], r2
730 ; CHECK-LE-NEXT: lsls r2, r1, #30
731 ; CHECK-LE-NEXT: itt mi
732 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #2]
733 ; CHECK-LE-NEXT: vmovmi.16 q0[1], r2
734 ; CHECK-LE-NEXT: lsls r2, r1, #29
735 ; CHECK-LE-NEXT: itt mi
736 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #4]
737 ; CHECK-LE-NEXT: vmovmi.16 q0[2], r2
738 ; CHECK-LE-NEXT: lsls r2, r1, #28
739 ; CHECK-LE-NEXT: itt mi
740 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #6]
741 ; CHECK-LE-NEXT: vmovmi.16 q0[3], r2
742 ; CHECK-LE-NEXT: lsls r2, r1, #27
743 ; CHECK-LE-NEXT: itt mi
744 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #8]
745 ; CHECK-LE-NEXT: vmovmi.16 q0[4], r2
746 ; CHECK-LE-NEXT: lsls r2, r1, #26
747 ; CHECK-LE-NEXT: itt mi
748 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #10]
749 ; CHECK-LE-NEXT: vmovmi.16 q0[5], r2
750 ; CHECK-LE-NEXT: lsls r2, r1, #25
751 ; CHECK-LE-NEXT: itt mi
752 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #12]
753 ; CHECK-LE-NEXT: vmovmi.16 q0[6], r2
754 ; CHECK-LE-NEXT: lsls r1, r1, #24
755 ; CHECK-LE-NEXT: itt mi
756 ; CHECK-LE-NEXT: ldrhmi r0, [r0, #14]
757 ; CHECK-LE-NEXT: vmovmi.16 q0[7], r0
758 ; CHECK-LE-NEXT: add sp, #8
234759 ; CHECK-LE-NEXT: bx lr
235760 ;
236761 ; CHECK-BE-LABEL: masked_v8i16_align4_other:
237762 ; CHECK-BE: @ %bb.0: @ %entry
763 ; CHECK-BE-NEXT: .pad #8
764 ; CHECK-BE-NEXT: sub sp, #8
238765 ; CHECK-BE-NEXT: vrev64.16 q1, q0
766 ; CHECK-BE-NEXT: mov r1, sp
239767 ; CHECK-BE-NEXT: vcmp.s16 gt, q1, zr
240 ; CHECK-BE-NEXT: vpst
241 ; CHECK-BE-NEXT: vldrht.u16 q0, [r0]
242 ; CHECK-BE-NEXT: vpsel q1, q0, q1
768 ; CHECK-BE-NEXT: vstr p0, [r1]
769 ; CHECK-BE-NEXT: ldrb.w r1, [sp]
770 ; CHECK-BE-NEXT: lsls r2, r1, #31
771 ; CHECK-BE-NEXT: itt ne
772 ; CHECK-BE-NEXT: ldrhne r2, [r0]
773 ; CHECK-BE-NEXT: vmovne.16 q1[0], r2
774 ; CHECK-BE-NEXT: lsls r2, r1, #30
775 ; CHECK-BE-NEXT: itt mi
776 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #2]
777 ; CHECK-BE-NEXT: vmovmi.16 q1[1], r2
778 ; CHECK-BE-NEXT: lsls r2, r1, #29
779 ; CHECK-BE-NEXT: itt mi
780 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #4]
781 ; CHECK-BE-NEXT: vmovmi.16 q1[2], r2
782 ; CHECK-BE-NEXT: lsls r2, r1, #28
783 ; CHECK-BE-NEXT: itt mi
784 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #6]
785 ; CHECK-BE-NEXT: vmovmi.16 q1[3], r2
786 ; CHECK-BE-NEXT: lsls r2, r1, #27
787 ; CHECK-BE-NEXT: itt mi
788 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #8]
789 ; CHECK-BE-NEXT: vmovmi.16 q1[4], r2
790 ; CHECK-BE-NEXT: lsls r2, r1, #26
791 ; CHECK-BE-NEXT: itt mi
792 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #10]
793 ; CHECK-BE-NEXT: vmovmi.16 q1[5], r2
794 ; CHECK-BE-NEXT: lsls r2, r1, #25
795 ; CHECK-BE-NEXT: itt mi
796 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #12]
797 ; CHECK-BE-NEXT: vmovmi.16 q1[6], r2
798 ; CHECK-BE-NEXT: lsls r1, r1, #24
799 ; CHECK-BE-NEXT: itt mi
800 ; CHECK-BE-NEXT: ldrhmi r0, [r0, #14]
801 ; CHECK-BE-NEXT: vmovmi.16 q1[7], r0
243802 ; CHECK-BE-NEXT: vrev64.16 q0, q1
803 ; CHECK-BE-NEXT: add sp, #8
244804 ; CHECK-BE-NEXT: bx lr
245805 entry:
246806 %c = icmp sgt <8 x i16> %a, zeroinitializer
251811 define i8* @masked_v8i16_preinc(i8* %x, i8* %y, <8 x i16> %a) {
252812 ; CHECK-LE-LABEL: masked_v8i16_preinc:
253813 ; CHECK-LE: @ %bb.0: @ %entry
254 ; CHECK-LE-NEXT: vldr d1, [sp]
814 ; CHECK-LE-NEXT: .pad #8
815 ; CHECK-LE-NEXT: sub sp, #8
816 ; CHECK-LE-NEXT: vldr d1, [sp, #8]
817 ; CHECK-LE-NEXT: adds r0, #4
255818 ; CHECK-LE-NEXT: vmov d0, r2, r3
819 ; CHECK-LE-NEXT: mov r2, sp
256820 ; CHECK-LE-NEXT: vcmp.s16 gt, q0, zr
257 ; CHECK-LE-NEXT: vpst
258 ; CHECK-LE-NEXT: vldrht.u16 q0, [r0, #4]
821 ; CHECK-LE-NEXT: @ implicit-def: $q0
822 ; CHECK-LE-NEXT: vstr p0, [r2]
823 ; CHECK-LE-NEXT: ldrb.w r2, [sp]
824 ; CHECK-LE-NEXT: lsls r3, r2, #31
825 ; CHECK-LE-NEXT: itt ne
826 ; CHECK-LE-NEXT: ldrhne r3, [r0]
827 ; CHECK-LE-NEXT: vmovne.16 q0[0], r3
828 ; CHECK-LE-NEXT: lsls r3, r2, #30
829 ; CHECK-LE-NEXT: itt mi
830 ; CHECK-LE-NEXT: ldrhmi r3, [r0, #2]
831 ; CHECK-LE-NEXT: vmovmi.16 q0[1], r3
832 ; CHECK-LE-NEXT: lsls r3, r2, #29
833 ; CHECK-LE-NEXT: itt mi
834 ; CHECK-LE-NEXT: ldrhmi r3, [r0, #4]
835 ; CHECK-LE-NEXT: vmovmi.16 q0[2], r3
836 ; CHECK-LE-NEXT: lsls r3, r2, #28
837 ; CHECK-LE-NEXT: itt mi
838 ; CHECK-LE-NEXT: ldrhmi r3, [r0, #6]
839 ; CHECK-LE-NEXT: vmovmi.16 q0[3], r3
840 ; CHECK-LE-NEXT: lsls r3, r2, #27
841 ; CHECK-LE-NEXT: itt mi
842 ; CHECK-LE-NEXT: ldrhmi r3, [r0, #8]
843 ; CHECK-LE-NEXT: vmovmi.16 q0[4], r3
844 ; CHECK-LE-NEXT: lsls r3, r2, #26
845 ; CHECK-LE-NEXT: itt mi
846 ; CHECK-LE-NEXT: ldrhmi r3, [r0, #10]
847 ; CHECK-LE-NEXT: vmovmi.16 q0[5], r3
848 ; CHECK-LE-NEXT: lsls r3, r2, #25
849 ; CHECK-LE-NEXT: itt mi
850 ; CHECK-LE-NEXT: ldrhmi r3, [r0, #12]
851 ; CHECK-LE-NEXT: vmovmi.16 q0[6], r3
852 ; CHECK-LE-NEXT: lsls r2, r2, #24
853 ; CHECK-LE-NEXT: itt mi
854 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #14]
855 ; CHECK-LE-NEXT: vmovmi.16 q0[7], r2
259856 ; CHECK-LE-NEXT: vstrw.32 q0, [r1]
260 ; CHECK-LE-NEXT: adds r0, #4
857 ; CHECK-LE-NEXT: add sp, #8
261858 ; CHECK-LE-NEXT: bx lr
262859 ;
263860 ; CHECK-BE-LABEL: masked_v8i16_preinc:
264861 ; CHECK-BE: @ %bb.0: @ %entry
265 ; CHECK-BE-NEXT: vldr d1, [sp]
862 ; CHECK-BE-NEXT: .pad #8
863 ; CHECK-BE-NEXT: sub sp, #8
864 ; CHECK-BE-NEXT: vldr d1, [sp, #8]
865 ; CHECK-BE-NEXT: adds r0, #4
266866 ; CHECK-BE-NEXT: vmov d0, r3, r2
867 ; CHECK-BE-NEXT: mov r2, sp
267868 ; CHECK-BE-NEXT: vrev64.16 q1, q0
869 ; CHECK-BE-NEXT: @ implicit-def: $q0
268870 ; CHECK-BE-NEXT: vcmp.s16 gt, q1, zr
269 ; CHECK-BE-NEXT: vpst
270 ; CHECK-BE-NEXT: vldrht.u16 q0, [r0, #4]
871 ; CHECK-BE-NEXT: vstr p0, [r2]
872 ; CHECK-BE-NEXT: ldrb.w r2, [sp]
873 ; CHECK-BE-NEXT: lsls r3, r2, #31
874 ; CHECK-BE-NEXT: itt ne
875 ; CHECK-BE-NEXT: ldrhne r3, [r0]
876 ; CHECK-BE-NEXT: vmovne.16 q0[0], r3
877 ; CHECK-BE-NEXT: lsls r3, r2, #30
878 ; CHECK-BE-NEXT: itt mi
879 ; CHECK-BE-NEXT: ldrhmi r3, [r0, #2]
880 ; CHECK-BE-NEXT: vmovmi.16 q0[1], r3
881 ; CHECK-BE-NEXT: lsls r3, r2, #29
882 ; CHECK-BE-NEXT: itt mi
883 ; CHECK-BE-NEXT: ldrhmi r3, [r0, #4]
884 ; CHECK-BE-NEXT: vmovmi.16 q0[2], r3
885 ; CHECK-BE-NEXT: lsls r3, r2, #28
886 ; CHECK-BE-NEXT: itt mi
887 ; CHECK-BE-NEXT: ldrhmi r3, [r0, #6]
888 ; CHECK-BE-NEXT: vmovmi.16 q0[3], r3
889 ; CHECK-BE-NEXT: lsls r3, r2, #27
890 ; CHECK-BE-NEXT: itt mi
891 ; CHECK-BE-NEXT: ldrhmi r3, [r0, #8]
892 ; CHECK-BE-NEXT: vmovmi.16 q0[4], r3
893 ; CHECK-BE-NEXT: lsls r3, r2, #26
894 ; CHECK-BE-NEXT: itt mi
895 ; CHECK-BE-NEXT: ldrhmi r3, [r0, #10]
896 ; CHECK-BE-NEXT: vmovmi.16 q0[5], r3
897 ; CHECK-BE-NEXT: lsls r3, r2, #25
898 ; CHECK-BE-NEXT: itt mi
899 ; CHECK-BE-NEXT: ldrhmi r3, [r0, #12]
900 ; CHECK-BE-NEXT: vmovmi.16 q0[6], r3
901 ; CHECK-BE-NEXT: lsls r2, r2, #24
902 ; CHECK-BE-NEXT: itt mi
903 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #14]
904 ; CHECK-BE-NEXT: vmovmi.16 q0[7], r2
271905 ; CHECK-BE-NEXT: vstrh.16 q0, [r1]
272 ; CHECK-BE-NEXT: adds r0, #4
906 ; CHECK-BE-NEXT: add sp, #8
273907 ; CHECK-BE-NEXT: bx lr
274908 entry:
275909 %z = getelementptr inbounds i8, i8* %x, i32 4
284918 define arm_aapcs_vfpcc i8* @masked_v8i16_postinc(i8* %x, i8* %y, <8 x i16> %a) {
285919 ; CHECK-LE-LABEL: masked_v8i16_postinc:
286920 ; CHECK-LE: @ %bb.0: @ %entry
921 ; CHECK-LE-NEXT: .pad #8
922 ; CHECK-LE-NEXT: sub sp, #8
287923 ; CHECK-LE-NEXT: vcmp.s16 gt, q0, zr
288 ; CHECK-LE-NEXT: vpst
289 ; CHECK-LE-NEXT: vldrht.u16 q0, [r0]
924 ; CHECK-LE-NEXT: mov r2, sp
925 ; CHECK-LE-NEXT: vstr p0, [r2]
926 ; CHECK-LE-NEXT: @ implicit-def: $q0
927 ; CHECK-LE-NEXT: add.w r12, r0, #4
928 ; CHECK-LE-NEXT: ldrb.w r3, [sp]
929 ; CHECK-LE-NEXT: lsls r2, r3, #31
930 ; CHECK-LE-NEXT: itt ne
931 ; CHECK-LE-NEXT: ldrhne r2, [r0]
932 ; CHECK-LE-NEXT: vmovne.16 q0[0], r2
933 ; CHECK-LE-NEXT: lsls r2, r3, #30
934 ; CHECK-LE-NEXT: itt mi
935 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #2]
936 ; CHECK-LE-NEXT: vmovmi.16 q0[1], r2
937 ; CHECK-LE-NEXT: lsls r2, r3, #29
938 ; CHECK-LE-NEXT: itt mi
939 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #4]
940 ; CHECK-LE-NEXT: vmovmi.16 q0[2], r2
941 ; CHECK-LE-NEXT: lsls r2, r3, #28
942 ; CHECK-LE-NEXT: itt mi
943 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #6]
944 ; CHECK-LE-NEXT: vmovmi.16 q0[3], r2
945 ; CHECK-LE-NEXT: lsls r2, r3, #27
946 ; CHECK-LE-NEXT: itt mi
947 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #8]
948 ; CHECK-LE-NEXT: vmovmi.16 q0[4], r2
949 ; CHECK-LE-NEXT: lsls r2, r3, #26
950 ; CHECK-LE-NEXT: itt mi
951 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #10]
952 ; CHECK-LE-NEXT: vmovmi.16 q0[5], r2
953 ; CHECK-LE-NEXT: lsls r2, r3, #25
954 ; CHECK-LE-NEXT: itt mi
955 ; CHECK-LE-NEXT: ldrhmi r2, [r0, #12]
956 ; CHECK-LE-NEXT: vmovmi.16 q0[6], r2
957 ; CHECK-LE-NEXT: lsls r2, r3, #24
958 ; CHECK-LE-NEXT: itt mi
959 ; CHECK-LE-NEXT: ldrhmi r0, [r0, #14]
960 ; CHECK-LE-NEXT: vmovmi.16 q0[7], r0
290961 ; CHECK-LE-NEXT: vstrw.32 q0, [r1]
291 ; CHECK-LE-NEXT: adds r0, #4
962 ; CHECK-LE-NEXT: mov r0, r12
963 ; CHECK-LE-NEXT: add sp, #8
292964 ; CHECK-LE-NEXT: bx lr
293965 ;
294966 ; CHECK-BE-LABEL: masked_v8i16_postinc:
295967 ; CHECK-BE: @ %bb.0: @ %entry
968 ; CHECK-BE-NEXT: .pad #8
969 ; CHECK-BE-NEXT: sub sp, #8
296970 ; CHECK-BE-NEXT: vrev64.16 q1, q0
971 ; CHECK-BE-NEXT: mov r2, sp
297972 ; CHECK-BE-NEXT: vcmp.s16 gt, q1, zr
298 ; CHECK-BE-NEXT: vpst
299 ; CHECK-BE-NEXT: vldrht.u16 q0, [r0]
973 ; CHECK-BE-NEXT: @ implicit-def: $q0
974 ; CHECK-BE-NEXT: add.w r12, r0, #4
975 ; CHECK-BE-NEXT: vstr p0, [r2]
976 ; CHECK-BE-NEXT: ldrb.w r3, [sp]
977 ; CHECK-BE-NEXT: lsls r2, r3, #31
978 ; CHECK-BE-NEXT: itt ne
979 ; CHECK-BE-NEXT: ldrhne r2, [r0]
980 ; CHECK-BE-NEXT: vmovne.16 q0[0], r2
981 ; CHECK-BE-NEXT: lsls r2, r3, #30
982 ; CHECK-BE-NEXT: itt mi
983 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #2]
984 ; CHECK-BE-NEXT: vmovmi.16 q0[1], r2
985 ; CHECK-BE-NEXT: lsls r2, r3, #29
986 ; CHECK-BE-NEXT: itt mi
987 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #4]
988 ; CHECK-BE-NEXT: vmovmi.16 q0[2], r2
989 ; CHECK-BE-NEXT: lsls r2, r3, #28
990 ; CHECK-BE-NEXT: itt mi
991 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #6]
992 ; CHECK-BE-NEXT: vmovmi.16 q0[3], r2
993 ; CHECK-BE-NEXT: lsls r2, r3, #27
994 ; CHECK-BE-NEXT: itt mi
995 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #8]
996 ; CHECK-BE-NEXT: vmovmi.16 q0[4], r2
997 ; CHECK-BE-NEXT: lsls r2, r3, #26
998 ; CHECK-BE-NEXT: itt mi
999 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #10]
1000 ; CHECK-BE-NEXT: vmovmi.16 q0[5], r2
1001 ; CHECK-BE-NEXT: lsls r2, r3, #25
1002 ; CHECK-BE-NEXT: itt mi
1003 ; CHECK-BE-NEXT: ldrhmi r2, [r0, #12]
1004 ; CHECK-BE-NEXT: vmovmi.16 q0[6], r2
1005 ; CHECK-BE-NEXT: lsls r2, r3, #24
1006 ; CHECK-BE-NEXT: itt mi
1007 ; CHECK-BE-NEXT: ldrhmi r0, [r0, #14]
1008 ; CHECK-BE-NEXT: vmovmi.16 q0[7], r0
3001009 ; CHECK-BE-NEXT: vstrh.16 q0, [r1]
301 ; CHECK-BE-NEXT: adds r0, #4
1010 ; CHECK-BE-NEXT: mov r0, r12
1011 ; CHECK-BE-NEXT: add sp, #8
3021012 ; CHECK-BE-NEXT: bx lr
3031013 entry:
3041014 %z = getelementptr inbounds i8, i8* %x, i32 4
3141024 define arm_aapcs_vfpcc <16 x i8> @masked_v16i8_align4_zero(<16 x i8> *%dest, <16 x i8> %a) {
3151025 ; CHECK-LE-LABEL: masked_v16i8_align4_zero:
3161026 ; CHECK-LE: @ %bb.0: @ %entry
317 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
1027 ; CHECK-LE-NEXT: .save {r4, r6, r7, lr}
1028 ; CHECK-LE-NEXT: push {r4, r6, r7, lr}
1029 ; CHECK-LE-NEXT: .setfp r7, sp, #8
1030 ; CHECK-LE-NEXT: add r7, sp, #8
1031 ; CHECK-LE-NEXT: .pad #16
1032 ; CHECK-LE-NEXT: sub sp, #16
1033 ; CHECK-LE-NEXT: mov r4, sp
1034 ; CHECK-LE-NEXT: bfc r4, #0, #4
1035 ; CHECK-LE-NEXT: mov sp, r4
1036 ; CHECK-LE-NEXT: mov r1, sp
3181037 ; CHECK-LE-NEXT: vcmp.s8 gt, q0, zr
319 ; CHECK-LE-NEXT: vpst
320 ; CHECK-LE-NEXT: vldrbt.u8 q0, [r0]
321 ; CHECK-LE-NEXT: vpsel q0, q0, q1
322 ; CHECK-LE-NEXT: bx lr
1038 ; CHECK-LE-NEXT: vstr p0, [r1]
1039 ; CHECK-LE-NEXT: ldrh.w r1, [sp]
1040 ; CHECK-LE-NEXT: lsls r2, r1, #31
1041 ; CHECK-LE-NEXT: beq .LBB12_2
1042 ; CHECK-LE-NEXT: @ %bb.1: @ %cond.load
1043 ; CHECK-LE-NEXT: movs r2, #0
1044 ; CHECK-LE-NEXT: ldrb r3, [r0]
1045 ; CHECK-LE-NEXT: vdup.8 q0, r2
1046 ; CHECK-LE-NEXT: vmov.8 q0[0], r3
1047 ; CHECK-LE-NEXT: b .LBB12_3
1048 ; CHECK-LE-NEXT: .LBB12_2:
1049 ; CHECK-LE-NEXT: vmov.i32 q0, #0x0
1050 ; CHECK-LE-NEXT: .LBB12_3: @ %else
1051 ; CHECK-LE-NEXT: lsls r2, r1, #30
1052 ; CHECK-LE-NEXT: itt mi
1053 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #1]
1054 ; CHECK-LE-NEXT: vmovmi.8 q0[1], r2
1055 ; CHECK-LE-NEXT: lsls r2, r1, #29
1056 ; CHECK-LE-NEXT: itt mi
1057 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #2]
1058 ; CHECK-LE-NEXT: vmovmi.8 q0[2], r2
1059 ; CHECK-LE-NEXT: lsls r2, r1, #28
1060 ; CHECK-LE-NEXT: itt mi
1061 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #3]
1062 ; CHECK-LE-NEXT: vmovmi.8 q0[3], r2
1063 ; CHECK-LE-NEXT: lsls r2, r1, #27
1064 ; CHECK-LE-NEXT: itt mi
1065 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #4]
1066 ; CHECK-LE-NEXT: vmovmi.8 q0[4], r2
1067 ; CHECK-LE-NEXT: lsls r2, r1, #26
1068 ; CHECK-LE-NEXT: itt mi
1069 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #5]
1070 ; CHECK-LE-NEXT: vmovmi.8 q0[5], r2
1071 ; CHECK-LE-NEXT: lsls r2, r1, #25
1072 ; CHECK-LE-NEXT: itt mi
1073 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #6]
1074 ; CHECK-LE-NEXT: vmovmi.8 q0[6], r2
1075 ; CHECK-LE-NEXT: lsls r2, r1, #24
1076 ; CHECK-LE-NEXT: itt mi
1077 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #7]
1078 ; CHECK-LE-NEXT: vmovmi.8 q0[7], r2
1079 ; CHECK-LE-NEXT: lsls r2, r1, #23
1080 ; CHECK-LE-NEXT: itt mi
1081 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #8]
1082 ; CHECK-LE-NEXT: vmovmi.8 q0[8], r2
1083 ; CHECK-LE-NEXT: lsls r2, r1, #22
1084 ; CHECK-LE-NEXT: itt mi
1085 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #9]
1086 ; CHECK-LE-NEXT: vmovmi.8 q0[9], r2
1087 ; CHECK-LE-NEXT: lsls r2, r1, #21
1088 ; CHECK-LE-NEXT: itt mi
1089 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #10]
1090 ; CHECK-LE-NEXT: vmovmi.8 q0[10], r2
1091 ; CHECK-LE-NEXT: lsls r2, r1, #20
1092 ; CHECK-LE-NEXT: itt mi
1093 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #11]
1094 ; CHECK-LE-NEXT: vmovmi.8 q0[11], r2
1095 ; CHECK-LE-NEXT: lsls r2, r1, #19
1096 ; CHECK-LE-NEXT: itt mi
1097 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #12]
1098 ; CHECK-LE-NEXT: vmovmi.8 q0[12], r2
1099 ; CHECK-LE-NEXT: lsls r2, r1, #18
1100 ; CHECK-LE-NEXT: itt mi
1101 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #13]
1102 ; CHECK-LE-NEXT: vmovmi.8 q0[13], r2
1103 ; CHECK-LE-NEXT: sub.w r4, r7, #8
1104 ; CHECK-LE-NEXT: lsls r2, r1, #17
1105 ; CHECK-LE-NEXT: itt mi
1106 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #14]
1107 ; CHECK-LE-NEXT: vmovmi.8 q0[14], r2
1108 ; CHECK-LE-NEXT: lsls r1, r1, #16
1109 ; CHECK-LE-NEXT: itt mi
1110 ; CHECK-LE-NEXT: ldrbmi r0, [r0, #15]
1111 ; CHECK-LE-NEXT: vmovmi.8 q0[15], r0
1112 ; CHECK-LE-NEXT: mov sp, r4
1113 ; CHECK-LE-NEXT: pop {r4, r6, r7, pc}
3231114 ;
3241115 ; CHECK-BE-LABEL: masked_v16i8_align4_zero:
3251116 ; CHECK-BE: @ %bb.0: @ %entry
326 ; CHECK-BE-NEXT: vmov.i32 q1, #0x0
327 ; CHECK-BE-NEXT: vrev64.8 q2, q0
328 ; CHECK-BE-NEXT: vrev32.8 q1, q1
329 ; CHECK-BE-NEXT: vcmp.s8 gt, q2, zr
330 ; CHECK-BE-NEXT: vpst
331 ; CHECK-BE-NEXT: vldrbt.u8 q0, [r0]
332 ; CHECK-BE-NEXT: vpsel q1, q0, q1
1117 ; CHECK-BE-NEXT: .save {r4, r6, r7, lr}
1118 ; CHECK-BE-NEXT: push {r4, r6, r7, lr}
1119 ; CHECK-BE-NEXT: .setfp r7, sp, #8
1120 ; CHECK-BE-NEXT: add r7, sp, #8
1121 ; CHECK-BE-NEXT: .pad #16
1122 ; CHECK-BE-NEXT: sub sp, #16
1123 ; CHECK-BE-NEXT: mov r4, sp
1124 ; CHECK-BE-NEXT: bfc r4, #0, #4
1125 ; CHECK-BE-NEXT: mov sp, r4
1126 ; CHECK-BE-NEXT: vrev64.8 q1, q0
1127 ; CHECK-BE-NEXT: mov r1, sp
1128 ; CHECK-BE-NEXT: vcmp.s8 gt, q1, zr
1129 ; CHECK-BE-NEXT: vstr p0, [r1]
1130 ; CHECK-BE-NEXT: ldrh.w r1, [sp]
1131 ; CHECK-BE-NEXT: lsls r2, r1, #31
1132 ; CHECK-BE-NEXT: beq .LBB12_2
1133 ; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
1134 ; CHECK-BE-NEXT: movs r2, #0
1135 ; CHECK-BE-NEXT: ldrb r3, [r0]
1136 ; CHECK-BE-NEXT: vdup.8 q1, r2
1137 ; CHECK-BE-NEXT: vmov.8 q1[0], r3
1138 ; CHECK-BE-NEXT: b .LBB12_3
1139 ; CHECK-BE-NEXT: .LBB12_2:
1140 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
1141 ; CHECK-BE-NEXT: vrev32.8 q1, q0
1142 ; CHECK-BE-NEXT: .LBB12_3: @ %else
1143 ; CHECK-BE-NEXT: lsls r2, r1, #30
1144 ; CHECK-BE-NEXT: itt mi
1145 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #1]
1146 ; CHECK-BE-NEXT: vmovmi.8 q1[1], r2
1147 ; CHECK-BE-NEXT: lsls r2, r1, #29
1148 ; CHECK-BE-NEXT: itt mi
1149 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #2]
1150 ; CHECK-BE-NEXT: vmovmi.8 q1[2], r2
1151 ; CHECK-BE-NEXT: lsls r2, r1, #28
1152 ; CHECK-BE-NEXT: itt mi
1153 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #3]
1154 ; CHECK-BE-NEXT: vmovmi.8 q1[3], r2
1155 ; CHECK-BE-NEXT: lsls r2, r1, #27
1156 ; CHECK-BE-NEXT: itt mi
1157 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #4]
1158 ; CHECK-BE-NEXT: vmovmi.8 q1[4], r2
1159 ; CHECK-BE-NEXT: lsls r2, r1, #26
1160 ; CHECK-BE-NEXT: itt mi
1161 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #5]
1162 ; CHECK-BE-NEXT: vmovmi.8 q1[5], r2
1163 ; CHECK-BE-NEXT: lsls r2, r1, #25
1164 ; CHECK-BE-NEXT: itt mi
1165 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #6]
1166 ; CHECK-BE-NEXT: vmovmi.8 q1[6], r2
1167 ; CHECK-BE-NEXT: lsls r2, r1, #24
1168 ; CHECK-BE-NEXT: itt mi
1169 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #7]
1170 ; CHECK-BE-NEXT: vmovmi.8 q1[7], r2
1171 ; CHECK-BE-NEXT: lsls r2, r1, #23
1172 ; CHECK-BE-NEXT: itt mi
1173 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #8]
1174 ; CHECK-BE-NEXT: vmovmi.8 q1[8], r2
1175 ; CHECK-BE-NEXT: lsls r2, r1, #22
1176 ; CHECK-BE-NEXT: itt mi
1177 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #9]
1178 ; CHECK-BE-NEXT: vmovmi.8 q1[9], r2
1179 ; CHECK-BE-NEXT: lsls r2, r1, #21
1180 ; CHECK-BE-NEXT: itt mi
1181 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #10]
1182 ; CHECK-BE-NEXT: vmovmi.8 q1[10], r2
1183 ; CHECK-BE-NEXT: lsls r2, r1, #20
1184 ; CHECK-BE-NEXT: itt mi
1185 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #11]
1186 ; CHECK-BE-NEXT: vmovmi.8 q1[11], r2
1187 ; CHECK-BE-NEXT: lsls r2, r1, #19
1188 ; CHECK-BE-NEXT: itt mi
1189 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #12]
1190 ; CHECK-BE-NEXT: vmovmi.8 q1[12], r2
1191 ; CHECK-BE-NEXT: lsls r2, r1, #18
1192 ; CHECK-BE-NEXT: itt mi
1193 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #13]
1194 ; CHECK-BE-NEXT: vmovmi.8 q1[13], r2
1195 ; CHECK-BE-NEXT: sub.w r4, r7, #8
1196 ; CHECK-BE-NEXT: lsls r2, r1, #17
1197 ; CHECK-BE-NEXT: itt mi
1198 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #14]
1199 ; CHECK-BE-NEXT: vmovmi.8 q1[14], r2
1200 ; CHECK-BE-NEXT: lsls r1, r1, #16
1201 ; CHECK-BE-NEXT: itt mi
1202 ; CHECK-BE-NEXT: ldrbmi r0, [r0, #15]
1203 ; CHECK-BE-NEXT: vmovmi.8 q1[15], r0
3331204 ; CHECK-BE-NEXT: vrev64.8 q0, q1
334 ; CHECK-BE-NEXT: bx lr
1205 ; CHECK-BE-NEXT: mov sp, r4
1206 ; CHECK-BE-NEXT: pop {r4, r6, r7, pc}
3351207 entry:
3361208 %c = icmp sgt <16 x i8> %a, zeroinitializer
3371209 %l = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %dest, i32 1, <16 x i1> %c, <16 x i8> zeroinitializer)
3411213 define arm_aapcs_vfpcc <16 x i8> @masked_v16i8_align4_undef(<16 x i8> *%dest, <16 x i8> %a) {
3421214 ; CHECK-LE-LABEL: masked_v16i8_align4_undef:
3431215 ; CHECK-LE: @ %bb.0: @ %entry
1216 ; CHECK-LE-NEXT: .save {r4, r6, r7, lr}
1217 ; CHECK-LE-NEXT: push {r4, r6, r7, lr}
1218 ; CHECK-LE-NEXT: .setfp r7, sp, #8
1219 ; CHECK-LE-NEXT: add r7, sp, #8
1220 ; CHECK-LE-NEXT: .pad #16
1221 ; CHECK-LE-NEXT: sub sp, #16
1222 ; CHECK-LE-NEXT: mov r4, sp
1223 ; CHECK-LE-NEXT: bfc r4, #0, #4
1224 ; CHECK-LE-NEXT: mov sp, r4
3441225 ; CHECK-LE-NEXT: vcmp.s8 gt, q0, zr
345 ; CHECK-LE-NEXT: vpst
346 ; CHECK-LE-NEXT: vldrbt.u8 q0, [r0]
347 ; CHECK-LE-NEXT: bx lr
1226 ; CHECK-LE-NEXT: mov r1, sp
1227 ; CHECK-LE-NEXT: vstr p0, [r1]
1228 ; CHECK-LE-NEXT: @ implicit-def: $q0
1229 ; CHECK-LE-NEXT: sub.w r4, r7, #8
1230 ; CHECK-LE-NEXT: ldrh.w r1, [sp]
1231 ; CHECK-LE-NEXT: lsls r2, r1, #31
1232 ; CHECK-LE-NEXT: itt ne
1233 ; CHECK-LE-NEXT: ldrbne r2, [r0]
1234 ; CHECK-LE-NEXT: vmovne.8 q0[0], r2
1235 ; CHECK-LE-NEXT: lsls r2, r1, #30
1236 ; CHECK-LE-NEXT: itt mi
1237 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #1]
1238 ; CHECK-LE-NEXT: vmovmi.8 q0[1], r2
1239 ; CHECK-LE-NEXT: lsls r2, r1, #29
1240 ; CHECK-LE-NEXT: itt mi
1241 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #2]
1242 ; CHECK-LE-NEXT: vmovmi.8 q0[2], r2
1243 ; CHECK-LE-NEXT: lsls r2, r1, #28
1244 ; CHECK-LE-NEXT: itt mi
1245 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #3]
1246 ; CHECK-LE-NEXT: vmovmi.8 q0[3], r2
1247 ; CHECK-LE-NEXT: lsls r2, r1, #27
1248 ; CHECK-LE-NEXT: itt mi
1249 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #4]
1250 ; CHECK-LE-NEXT: vmovmi.8 q0[4], r2
1251 ; CHECK-LE-NEXT: lsls r2, r1, #26
1252 ; CHECK-LE-NEXT: itt mi
1253 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #5]
1254 ; CHECK-LE-NEXT: vmovmi.8 q0[5], r2
1255 ; CHECK-LE-NEXT: lsls r2, r1, #25
1256 ; CHECK-LE-NEXT: itt mi
1257 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #6]
1258 ; CHECK-LE-NEXT: vmovmi.8 q0[6], r2
1259 ; CHECK-LE-NEXT: lsls r2, r1, #24
1260 ; CHECK-LE-NEXT: itt mi
1261 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #7]
1262 ; CHECK-LE-NEXT: vmovmi.8 q0[7], r2
1263 ; CHECK-LE-NEXT: lsls r2, r1, #23
1264 ; CHECK-LE-NEXT: itt mi
1265 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #8]
1266 ; CHECK-LE-NEXT: vmovmi.8 q0[8], r2
1267 ; CHECK-LE-NEXT: lsls r2, r1, #22
1268 ; CHECK-LE-NEXT: itt mi
1269 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #9]
1270 ; CHECK-LE-NEXT: vmovmi.8 q0[9], r2
1271 ; CHECK-LE-NEXT: lsls r2, r1, #21
1272 ; CHECK-LE-NEXT: itt mi
1273 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #10]
1274 ; CHECK-LE-NEXT: vmovmi.8 q0[10], r2
1275 ; CHECK-LE-NEXT: lsls r2, r1, #20
1276 ; CHECK-LE-NEXT: itt mi
1277 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #11]
1278 ; CHECK-LE-NEXT: vmovmi.8 q0[11], r2
1279 ; CHECK-LE-NEXT: lsls r2, r1, #19
1280 ; CHECK-LE-NEXT: itt mi
1281 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #12]
1282 ; CHECK-LE-NEXT: vmovmi.8 q0[12], r2
1283 ; CHECK-LE-NEXT: lsls r2, r1, #18
1284 ; CHECK-LE-NEXT: itt mi
1285 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #13]
1286 ; CHECK-LE-NEXT: vmovmi.8 q0[13], r2
1287 ; CHECK-LE-NEXT: lsls r2, r1, #17
1288 ; CHECK-LE-NEXT: itt mi
1289 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #14]
1290 ; CHECK-LE-NEXT: vmovmi.8 q0[14], r2
1291 ; CHECK-LE-NEXT: lsls r1, r1, #16
1292 ; CHECK-LE-NEXT: itt mi
1293 ; CHECK-LE-NEXT: ldrbmi r0, [r0, #15]
1294 ; CHECK-LE-NEXT: vmovmi.8 q0[15], r0
1295 ; CHECK-LE-NEXT: mov sp, r4
1296 ; CHECK-LE-NEXT: pop {r4, r6, r7, pc}
3481297 ;
3491298 ; CHECK-BE-LABEL: masked_v16i8_align4_undef:
3501299 ; CHECK-BE: @ %bb.0: @ %entry
1300 ; CHECK-BE-NEXT: .save {r4, r6, r7, lr}
1301 ; CHECK-BE-NEXT: push {r4, r6, r7, lr}
1302 ; CHECK-BE-NEXT: .setfp r7, sp, #8
1303 ; CHECK-BE-NEXT: add r7, sp, #8
1304 ; CHECK-BE-NEXT: .pad #16
1305 ; CHECK-BE-NEXT: sub sp, #16
1306 ; CHECK-BE-NEXT: mov r4, sp
1307 ; CHECK-BE-NEXT: bfc r4, #0, #4
1308 ; CHECK-BE-NEXT: mov sp, r4
3511309 ; CHECK-BE-NEXT: vrev64.8 q1, q0
1310 ; CHECK-BE-NEXT: mov r1, sp
3521311 ; CHECK-BE-NEXT: vcmp.s8 gt, q1, zr
353 ; CHECK-BE-NEXT: vpst
354 ; CHECK-BE-NEXT: vldrbt.u8 q1, [r0]
1312 ; CHECK-BE-NEXT: @ implicit-def: $q1
1313 ; CHECK-BE-NEXT: sub.w r4, r7, #8
1314 ; CHECK-BE-NEXT: vstr p0, [r1]
1315 ; CHECK-BE-NEXT: ldrh.w r1, [sp]
1316 ; CHECK-BE-NEXT: lsls r2, r1, #31
1317 ; CHECK-BE-NEXT: itt ne
1318 ; CHECK-BE-NEXT: ldrbne r2, [r0]
1319 ; CHECK-BE-NEXT: vmovne.8 q1[0], r2
1320 ; CHECK-BE-NEXT: lsls r2, r1, #30
1321 ; CHECK-BE-NEXT: itt mi
1322 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #1]
1323 ; CHECK-BE-NEXT: vmovmi.8 q1[1], r2
1324 ; CHECK-BE-NEXT: lsls r2, r1, #29
1325 ; CHECK-BE-NEXT: itt mi
1326 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #2]
1327 ; CHECK-BE-NEXT: vmovmi.8 q1[2], r2
1328 ; CHECK-BE-NEXT: lsls r2, r1, #28
1329 ; CHECK-BE-NEXT: itt mi
1330 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #3]
1331 ; CHECK-BE-NEXT: vmovmi.8 q1[3], r2
1332 ; CHECK-BE-NEXT: lsls r2, r1, #27
1333 ; CHECK-BE-NEXT: itt mi
1334 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #4]
1335 ; CHECK-BE-NEXT: vmovmi.8 q1[4], r2
1336 ; CHECK-BE-NEXT: lsls r2, r1, #26
1337 ; CHECK-BE-NEXT: itt mi
1338 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #5]
1339 ; CHECK-BE-NEXT: vmovmi.8 q1[5], r2
1340 ; CHECK-BE-NEXT: lsls r2, r1, #25
1341 ; CHECK-BE-NEXT: itt mi
1342 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #6]
1343 ; CHECK-BE-NEXT: vmovmi.8 q1[6], r2
1344 ; CHECK-BE-NEXT: lsls r2, r1, #24
1345 ; CHECK-BE-NEXT: itt mi
1346 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #7]
1347 ; CHECK-BE-NEXT: vmovmi.8 q1[7], r2
1348 ; CHECK-BE-NEXT: lsls r2, r1, #23
1349 ; CHECK-BE-NEXT: itt mi
1350 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #8]
1351 ; CHECK-BE-NEXT: vmovmi.8 q1[8], r2
1352 ; CHECK-BE-NEXT: lsls r2, r1, #22
1353 ; CHECK-BE-NEXT: itt mi
1354 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #9]
1355 ; CHECK-BE-NEXT: vmovmi.8 q1[9], r2
1356 ; CHECK-BE-NEXT: lsls r2, r1, #21
1357 ; CHECK-BE-NEXT: itt mi
1358 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #10]
1359 ; CHECK-BE-NEXT: vmovmi.8 q1[10], r2
1360 ; CHECK-BE-NEXT: lsls r2, r1, #20
1361 ; CHECK-BE-NEXT: itt mi
1362 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #11]
1363 ; CHECK-BE-NEXT: vmovmi.8 q1[11], r2
1364 ; CHECK-BE-NEXT: lsls r2, r1, #19
1365 ; CHECK-BE-NEXT: itt mi
1366 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #12]
1367 ; CHECK-BE-NEXT: vmovmi.8 q1[12], r2
1368 ; CHECK-BE-NEXT: lsls r2, r1, #18
1369 ; CHECK-BE-NEXT: itt mi
1370 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #13]
1371 ; CHECK-BE-NEXT: vmovmi.8 q1[13], r2
1372 ; CHECK-BE-NEXT: lsls r2, r1, #17
1373 ; CHECK-BE-NEXT: itt mi
1374 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #14]
1375 ; CHECK-BE-NEXT: vmovmi.8 q1[14], r2
1376 ; CHECK-BE-NEXT: lsls r1, r1, #16
1377 ; CHECK-BE-NEXT: itt mi
1378 ; CHECK-BE-NEXT: ldrbmi r0, [r0, #15]
1379 ; CHECK-BE-NEXT: vmovmi.8 q1[15], r0
3551380 ; CHECK-BE-NEXT: vrev64.8 q0, q1
356 ; CHECK-BE-NEXT: bx lr
1381 ; CHECK-BE-NEXT: mov sp, r4
1382 ; CHECK-BE-NEXT: pop {r4, r6, r7, pc}
3571383 entry:
3581384 %c = icmp sgt <16 x i8> %a, zeroinitializer
3591385 %l = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %dest, i32 1, <16 x i1> %c, <16 x i8> undef)
3631389 define arm_aapcs_vfpcc <16 x i8> @masked_v16i8_align4_other(<16 x i8> *%dest, <16 x i8> %a) {
3641390 ; CHECK-LE-LABEL: masked_v16i8_align4_other:
3651391 ; CHECK-LE: @ %bb.0: @ %entry
1392 ; CHECK-LE-NEXT: .save {r4, r6, r7, lr}
1393 ; CHECK-LE-NEXT: push {r4, r6, r7, lr}
1394 ; CHECK-LE-NEXT: .setfp r7, sp, #8
1395 ; CHECK-LE-NEXT: add r7, sp, #8
1396 ; CHECK-LE-NEXT: .pad #16
1397 ; CHECK-LE-NEXT: sub sp, #16
1398 ; CHECK-LE-NEXT: mov r4, sp
1399 ; CHECK-LE-NEXT: bfc r4, #0, #4
1400 ; CHECK-LE-NEXT: mov sp, r4
1401 ; CHECK-LE-NEXT: mov r1, sp
3661402 ; CHECK-LE-NEXT: vcmp.s8 gt, q0, zr
367 ; CHECK-LE-NEXT: vpst
368 ; CHECK-LE-NEXT: vldrbt.u8 q1, [r0]
369 ; CHECK-LE-NEXT: vpsel q0, q1, q0
370 ; CHECK-LE-NEXT: bx lr
1403 ; CHECK-LE-NEXT: vstr p0, [r1]
1404 ; CHECK-LE-NEXT: sub.w r4, r7, #8
1405 ; CHECK-LE-NEXT: ldrh.w r1, [sp]
1406 ; CHECK-LE-NEXT: lsls r2, r1, #31
1407 ; CHECK-LE-NEXT: itt ne
1408 ; CHECK-LE-NEXT: ldrbne r2, [r0]
1409 ; CHECK-LE-NEXT: vmovne.8 q0[0], r2
1410 ; CHECK-LE-NEXT: lsls r2, r1, #30
1411 ; CHECK-LE-NEXT: itt mi
1412 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #1]
1413 ; CHECK-LE-NEXT: vmovmi.8 q0[1], r2
1414 ; CHECK-LE-NEXT: lsls r2, r1, #29
1415 ; CHECK-LE-NEXT: itt mi
1416 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #2]
1417 ; CHECK-LE-NEXT: vmovmi.8 q0[2], r2
1418 ; CHECK-LE-NEXT: lsls r2, r1, #28
1419 ; CHECK-LE-NEXT: itt mi
1420 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #3]
1421 ; CHECK-LE-NEXT: vmovmi.8 q0[3], r2
1422 ; CHECK-LE-NEXT: lsls r2, r1, #27
1423 ; CHECK-LE-NEXT: itt mi
1424 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #4]
1425 ; CHECK-LE-NEXT: vmovmi.8 q0[4], r2
1426 ; CHECK-LE-NEXT: lsls r2, r1, #26
1427 ; CHECK-LE-NEXT: itt mi
1428 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #5]
1429 ; CHECK-LE-NEXT: vmovmi.8 q0[5], r2
1430 ; CHECK-LE-NEXT: lsls r2, r1, #25
1431 ; CHECK-LE-NEXT: itt mi
1432 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #6]
1433 ; CHECK-LE-NEXT: vmovmi.8 q0[6], r2
1434 ; CHECK-LE-NEXT: lsls r2, r1, #24
1435 ; CHECK-LE-NEXT: itt mi
1436 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #7]
1437 ; CHECK-LE-NEXT: vmovmi.8 q0[7], r2
1438 ; CHECK-LE-NEXT: lsls r2, r1, #23
1439 ; CHECK-LE-NEXT: itt mi
1440 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #8]
1441 ; CHECK-LE-NEXT: vmovmi.8 q0[8], r2
1442 ; CHECK-LE-NEXT: lsls r2, r1, #22
1443 ; CHECK-LE-NEXT: itt mi
1444 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #9]
1445 ; CHECK-LE-NEXT: vmovmi.8 q0[9], r2
1446 ; CHECK-LE-NEXT: lsls r2, r1, #21
1447 ; CHECK-LE-NEXT: itt mi
1448 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #10]
1449 ; CHECK-LE-NEXT: vmovmi.8 q0[10], r2
1450 ; CHECK-LE-NEXT: lsls r2, r1, #20
1451 ; CHECK-LE-NEXT: itt mi
1452 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #11]
1453 ; CHECK-LE-NEXT: vmovmi.8 q0[11], r2
1454 ; CHECK-LE-NEXT: lsls r2, r1, #19
1455 ; CHECK-LE-NEXT: itt mi
1456 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #12]
1457 ; CHECK-LE-NEXT: vmovmi.8 q0[12], r2
1458 ; CHECK-LE-NEXT: lsls r2, r1, #18
1459 ; CHECK-LE-NEXT: itt mi
1460 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #13]
1461 ; CHECK-LE-NEXT: vmovmi.8 q0[13], r2
1462 ; CHECK-LE-NEXT: lsls r2, r1, #17
1463 ; CHECK-LE-NEXT: itt mi
1464 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #14]
1465 ; CHECK-LE-NEXT: vmovmi.8 q0[14], r2
1466 ; CHECK-LE-NEXT: lsls r1, r1, #16
1467 ; CHECK-LE-NEXT: itt mi
1468 ; CHECK-LE-NEXT: ldrbmi r0, [r0, #15]
1469 ; CHECK-LE-NEXT: vmovmi.8 q0[15], r0
1470 ; CHECK-LE-NEXT: mov sp, r4
1471 ; CHECK-LE-NEXT: pop {r4, r6, r7, pc}
3711472 ;
3721473 ; CHECK-BE-LABEL: masked_v16i8_align4_other:
3731474 ; CHECK-BE: @ %bb.0: @ %entry
1475 ; CHECK-BE-NEXT: .save {r4, r6, r7, lr}
1476 ; CHECK-BE-NEXT: push {r4, r6, r7, lr}
1477 ; CHECK-BE-NEXT: .setfp r7, sp, #8
1478 ; CHECK-BE-NEXT: add r7, sp, #8
1479 ; CHECK-BE-NEXT: .pad #16
1480 ; CHECK-BE-NEXT: sub sp, #16
1481 ; CHECK-BE-NEXT: mov r4, sp
1482 ; CHECK-BE-NEXT: bfc r4, #0, #4
1483 ; CHECK-BE-NEXT: mov sp, r4
3741484 ; CHECK-BE-NEXT: vrev64.8 q1, q0
1485 ; CHECK-BE-NEXT: mov r1, sp
3751486 ; CHECK-BE-NEXT: vcmp.s8 gt, q1, zr
376 ; CHECK-BE-NEXT: vpst
377 ; CHECK-BE-NEXT: vldrbt.u8 q0, [r0]
378 ; CHECK-BE-NEXT: vpsel q1, q0, q1
1487 ; CHECK-BE-NEXT: sub.w r4, r7, #8
1488 ; CHECK-BE-NEXT: vstr p0, [r1]
1489 ; CHECK-BE-NEXT: ldrh.w r1, [sp]
1490 ; CHECK-BE-NEXT: lsls r2, r1, #31
1491 ; CHECK-BE-NEXT: itt ne
1492 ; CHECK-BE-NEXT: ldrbne r2, [r0]
1493 ; CHECK-BE-NEXT: vmovne.8 q1[0], r2
1494 ; CHECK-BE-NEXT: lsls r2, r1, #30
1495 ; CHECK-BE-NEXT: itt mi
1496 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #1]
1497 ; CHECK-BE-NEXT: vmovmi.8 q1[1], r2
1498 ; CHECK-BE-NEXT: lsls r2, r1, #29
1499 ; CHECK-BE-NEXT: itt mi
1500 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #2]
1501 ; CHECK-BE-NEXT: vmovmi.8 q1[2], r2
1502 ; CHECK-BE-NEXT: lsls r2, r1, #28
1503 ; CHECK-BE-NEXT: itt mi
1504 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #3]
1505 ; CHECK-BE-NEXT: vmovmi.8 q1[3], r2
1506 ; CHECK-BE-NEXT: lsls r2, r1, #27
1507 ; CHECK-BE-NEXT: itt mi
1508 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #4]
1509 ; CHECK-BE-NEXT: vmovmi.8 q1[4], r2
1510 ; CHECK-BE-NEXT: lsls r2, r1, #26
1511 ; CHECK-BE-NEXT: itt mi
1512 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #5]
1513 ; CHECK-BE-NEXT: vmovmi.8 q1[5], r2
1514 ; CHECK-BE-NEXT: lsls r2, r1, #25
1515 ; CHECK-BE-NEXT: itt mi
1516 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #6]
1517 ; CHECK-BE-NEXT: vmovmi.8 q1[6], r2
1518 ; CHECK-BE-NEXT: lsls r2, r1, #24
1519 ; CHECK-BE-NEXT: itt mi
1520 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #7]
1521 ; CHECK-BE-NEXT: vmovmi.8 q1[7], r2
1522 ; CHECK-BE-NEXT: lsls r2, r1, #23
1523 ; CHECK-BE-NEXT: itt mi
1524 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #8]
1525 ; CHECK-BE-NEXT: vmovmi.8 q1[8], r2
1526 ; CHECK-BE-NEXT: lsls r2, r1, #22
1527 ; CHECK-BE-NEXT: itt mi
1528 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #9]
1529 ; CHECK-BE-NEXT: vmovmi.8 q1[9], r2
1530 ; CHECK-BE-NEXT: lsls r2, r1, #21
1531 ; CHECK-BE-NEXT: itt mi
1532 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #10]
1533 ; CHECK-BE-NEXT: vmovmi.8 q1[10], r2
1534 ; CHECK-BE-NEXT: lsls r2, r1, #20
1535 ; CHECK-BE-NEXT: itt mi
1536 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #11]
1537 ; CHECK-BE-NEXT: vmovmi.8 q1[11], r2
1538 ; CHECK-BE-NEXT: lsls r2, r1, #19
1539 ; CHECK-BE-NEXT: itt mi
1540 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #12]
1541 ; CHECK-BE-NEXT: vmovmi.8 q1[12], r2
1542 ; CHECK-BE-NEXT: lsls r2, r1, #18
1543 ; CHECK-BE-NEXT: itt mi
1544 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #13]
1545 ; CHECK-BE-NEXT: vmovmi.8 q1[13], r2
1546 ; CHECK-BE-NEXT: lsls r2, r1, #17
1547 ; CHECK-BE-NEXT: itt mi
1548 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #14]
1549 ; CHECK-BE-NEXT: vmovmi.8 q1[14], r2
1550 ; CHECK-BE-NEXT: lsls r1, r1, #16
1551 ; CHECK-BE-NEXT: itt mi
1552 ; CHECK-BE-NEXT: ldrbmi r0, [r0, #15]
1553 ; CHECK-BE-NEXT: vmovmi.8 q1[15], r0
3791554 ; CHECK-BE-NEXT: vrev64.8 q0, q1
380 ; CHECK-BE-NEXT: bx lr
1555 ; CHECK-BE-NEXT: mov sp, r4
1556 ; CHECK-BE-NEXT: pop {r4, r6, r7, pc}
3811557 entry:
3821558 %c = icmp sgt <16 x i8> %a, zeroinitializer
3831559 %l = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %dest, i32 1, <16 x i1> %c, <16 x i8> %a)
3871563 define arm_aapcs_vfpcc i8* @masked_v16i8_preinc(i8* %x, i8* %y, <16 x i8> %a) {
3881564 ; CHECK-LE-LABEL: masked_v16i8_preinc:
3891565 ; CHECK-LE: @ %bb.0: @ %entry
1566 ; CHECK-LE-NEXT: .save {r4, r6, r7, lr}
1567 ; CHECK-LE-NEXT: push {r4, r6, r7, lr}
1568 ; CHECK-LE-NEXT: .setfp r7, sp, #8
1569 ; CHECK-LE-NEXT: add r7, sp, #8
1570 ; CHECK-LE-NEXT: .pad #16
1571 ; CHECK-LE-NEXT: sub sp, #16
1572 ; CHECK-LE-NEXT: mov r4, sp
1573 ; CHECK-LE-NEXT: bfc r4, #0, #4
1574 ; CHECK-LE-NEXT: mov sp, r4
3901575 ; CHECK-LE-NEXT: vcmp.s8 gt, q0, zr
391 ; CHECK-LE-NEXT: vpst
392 ; CHECK-LE-NEXT: vldrbt.u8 q0, [r0, #4]
1576 ; CHECK-LE-NEXT: mov r2, sp
1577 ; CHECK-LE-NEXT: vstr p0, [r2]
1578 ; CHECK-LE-NEXT: @ implicit-def: $q0
1579 ; CHECK-LE-NEXT: adds r0, #4
1580 ; CHECK-LE-NEXT: ldrh.w r2, [sp]
1581 ; CHECK-LE-NEXT: sub.w r4, r7, #8
1582 ; CHECK-LE-NEXT: lsls r3, r2, #31
1583 ; CHECK-LE-NEXT: itt ne
1584 ; CHECK-LE-NEXT: ldrbne r3, [r0]
1585 ; CHECK-LE-NEXT: vmovne.8 q0[0], r3
1586 ; CHECK-LE-NEXT: lsls r3, r2, #30
1587 ; CHECK-LE-NEXT: itt mi
1588 ; CHECK-LE-NEXT: ldrbmi r3, [r0, #1]
1589 ; CHECK-LE-NEXT: vmovmi.8 q0[1], r3
1590 ; CHECK-LE-NEXT: lsls r3, r2, #29
1591 ; CHECK-LE-NEXT: itt mi
1592 ; CHECK-LE-NEXT: ldrbmi r3, [r0, #2]
1593 ; CHECK-LE-NEXT: vmovmi.8 q0[2], r3
1594 ; CHECK-LE-NEXT: lsls r3, r2, #28
1595 ; CHECK-LE-NEXT: itt mi
1596 ; CHECK-LE-NEXT: ldrbmi r3, [r0, #3]
1597 ; CHECK-LE-NEXT: vmovmi.8 q0[3], r3
1598 ; CHECK-LE-NEXT: lsls r3, r2, #27
1599 ; CHECK-LE-NEXT: itt mi
1600 ; CHECK-LE-NEXT: ldrbmi r3, [r0, #4]
1601 ; CHECK-LE-NEXT: vmovmi.8 q0[4], r3
1602 ; CHECK-LE-NEXT: lsls r3, r2, #26
1603 ; CHECK-LE-NEXT: itt mi
1604 ; CHECK-LE-NEXT: ldrbmi r3, [r0, #5]
1605 ; CHECK-LE-NEXT: vmovmi.8 q0[5], r3
1606 ; CHECK-LE-NEXT: lsls r3, r2, #25
1607 ; CHECK-LE-NEXT: itt mi
1608 ; CHECK-LE-NEXT: ldrbmi r3, [r0, #6]
1609 ; CHECK-LE-NEXT: vmovmi.8 q0[6], r3
1610 ; CHECK-LE-NEXT: lsls r3, r2, #24
1611 ; CHECK-LE-NEXT: itt mi
1612 ; CHECK-LE-NEXT: ldrbmi r3, [r0, #7]
1613 ; CHECK-LE-NEXT: vmovmi.8 q0[7], r3
1614 ; CHECK-LE-NEXT: lsls r3, r2, #23
1615 ; CHECK-LE-NEXT: itt mi
1616 ; CHECK-LE-NEXT: ldrbmi r3, [r0, #8]
1617 ; CHECK-LE-NEXT: vmovmi.8 q0[8], r3
1618 ; CHECK-LE-NEXT: lsls r3, r2, #22
1619 ; CHECK-LE-NEXT: itt mi
1620 ; CHECK-LE-NEXT: ldrbmi r3, [r0, #9]
1621 ; CHECK-LE-NEXT: vmovmi.8 q0[9], r3
1622 ; CHECK-LE-NEXT: lsls r3, r2, #21
1623 ; CHECK-LE-NEXT: itt mi
1624 ; CHECK-LE-NEXT: ldrbmi r3, [r0, #10]
1625 ; CHECK-LE-NEXT: vmovmi.8 q0[10], r3
1626 ; CHECK-LE-NEXT: lsls r3, r2, #20
1627 ; CHECK-LE-NEXT: itt mi
1628 ; CHECK-LE-NEXT: ldrbmi r3, [r0, #11]
1629 ; CHECK-LE-NEXT: vmovmi.8 q0[11], r3
1630 ; CHECK-LE-NEXT: lsls r3, r2, #19
1631 ; CHECK-LE-NEXT: itt mi
1632 ; CHECK-LE-NEXT: ldrbmi r3, [r0, #12]
1633 ; CHECK-LE-NEXT: vmovmi.8 q0[12], r3
1634 ; CHECK-LE-NEXT: lsls r3, r2, #18
1635 ; CHECK-LE-NEXT: itt mi
1636 ; CHECK-LE-NEXT: ldrbmi r3, [r0, #13]
1637 ; CHECK-LE-NEXT: vmovmi.8 q0[13], r3
1638 ; CHECK-LE-NEXT: lsls r3, r2, #17
1639 ; CHECK-LE-NEXT: itt mi
1640 ; CHECK-LE-NEXT: ldrbmi r3, [r0, #14]
1641 ; CHECK-LE-NEXT: vmovmi.8 q0[14], r3
1642 ; CHECK-LE-NEXT: lsls r2, r2, #16
1643 ; CHECK-LE-NEXT: itt mi
1644 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #15]
1645 ; CHECK-LE-NEXT: vmovmi.8 q0[15], r2
3931646 ; CHECK-LE-NEXT: vstrw.32 q0, [r1]
394 ; CHECK-LE-NEXT: adds r0, #4
395 ; CHECK-LE-NEXT: bx lr
1647 ; CHECK-LE-NEXT: mov sp, r4
1648 ; CHECK-LE-NEXT: pop {r4, r6, r7, pc}
3961649 ;
3971650 ; CHECK-BE-LABEL: masked_v16i8_preinc:
3981651 ; CHECK-BE: @ %bb.0: @ %entry
1652 ; CHECK-BE-NEXT: .save {r4, r6, r7, lr}
1653 ; CHECK-BE-NEXT: push {r4, r6, r7, lr}
1654 ; CHECK-BE-NEXT: .setfp r7, sp, #8
1655 ; CHECK-BE-NEXT: add r7, sp, #8
1656 ; CHECK-BE-NEXT: .pad #16
1657 ; CHECK-BE-NEXT: sub sp, #16
1658 ; CHECK-BE-NEXT: mov r4, sp
1659 ; CHECK-BE-NEXT: bfc r4, #0, #4
1660 ; CHECK-BE-NEXT: mov sp, r4
3991661 ; CHECK-BE-NEXT: vrev64.8 q1, q0
1662 ; CHECK-BE-NEXT: mov r2, sp
4001663 ; CHECK-BE-NEXT: vcmp.s8 gt, q1, zr
401 ; CHECK-BE-NEXT: vpst
402 ; CHECK-BE-NEXT: vldrbt.u8 q0, [r0, #4]
1664 ; CHECK-BE-NEXT: @ implicit-def: $q0
1665 ; CHECK-BE-NEXT: adds r0, #4
1666 ; CHECK-BE-NEXT: vstr p0, [r2]
1667 ; CHECK-BE-NEXT: sub.w r4, r7, #8
1668 ; CHECK-BE-NEXT: ldrh.w r2, [sp]
1669 ; CHECK-BE-NEXT: lsls r3, r2, #31
1670 ; CHECK-BE-NEXT: itt ne
1671 ; CHECK-BE-NEXT: ldrbne r3, [r0]
1672 ; CHECK-BE-NEXT: vmovne.8 q0[0], r3
1673 ; CHECK-BE-NEXT: lsls r3, r2, #30
1674 ; CHECK-BE-NEXT: itt mi
1675 ; CHECK-BE-NEXT: ldrbmi r3, [r0, #1]
1676 ; CHECK-BE-NEXT: vmovmi.8 q0[1], r3
1677 ; CHECK-BE-NEXT: lsls r3, r2, #29
1678 ; CHECK-BE-NEXT: itt mi
1679 ; CHECK-BE-NEXT: ldrbmi r3, [r0, #2]
1680 ; CHECK-BE-NEXT: vmovmi.8 q0[2], r3
1681 ; CHECK-BE-NEXT: lsls r3, r2, #28
1682 ; CHECK-BE-NEXT: itt mi
1683 ; CHECK-BE-NEXT: ldrbmi r3, [r0, #3]
1684 ; CHECK-BE-NEXT: vmovmi.8 q0[3], r3
1685 ; CHECK-BE-NEXT: lsls r3, r2, #27
1686 ; CHECK-BE-NEXT: itt mi
1687 ; CHECK-BE-NEXT: ldrbmi r3, [r0, #4]
1688 ; CHECK-BE-NEXT: vmovmi.8 q0[4], r3
1689 ; CHECK-BE-NEXT: lsls r3, r2, #26
1690 ; CHECK-BE-NEXT: itt mi
1691 ; CHECK-BE-NEXT: ldrbmi r3, [r0, #5]
1692 ; CHECK-BE-NEXT: vmovmi.8 q0[5], r3
1693 ; CHECK-BE-NEXT: lsls r3, r2, #25
1694 ; CHECK-BE-NEXT: itt mi
1695 ; CHECK-BE-NEXT: ldrbmi r3, [r0, #6]
1696 ; CHECK-BE-NEXT: vmovmi.8 q0[6], r3
1697 ; CHECK-BE-NEXT: lsls r3, r2, #24
1698 ; CHECK-BE-NEXT: itt mi
1699 ; CHECK-BE-NEXT: ldrbmi r3, [r0, #7]
1700 ; CHECK-BE-NEXT: vmovmi.8 q0[7], r3
1701 ; CHECK-BE-NEXT: lsls r3, r2, #23
1702 ; CHECK-BE-NEXT: itt mi
1703 ; CHECK-BE-NEXT: ldrbmi r3, [r0, #8]
1704 ; CHECK-BE-NEXT: vmovmi.8 q0[8], r3
1705 ; CHECK-BE-NEXT: lsls r3, r2, #22
1706 ; CHECK-BE-NEXT: itt mi
1707 ; CHECK-BE-NEXT: ldrbmi r3, [r0, #9]
1708 ; CHECK-BE-NEXT: vmovmi.8 q0[9], r3
1709 ; CHECK-BE-NEXT: lsls r3, r2, #21
1710 ; CHECK-BE-NEXT: itt mi
1711 ; CHECK-BE-NEXT: ldrbmi r3, [r0, #10]
1712 ; CHECK-BE-NEXT: vmovmi.8 q0[10], r3
1713 ; CHECK-BE-NEXT: lsls r3, r2, #20
1714 ; CHECK-BE-NEXT: itt mi
1715 ; CHECK-BE-NEXT: ldrbmi r3, [r0, #11]
1716 ; CHECK-BE-NEXT: vmovmi.8 q0[11], r3
1717 ; CHECK-BE-NEXT: lsls r3, r2, #19
1718 ; CHECK-BE-NEXT: itt mi
1719 ; CHECK-BE-NEXT: ldrbmi r3, [r0, #12]
1720 ; CHECK-BE-NEXT: vmovmi.8 q0[12], r3
1721 ; CHECK-BE-NEXT: lsls r3, r2, #18
1722 ; CHECK-BE-NEXT: itt mi
1723 ; CHECK-BE-NEXT: ldrbmi r3, [r0, #13]
1724 ; CHECK-BE-NEXT: vmovmi.8 q0[13], r3
1725 ; CHECK-BE-NEXT: lsls r3, r2, #17
1726 ; CHECK-BE-NEXT: itt mi
1727 ; CHECK-BE-NEXT: ldrbmi r3, [r0, #14]
1728 ; CHECK-BE-NEXT: vmovmi.8 q0[14], r3
1729 ; CHECK-BE-NEXT: lsls r2, r2, #16
1730 ; CHECK-BE-NEXT: itt mi
1731 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #15]
1732 ; CHECK-BE-NEXT: vmovmi.8 q0[15], r2
4031733 ; CHECK-BE-NEXT: vstrb.8 q0, [r1]
404 ; CHECK-BE-NEXT: adds r0, #4
405 ; CHECK-BE-NEXT: bx lr
1734 ; CHECK-BE-NEXT: mov sp, r4
1735 ; CHECK-BE-NEXT: pop {r4, r6, r7, pc}
4061736 entry:
4071737 %z = getelementptr inbounds i8, i8* %x, i32 4
4081738 %0 = bitcast i8* %z to <16 x i8>*
4161746 define arm_aapcs_vfpcc i8* @masked_v16i8_postinc(i8* %x, i8* %y, <16 x i8> %a) {
4171747 ; CHECK-LE-LABEL: masked_v16i8_postinc:
4181748 ; CHECK-LE: @ %bb.0: @ %entry
1749 ; CHECK-LE-NEXT: .save {r4, r6, r7, lr}
1750 ; CHECK-LE-NEXT: push {r4, r6, r7, lr}
1751 ; CHECK-LE-NEXT: .setfp r7, sp, #8
1752 ; CHECK-LE-NEXT: add r7, sp, #8
1753 ; CHECK-LE-NEXT: .pad #16
1754 ; CHECK-LE-NEXT: sub sp, #16
1755 ; CHECK-LE-NEXT: mov r4, sp
1756 ; CHECK-LE-NEXT: bfc r4, #0, #4
1757 ; CHECK-LE-NEXT: mov sp, r4
4191758 ; CHECK-LE-NEXT: vcmp.s8 gt, q0, zr
420 ; CHECK-LE-NEXT: vpst
421 ; CHECK-LE-NEXT: vldrbt.u8 q0, [r0]
1759 ; CHECK-LE-NEXT: mov r2, sp
1760 ; CHECK-LE-NEXT: vstr p0, [r2]
1761 ; CHECK-LE-NEXT: @ implicit-def: $q0
1762 ; CHECK-LE-NEXT: sub.w r4, r7, #8
1763 ; CHECK-LE-NEXT: ldrh.w r3, [sp]
1764 ; CHECK-LE-NEXT: add.w r12, r0, #4
1765 ; CHECK-LE-NEXT: lsls r2, r3, #31
1766 ; CHECK-LE-NEXT: itt ne
1767 ; CHECK-LE-NEXT: ldrbne r2, [r0]
1768 ; CHECK-LE-NEXT: vmovne.8 q0[0], r2
1769 ; CHECK-LE-NEXT: lsls r2, r3, #30
1770 ; CHECK-LE-NEXT: itt mi
1771 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #1]
1772 ; CHECK-LE-NEXT: vmovmi.8 q0[1], r2
1773 ; CHECK-LE-NEXT: lsls r2, r3, #29
1774 ; CHECK-LE-NEXT: itt mi
1775 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #2]
1776 ; CHECK-LE-NEXT: vmovmi.8 q0[2], r2
1777 ; CHECK-LE-NEXT: lsls r2, r3, #28
1778 ; CHECK-LE-NEXT: itt mi
1779 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #3]
1780 ; CHECK-LE-NEXT: vmovmi.8 q0[3], r2
1781 ; CHECK-LE-NEXT: lsls r2, r3, #27
1782 ; CHECK-LE-NEXT: itt mi
1783 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #4]
1784 ; CHECK-LE-NEXT: vmovmi.8 q0[4], r2
1785 ; CHECK-LE-NEXT: lsls r2, r3, #26
1786 ; CHECK-LE-NEXT: itt mi
1787 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #5]
1788 ; CHECK-LE-NEXT: vmovmi.8 q0[5], r2
1789 ; CHECK-LE-NEXT: lsls r2, r3, #25
1790 ; CHECK-LE-NEXT: itt mi
1791 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #6]
1792 ; CHECK-LE-NEXT: vmovmi.8 q0[6], r2
1793 ; CHECK-LE-NEXT: lsls r2, r3, #24
1794 ; CHECK-LE-NEXT: itt mi
1795 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #7]
1796 ; CHECK-LE-NEXT: vmovmi.8 q0[7], r2
1797 ; CHECK-LE-NEXT: lsls r2, r3, #23
1798 ; CHECK-LE-NEXT: itt mi
1799 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #8]
1800 ; CHECK-LE-NEXT: vmovmi.8 q0[8], r2
1801 ; CHECK-LE-NEXT: lsls r2, r3, #22
1802 ; CHECK-LE-NEXT: itt mi
1803 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #9]
1804 ; CHECK-LE-NEXT: vmovmi.8 q0[9], r2
1805 ; CHECK-LE-NEXT: lsls r2, r3, #21
1806 ; CHECK-LE-NEXT: itt mi
1807 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #10]
1808 ; CHECK-LE-NEXT: vmovmi.8 q0[10], r2
1809 ; CHECK-LE-NEXT: lsls r2, r3, #20
1810 ; CHECK-LE-NEXT: itt mi
1811 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #11]
1812 ; CHECK-LE-NEXT: vmovmi.8 q0[11], r2
1813 ; CHECK-LE-NEXT: lsls r2, r3, #19
1814 ; CHECK-LE-NEXT: itt mi
1815 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #12]
1816 ; CHECK-LE-NEXT: vmovmi.8 q0[12], r2
1817 ; CHECK-LE-NEXT: lsls r2, r3, #18
1818 ; CHECK-LE-NEXT: itt mi
1819 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #13]
1820 ; CHECK-LE-NEXT: vmovmi.8 q0[13], r2
1821 ; CHECK-LE-NEXT: lsls r2, r3, #17
1822 ; CHECK-LE-NEXT: itt mi
1823 ; CHECK-LE-NEXT: ldrbmi r2, [r0, #14]
1824 ; CHECK-LE-NEXT: vmovmi.8 q0[14], r2
1825 ; CHECK-LE-NEXT: lsls r2, r3, #16
1826 ; CHECK-LE-NEXT: itt mi
1827 ; CHECK-LE-NEXT: ldrbmi r0, [r0, #15]
1828 ; CHECK-LE-NEXT: vmovmi.8 q0[15], r0
4221829 ; CHECK-LE-NEXT: vstrw.32 q0, [r1]
423 ; CHECK-LE-NEXT: adds r0, #4
424 ; CHECK-LE-NEXT: bx lr
1830 ; CHECK-LE-NEXT: mov r0, r12
1831 ; CHECK-LE-NEXT: mov sp, r4
1832 ; CHECK-LE-NEXT: pop {r4, r6, r7, pc}
4251833 ;
4261834 ; CHECK-BE-LABEL: masked_v16i8_postinc:
4271835 ; CHECK-BE: @ %bb.0: @ %entry
1836 ; CHECK-BE-NEXT: .save {r4, r6, r7, lr}
1837 ; CHECK-BE-NEXT: push {r4, r6, r7, lr}
1838 ; CHECK-BE-NEXT: .setfp r7, sp, #8
1839 ; CHECK-BE-NEXT: add r7, sp, #8
1840 ; CHECK-BE-NEXT: .pad #16
1841 ; CHECK-BE-NEXT: sub sp, #16
1842 ; CHECK-BE-NEXT: mov r4, sp
1843 ; CHECK-BE-NEXT: bfc r4, #0, #4
1844 ; CHECK-BE-NEXT: mov sp, r4
4281845 ; CHECK-BE-NEXT: vrev64.8 q1, q0
1846 ; CHECK-BE-NEXT: mov r2, sp
4291847 ; CHECK-BE-NEXT: vcmp.s8 gt, q1, zr
430 ; CHECK-BE-NEXT: vpst
431 ; CHECK-BE-NEXT: vldrbt.u8 q0, [r0]
1848 ; CHECK-BE-NEXT: @ implicit-def: $q0
1849 ; CHECK-BE-NEXT: sub.w r4, r7, #8
1850 ; CHECK-BE-NEXT: vstr p0, [r2]
1851 ; CHECK-BE-NEXT: add.w r12, r0, #4
1852 ; CHECK-BE-NEXT: ldrh.w r3, [sp]
1853 ; CHECK-BE-NEXT: lsls r2, r3, #31
1854 ; CHECK-BE-NEXT: itt ne
1855 ; CHECK-BE-NEXT: ldrbne r2, [r0]
1856 ; CHECK-BE-NEXT: vmovne.8 q0[0], r2
1857 ; CHECK-BE-NEXT: lsls r2, r3, #30
1858 ; CHECK-BE-NEXT: itt mi
1859 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #1]
1860 ; CHECK-BE-NEXT: vmovmi.8 q0[1], r2
1861 ; CHECK-BE-NEXT: lsls r2, r3, #29
1862 ; CHECK-BE-NEXT: itt mi
1863 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #2]
1864 ; CHECK-BE-NEXT: vmovmi.8 q0[2], r2
1865 ; CHECK-BE-NEXT: lsls r2, r3, #28
1866 ; CHECK-BE-NEXT: itt mi
1867 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #3]
1868 ; CHECK-BE-NEXT: vmovmi.8 q0[3], r2
1869 ; CHECK-BE-NEXT: lsls r2, r3, #27
1870 ; CHECK-BE-NEXT: itt mi
1871 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #4]
1872 ; CHECK-BE-NEXT: vmovmi.8 q0[4], r2
1873 ; CHECK-BE-NEXT: lsls r2, r3, #26
1874 ; CHECK-BE-NEXT: itt mi
1875 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #5]
1876 ; CHECK-BE-NEXT: vmovmi.8 q0[5], r2
1877 ; CHECK-BE-NEXT: lsls r2, r3, #25
1878 ; CHECK-BE-NEXT: itt mi
1879 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #6]
1880 ; CHECK-BE-NEXT: vmovmi.8 q0[6], r2
1881 ; CHECK-BE-NEXT: lsls r2, r3, #24
1882 ; CHECK-BE-NEXT: itt mi
1883 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #7]
1884 ; CHECK-BE-NEXT: vmovmi.8 q0[7], r2
1885 ; CHECK-BE-NEXT: lsls r2, r3, #23
1886 ; CHECK-BE-NEXT: itt mi
1887 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #8]
1888 ; CHECK-BE-NEXT: vmovmi.8 q0[8], r2
1889 ; CHECK-BE-NEXT: lsls r2, r3, #22
1890 ; CHECK-BE-NEXT: itt mi
1891 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #9]
1892 ; CHECK-BE-NEXT: vmovmi.8 q0[9], r2
1893 ; CHECK-BE-NEXT: lsls r2, r3, #21
1894 ; CHECK-BE-NEXT: itt mi
1895 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #10]
1896 ; CHECK-BE-NEXT: vmovmi.8 q0[10], r2
1897 ; CHECK-BE-NEXT: lsls r2, r3, #20
1898 ; CHECK-BE-NEXT: itt mi
1899 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #11]
1900 ; CHECK-BE-NEXT: vmovmi.8 q0[11], r2
1901 ; CHECK-BE-NEXT: lsls r2, r3, #19
1902 ; CHECK-BE-NEXT: itt mi
1903 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #12]
1904 ; CHECK-BE-NEXT: vmovmi.8 q0[12], r2
1905 ; CHECK-BE-NEXT: lsls r2, r3, #18
1906 ; CHECK-BE-NEXT: itt mi
1907 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #13]
1908 ; CHECK-BE-NEXT: vmovmi.8 q0[13], r2
1909 ; CHECK-BE-NEXT: lsls r2, r3, #17
1910 ; CHECK-BE-NEXT: itt mi
1911 ; CHECK-BE-NEXT: ldrbmi r2, [r0, #14]
1912 ; CHECK-BE-NEXT: vmovmi.8 q0[14], r2
1913 ; CHECK-BE-NEXT: lsls r2, r3, #16
1914 ; CHECK-BE-NEXT: itt mi
1915 ; CHECK-BE-NEXT: ldrbmi r0, [r0, #15]
1916 ; CHECK-BE-NEXT: vmovmi.8 q0[15], r0
4321917 ; CHECK-BE-NEXT: vstrb.8 q0, [r1]
433 ; CHECK-BE-NEXT: adds r0, #4
434 ; CHECK-BE-NEXT: bx lr
1918 ; CHECK-BE-NEXT: mov r0, r12
1919 ; CHECK-BE-NEXT: mov sp, r4
1920 ; CHECK-BE-NEXT: pop {r4, r6, r7, pc}
4351921 entry:
4361922 %z = getelementptr inbounds i8, i8* %x, i32 4
4371923 %0 = bitcast i8* %x to <16 x i8>*
4461932 define arm_aapcs_vfpcc <4 x float> @masked_v4f32_align4_zero(<4 x float> *%dest, <4 x i32> %a) {
4471933 ; CHECK-LE-LABEL: masked_v4f32_align4_zero:
4481934 ; CHECK-LE: @ %bb.0: @ %entry
449 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
1935 ; CHECK-LE-NEXT: .pad #4
1936 ; CHECK-LE-NEXT: sub sp, #4
1937 ; CHECK-LE-NEXT: mov r1, sp
4501938 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
451 ; CHECK-LE-NEXT: vpst
452 ; CHECK-LE-NEXT: vldrwt.u32 q0, [r0]
453 ; CHECK-LE-NEXT: vpsel q0, q0, q1
1939 ; CHECK-LE-NEXT: vstr p0, [r1]
1940 ; CHECK-LE-NEXT: ldrb.w r1, [sp]
1941 ; CHECK-LE-NEXT: lsls r2, r1, #31
1942 ; CHECK-LE-NEXT: beq .LBB17_2
1943 ; CHECK-LE-NEXT: @ %bb.1: @ %cond.load
1944 ; CHECK-LE-NEXT: vldr s0, .LCPI17_0
1945 ; CHECK-LE-NEXT: vldr s4, [r0]
1946 ; CHECK-LE-NEXT: vmov r2, s0
1947 ; CHECK-LE-NEXT: vdup.32 q0, r2
1948 ; CHECK-LE-NEXT: vmov.f32 s0, s4
1949 ; CHECK-LE-NEXT: b .LBB17_3
1950 ; CHECK-LE-NEXT: .LBB17_2:
1951 ; CHECK-LE-NEXT: vmov.i32 q0, #0x0
1952 ; CHECK-LE-NEXT: .LBB17_3: @ %else
1953 ; CHECK-LE-NEXT: lsls r2, r1, #30
1954 ; CHECK-LE-NEXT: it mi
1955 ; CHECK-LE-NEXT: vldrmi s1, [r0, #4]
1956 ; CHECK-LE-NEXT: lsls r2, r1, #29
1957 ; CHECK-LE-NEXT: it mi
1958 ; CHECK-LE-NEXT: vldrmi s2, [r0, #8]
1959 ; CHECK-LE-NEXT: lsls r1, r1, #28
1960 ; CHECK-LE-NEXT: it mi
1961 ; CHECK-LE-NEXT: vldrmi s3, [r0, #12]
1962 ; CHECK-LE-NEXT: add sp, #4
4541963 ; CHECK-LE-NEXT: bx lr
1964 ; CHECK-LE-NEXT: .p2align 2
1965 ; CHECK-LE-NEXT: @ %bb.4:
1966 ; CHECK-LE-NEXT: .LCPI17_0:
1967 ; CHECK-LE-NEXT: .long 0 @ float 0
4551968 ;
4561969 ; CHECK-BE-LABEL: masked_v4f32_align4_zero:
4571970 ; CHECK-BE: @ %bb.0: @ %entry
458 ; CHECK-BE-NEXT: vrev64.32 q2, q0
1971 ; CHECK-BE-NEXT: .pad #4
1972 ; CHECK-BE-NEXT: sub sp, #4
1973 ; CHECK-BE-NEXT: vrev64.32 q1, q0
1974 ; CHECK-BE-NEXT: mov r1, sp
1975 ; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr
1976 ; CHECK-BE-NEXT: vstr p0, [r1]
1977 ; CHECK-BE-NEXT: ldrb.w r1, [sp]
1978 ; CHECK-BE-NEXT: lsls r2, r1, #31
1979 ; CHECK-BE-NEXT: beq .LBB17_2
1980 ; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
1981 ; CHECK-BE-NEXT: vldr s0, .LCPI17_0
1982 ; CHECK-BE-NEXT: vldr s2, [r0]
1983 ; CHECK-BE-NEXT: vmov r2, s0
1984 ; CHECK-BE-NEXT: vdup.32 q1, r2
1985 ; CHECK-BE-NEXT: vmov.f32 s4, s2
1986 ; CHECK-BE-NEXT: b .LBB17_3
1987 ; CHECK-BE-NEXT: .LBB17_2:
4591988 ; CHECK-BE-NEXT: vmov.i32 q1, #0x0
460 ; CHECK-BE-NEXT: vcmp.s32 gt, q2, zr
461 ; CHECK-BE-NEXT: vpst
462 ; CHECK-BE-NEXT: vldrwt.u32 q0, [r0]
463 ; CHECK-BE-NEXT: vpsel q1, q0, q1
1989 ; CHECK-BE-NEXT: .LBB17_3: @ %else
1990 ; CHECK-BE-NEXT: lsls r2, r1, #30
1991 ; CHECK-BE-NEXT: it mi
1992 ; CHECK-BE-NEXT: vldrmi s5, [r0, #4]
1993 ; CHECK-BE-NEXT: lsls r2, r1, #29
1994 ; CHECK-BE-NEXT: it mi
1995 ; CHECK-BE-NEXT: vldrmi s6, [r0, #8]
1996 ; CHECK-BE-NEXT: lsls r1, r1, #28
1997 ; CHECK-BE-NEXT: it mi
1998 ; CHECK-BE-NEXT: vldrmi s7, [r0, #12]
4641999 ; CHECK-BE-NEXT: vrev64.32 q0, q1
2000 ; CHECK-BE-NEXT: add sp, #4
4652001 ; CHECK-BE-NEXT: bx lr
2002 ; CHECK-BE-NEXT: .p2align 2
2003 ; CHECK-BE-NEXT: @ %bb.4:
2004 ; CHECK-BE-NEXT: .LCPI17_0:
2005 ; CHECK-BE-NEXT: .long 0 @ float 0
4662006 entry:
4672007 %c = icmp sgt <4 x i32> %a, zeroinitializer
4682008 %l = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %dest, i32 4, <4 x i1> %c, <4 x float> zeroinitializer)
4722012 define arm_aapcs_vfpcc <4 x float> @masked_v4f32_align4_undef(<4 x float> *%dest, <4 x i32> %a) {
4732013 ; CHECK-LE-LABEL: masked_v4f32_align4_undef:
4742014 ; CHECK-LE: @ %bb.0: @ %entry
2015 ; CHECK-LE-NEXT: .pad #4
2016 ; CHECK-LE-NEXT: sub sp, #4
4752017 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
476 ; CHECK-LE-NEXT: vpst
477 ; CHECK-LE-NEXT: vldrwt.u32 q0, [r0]
2018 ; CHECK-LE-NEXT: mov r1, sp
2019 ; CHECK-LE-NEXT: vstr p0, [r1]
2020 ; CHECK-LE-NEXT: @ implicit-def: $q0
2021 ; CHECK-LE-NEXT: ldrb.w r1, [sp]
2022 ; CHECK-LE-NEXT: lsls r2, r1, #31
2023 ; CHECK-LE-NEXT: it ne
2024 ; CHECK-LE-NEXT: vldrne s0, [r0]
2025 ; CHECK-LE-NEXT: lsls r2, r1, #30
2026 ; CHECK-LE-NEXT: it mi
2027 ; CHECK-LE-NEXT: vldrmi s1, [r0, #4]
2028 ; CHECK-LE-NEXT: lsls r2, r1, #29
2029 ; CHECK-LE-NEXT: it mi
2030 ; CHECK-LE-NEXT: vldrmi s2, [r0, #8]
2031 ; CHECK-LE-NEXT: lsls r1, r1, #28
2032 ; CHECK-LE-NEXT: it mi
2033 ; CHECK-LE-NEXT: vldrmi s3, [r0, #12]
2034 ; CHECK-LE-NEXT: add sp, #4
4782035 ; CHECK-LE-NEXT: bx lr
4792036 ;
4802037 ; CHECK-BE-LABEL: masked_v4f32_align4_undef:
4812038 ; CHECK-BE: @ %bb.0: @ %entry
2039 ; CHECK-BE-NEXT: .pad #4
2040 ; CHECK-BE-NEXT: sub sp, #4
4822041 ; CHECK-BE-NEXT: vrev64.32 q1, q0
2042 ; CHECK-BE-NEXT: mov r1, sp
4832043 ; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr
484 ; CHECK-BE-NEXT: vpst
485 ; CHECK-BE-NEXT: vldrwt.u32 q1, [r0]
2044 ; CHECK-BE-NEXT: @ implicit-def: $q1
2045 ; CHECK-BE-NEXT: vstr p0, [r1]
2046 ; CHECK-BE-NEXT: ldrb.w r1, [sp]
2047 ; CHECK-BE-NEXT: lsls r2, r1, #31
2048 ; CHECK-BE-NEXT: it ne
2049 ; CHECK-BE-NEXT: vldrne s4, [r0]
2050 ; CHECK-BE-NEXT: lsls r2, r1, #30
2051 ; CHECK-BE-NEXT: it mi
2052 ; CHECK-BE-NEXT: vldrmi s5, [r0, #4]
2053 ; CHECK-BE-NEXT: lsls r2, r1, #29
2054 ; CHECK-BE-NEXT: it mi
2055 ; CHECK-BE-NEXT: vldrmi s6, [r0, #8]
2056 ; CHECK-BE-NEXT: lsls r1, r1, #28
2057 ; CHECK-BE-NEXT: it mi
2058 ; CHECK-BE-NEXT: vldrmi s7, [r0, #12]
4862059 ; CHECK-BE-NEXT: vrev64.32 q0, q1
2060 ; CHECK-BE-NEXT: add sp, #4
4872061 ; CHECK-BE-NEXT: bx lr
4882062 entry:
4892063 %c = icmp sgt <4 x i32> %a, zeroinitializer
4942068 define arm_aapcs_vfpcc <4 x float> @masked_v4f32_align1_undef(<4 x float> *%dest, <4 x i32> %a) {
4952069 ; CHECK-LE-LABEL: masked_v4f32_align1_undef:
4962070 ; CHECK-LE: @ %bb.0: @ %entry
2071 ; CHECK-LE-NEXT: .pad #4
2072 ; CHECK-LE-NEXT: sub sp, #4
4972073 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
498 ; CHECK-LE-NEXT: vpst
499 ; CHECK-LE-NEXT: vldrbt.u8 q0, [r0]
2074 ; CHECK-LE-NEXT: mov r1, sp
2075 ; CHECK-LE-NEXT: vstr p0, [r1]
2076 ; CHECK-LE-NEXT: @ implicit-def: $q0
2077 ; CHECK-LE-NEXT: ldrb.w r1, [sp]
2078 ; CHECK-LE-NEXT: lsls r2, r1, #31
2079 ; CHECK-LE-NEXT: itt ne
2080 ; CHECK-LE-NEXT: ldrne r2, [r0]
2081 ; CHECK-LE-NEXT: vmovne s0, r2
2082 ; CHECK-LE-NEXT: lsls r2, r1, #30
2083 ; CHECK-LE-NEXT: itt mi
2084 ; CHECK-LE-NEXT: ldrmi r2, [r0, #4]
2085 ; CHECK-LE-NEXT: vmovmi s1, r2
2086 ; CHECK-LE-NEXT: lsls r2, r1, #29
2087 ; CHECK-LE-NEXT: itt mi
2088 ; CHECK-LE-NEXT: ldrmi r2, [r0, #8]
2089 ; CHECK-LE-NEXT: vmovmi s2, r2
2090 ; CHECK-LE-NEXT: lsls r1, r1, #28
2091 ; CHECK-LE-NEXT: itt mi
2092 ; CHECK-LE-NEXT: ldrmi r0, [r0, #12]
2093 ; CHECK-LE-NEXT: vmovmi s3, r0
2094 ; CHECK-LE-NEXT: add sp, #4
5002095 ; CHECK-LE-NEXT: bx lr
5012096 ;
5022097 ; CHECK-BE-LABEL: masked_v4f32_align1_undef:
5032098 ; CHECK-BE: @ %bb.0: @ %entry
2099 ; CHECK-BE-NEXT: .pad #4
2100 ; CHECK-BE-NEXT: sub sp, #4
5042101 ; CHECK-BE-NEXT: vrev64.32 q1, q0
2102 ; CHECK-BE-NEXT: mov r1, sp
5052103 ; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr
506 ; CHECK-BE-NEXT: vpst
507 ; CHECK-BE-NEXT: vldrbt.u8 q0, [r0]
508 ; CHECK-BE-NEXT: vrev32.8 q1, q0
2104 ; CHECK-BE-NEXT: @ implicit-def: $q1
2105 ; CHECK-BE-NEXT: vstr p0, [r1]
2106 ; CHECK-BE-NEXT: ldrb.w r1, [sp]
2107 ; CHECK-BE-NEXT: lsls r2, r1, #31
2108 ; CHECK-BE-NEXT: itt ne
2109 ; CHECK-BE-NEXT: ldrne r2, [r0]
2110 ; CHECK-BE-NEXT: vmovne s4, r2
2111 ; CHECK-BE-NEXT: lsls r2, r1, #30
2112 ; CHECK-BE-NEXT: itt mi
2113 ; CHECK-BE-NEXT: ldrmi r2, [r0, #4]
2114 ; CHECK-BE-NEXT: vmovmi s5, r2
2115 ; CHECK-BE-NEXT: lsls r2, r1, #29
2116 ; CHECK-BE-NEXT: itt mi
2117 ; CHECK-BE-NEXT: ldrmi r2, [r0, #8]
2118 ; CHECK-BE-NEXT: vmovmi s6, r2
2119 ; CHECK-BE-NEXT: lsls r1, r1, #28
2120 ; CHECK-BE-NEXT: itt mi
2121 ; CHECK-BE-NEXT: ldrmi r0, [r0, #12]
2122 ; CHECK-BE-NEXT: vmovmi s7, r0
5092123 ; CHECK-BE-NEXT: vrev64.32 q0, q1
2124 ; CHECK-BE-NEXT: add sp, #4
5102125 ; CHECK-BE-NEXT: bx lr
5112126 entry:
5122127 %c = icmp sgt <4 x i32> %a, zeroinitializer
5172132 define arm_aapcs_vfpcc <4 x float> @masked_v4f32_align4_other(<4 x float> *%dest, <4 x i32> %a, <4 x float> %b) {
5182133 ; CHECK-LE-LABEL: masked_v4f32_align4_other:
5192134 ; CHECK-LE: @ %bb.0: @ %entry
2135 ; CHECK-LE-NEXT: .pad #4
2136 ; CHECK-LE-NEXT: sub sp, #4
2137 ; CHECK-LE-NEXT: mov r1, sp
5202138 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
521 ; CHECK-LE-NEXT: vpst
522 ; CHECK-LE-NEXT: vldrwt.u32 q0, [r0]
523 ; CHECK-LE-NEXT: vpsel q0, q0, q1
2139 ; CHECK-LE-NEXT: vstr p0, [r1]
2140 ; CHECK-LE-NEXT: ldrb.w r1, [sp]
2141 ; CHECK-LE-NEXT: lsls r2, r1, #31
2142 ; CHECK-LE-NEXT: it ne
2143 ; CHECK-LE-NEXT: vldrne s4, [r0]
2144 ; CHECK-LE-NEXT: lsls r2, r1, #30
2145 ; CHECK-LE-NEXT: it mi
2146 ; CHECK-LE-NEXT: vldrmi s5, [r0, #4]
2147 ; CHECK-LE-NEXT: lsls r2, r1, #29
2148 ; CHECK-LE-NEXT: it mi
2149 ; CHECK-LE-NEXT: vldrmi s6, [r0, #8]
2150 ; CHECK-LE-NEXT: lsls r1, r1, #28
2151 ; CHECK-LE-NEXT: it mi
2152 ; CHECK-LE-NEXT: vldrmi s7, [r0, #12]
2153 ; CHECK-LE-NEXT: vmov q0, q1
2154 ; CHECK-LE-NEXT: add sp, #4
5242155 ; CHECK-LE-NEXT: bx lr
5252156 ;
5262157 ; CHECK-BE-LABEL: masked_v4f32_align4_other:
5272158 ; CHECK-BE: @ %bb.0: @ %entry
2159 ; CHECK-BE-NEXT: .pad #4
2160 ; CHECK-BE-NEXT: sub sp, #4
2161 ; CHECK-BE-NEXT: vrev64.32 q2, q0
2162 ; CHECK-BE-NEXT: mov r1, sp
2163 ; CHECK-BE-NEXT: vcmp.s32 gt, q2, zr
5282164 ; CHECK-BE-NEXT: vrev64.32 q2, q1
529 ; CHECK-BE-NEXT: vrev64.32 q1, q0
530 ; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr
531 ; CHECK-BE-NEXT: vpst
532 ; CHECK-BE-NEXT: vldrwt.u32 q0, [r0]
533 ; CHECK-BE-NEXT: vpsel q1, q0, q2
534 ; CHECK-BE-NEXT: vrev64.32 q0, q1
2165 ; CHECK-BE-NEXT: vstr p0, [r1]
2166 ; CHECK-BE-NEXT: ldrb.w r1, [sp]
2167 ; CHECK-BE-NEXT: lsls r2, r1, #31
2168 ; CHECK-BE-NEXT: it ne
2169 ; CHECK-BE-NEXT: vldrne s8, [r0]
2170 ; CHECK-BE-NEXT: lsls r2, r1, #30
2171 ; CHECK-BE-NEXT: it mi
2172 ; CHECK-BE-NEXT: vldrmi s9, [r0, #4]
2173 ; CHECK-BE-NEXT: lsls r2, r1, #29
2174 ; CHECK-BE-NEXT: it mi
2175 ; CHECK-BE-NEXT: vldrmi s10, [r0, #8]
2176 ; CHECK-BE-NEXT: lsls r1, r1, #28
2177 ; CHECK-BE-NEXT: it mi
2178 ; CHECK-BE-NEXT: vldrmi s11, [r0, #12]
2179 ; CHECK-BE-NEXT: vrev64.32 q0, q2
2180 ; CHECK-BE-NEXT: add sp, #4
5352181 ; CHECK-BE-NEXT: bx lr
5362182 entry:
5372183 %c = icmp sgt <4 x i32> %a, zeroinitializer
5422188 define arm_aapcs_vfpcc i8* @masked_v4f32_preinc(i8* %x, i8* %y, <4 x i32> %a) {
5432189 ; CHECK-LE-LABEL: masked_v4f32_preinc:
5442190 ; CHECK-LE: @ %bb.0: @ %entry
2191 ; CHECK-LE-NEXT: .pad #4
2192 ; CHECK-LE-NEXT: sub sp, #4
5452193 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
546 ; CHECK-LE-NEXT: vpst
547 ; CHECK-LE-NEXT: vldrwt.u32 q0, [r0, #4]
2194 ; CHECK-LE-NEXT: mov r2, sp
2195 ; CHECK-LE-NEXT: vstr p0, [r2]
2196 ; CHECK-LE-NEXT: @ implicit-def: $q0
2197 ; CHECK-LE-NEXT: adds r0, #4
2198 ; CHECK-LE-NEXT: ldrb.w r2, [sp]
2199 ; CHECK-LE-NEXT: lsls r3, r2, #31
2200 ; CHECK-LE-NEXT: it ne
2201 ; CHECK-LE-NEXT: vldrne s0, [r0]
2202 ; CHECK-LE-NEXT: lsls r3, r2, #30
2203 ; CHECK-LE-NEXT: it mi
2204 ; CHECK-LE-NEXT: vldrmi s1, [r0, #4]
2205 ; CHECK-LE-NEXT: lsls r3, r2, #29
<