llvm.org GIT mirror llvm / 6a9b29e
[msan] Fix select instrumentation. Select condition shadow was being ignored resulting in false negatives. This change OR-s sign-extended condition shadow into the result shadow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189785 91177308-0d34-0410-b5e6-96231b3b80d8 Evgeniy Stepanov 7 years ago
2 changed file(s) with 15 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
17421742
17431743 void visitSelectInst(SelectInst& I) {
17441744 IRBuilder<> IRB(&I);
1745 setShadow(&I, IRB.CreateSelect(I.getCondition(),
1746 getShadow(I.getTrueValue()), getShadow(I.getFalseValue()),
1747 "_msprop"));
1745 // a = select b, c, d
1746 // Sa = (sext Sb) | (select b, Sc, Sd)
1747 Value *S = IRB.CreateSelect(I.getCondition(), getShadow(I.getTrueValue()),
1748 getShadow(I.getFalseValue()));
1749 Value *S2 = IRB.CreateSExt(getShadow(I.getCondition()), S->getType());
1750 setShadow(&I, IRB.CreateOr(S, S2, "_msprop"));
17481751 if (MS.TrackOrigins) {
17491752 // Origins are always i32, so any vector conditions must be flattened.
17501753 // FIXME: consider tracking vector origins for app vectors?
259259
260260 ; CHECK: @Select
261261 ; CHECK: select
262 ; CHECK-NEXT: sext i1 {{.*}} to i32
263 ; CHECK-NEXT: or i32
262264 ; CHECK-NEXT: select
263265 ; CHECK: ret i32
264266
272274 %cond = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
273275 ret <8 x i16> %cond
274276 }
277
278 ; CHECK: @SelectVector
279 ; CHECK: select <8 x i1>
280 ; CHECK-NEXT: sext <8 x i1> {{.*}} to <8 x i16>
281 ; CHECK-NEXT: or <8 x i16>
282 ; CHECK-NEXT: select <8 x i1>
283 ; CHECK: ret <8 x i16>
275284
276285 ; CHECK-ORIGINS: @SelectVector
277286 ; CHECK-ORIGINS: bitcast <8 x i1> {{.*}} to i8