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Merging r260645: ------------------------------------------------------------------------ r260645 | Matthew.Arsenault | 2016-02-11 18:16:10 -0800 (Thu, 11 Feb 2016) | 2 lines AMDGPU: Initialize SILowerControlFlow ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@271643 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 years ago
3 changed file(s) with 46 addition(s) and 33 deletion(s). Raw diff Collapse all Expand all
4343 FunctionPass *createSILowerI1CopiesPass();
4444 FunctionPass *createSIShrinkInstructionsPass();
4545 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm);
46 FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);
46 FunctionPass *createSILowerControlFlowPass();
4747 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
4848 FunctionPass *createSIFixSGPRCopiesPass();
4949 FunctionPass *createSIFixSGPRLiveRangesPass();
6767
6868 void initializeSILoadStoreOptimizerPass(PassRegistry &);
6969 extern char &SILoadStoreOptimizerID;
70
71 void initializeSILowerControlFlowPass(PassRegistry &);
72 extern char &SILowerControlFlowPassID;
73
7074
7175 // Passes common to R600 and SI
7276 FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr);
5454 initializeAMDGPUPromoteAllocaPass(*PR);
5555 initializeSIAnnotateControlFlowPass(*PR);
5656 initializeSIInsertWaitsPass(*PR);
57 initializeSILowerControlFlowPass(*PR);
5758 }
5859
5960 static std::unique_ptr createTLOF(const Triple &TT) {
360361
361362 void GCNPassConfig::addPreEmitPass() {
362363 addPass(createSIInsertWaitsPass(), false);
363 addPass(createSILowerControlFlowPass(*TM), false);
364 addPass(createSILowerControlFlowPass(), false);
364365 }
365366
366367 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
6060
6161 using namespace llvm;
6262
63 #define DEBUG_TYPE "si-lower-control-flow"
64
6365 namespace {
6466
65 class SILowerControlFlowPass : public MachineFunctionPass {
66
67 class SILowerControlFlow : public MachineFunctionPass {
6768 private:
6869 static const unsigned SkipThreshold = 12;
6970
70 static char ID;
7171 const SIRegisterInfo *TRI;
7272 const SIInstrInfo *TII;
7373
9393 void IndirectDst(MachineInstr &MI);
9494
9595 public:
96 SILowerControlFlowPass(TargetMachine &tm) :
96 static char ID;
97
98 SILowerControlFlow() :
9799 MachineFunctionPass(ID), TRI(nullptr), TII(nullptr) { }
98100
99101 bool runOnMachineFunction(MachineFunction &MF) override;
100102
101103 const char *getPassName() const override {
102 return "SI Lower control flow instructions";
104 return "SI Lower control flow pseudo instructions";
103105 }
104106
105107 void getAnalysisUsage(AnalysisUsage &AU) const override {
110112
111113 } // End anonymous namespace
112114
113 char SILowerControlFlowPass::ID = 0;
114
115 FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
116 return new SILowerControlFlowPass(tm);
117 }
118
119 bool SILowerControlFlowPass::shouldSkip(MachineBasicBlock *From,
120 MachineBasicBlock *To) {
115 char SILowerControlFlow::ID = 0;
116
117 INITIALIZE_PASS(SILowerControlFlow, DEBUG_TYPE,
118 "SI lower control flow", false, false)
119
120 char &llvm::SILowerControlFlowPassID = SILowerControlFlow::ID;
121
122
123 FunctionPass *llvm::createSILowerControlFlowPass() {
124 return new SILowerControlFlow();
125 }
126
127 bool SILowerControlFlow::shouldSkip(MachineBasicBlock *From,
128 MachineBasicBlock *To) {
121129
122130 unsigned NumInstr = 0;
123131
136144 return false;
137145 }
138146
139 void SILowerControlFlowPass::Skip(MachineInstr &From, MachineOperand &To) {
147 void SILowerControlFlow::Skip(MachineInstr &From, MachineOperand &To) {
140148
141149 if (!shouldSkip(*From.getParent()->succ_begin(), To.getMBB()))
142150 return;
146154 .addOperand(To);
147155 }
148156
149 void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
157 void SILowerControlFlow::SkipIfDead(MachineInstr &MI) {
150158
151159 MachineBasicBlock &MBB = *MI.getParent();
152160 DebugLoc DL = MI.getDebugLoc();
179187 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
180188 }
181189
182 void SILowerControlFlowPass::If(MachineInstr &MI) {
190 void SILowerControlFlow::If(MachineInstr &MI) {
183191 MachineBasicBlock &MBB = *MI.getParent();
184192 DebugLoc DL = MI.getDebugLoc();
185193 unsigned Reg = MI.getOperand(0).getReg();
197205 MI.eraseFromParent();
198206 }
199207
200 void SILowerControlFlowPass::Else(MachineInstr &MI) {
208 void SILowerControlFlow::Else(MachineInstr &MI) {
201209 MachineBasicBlock &MBB = *MI.getParent();
202210 DebugLoc DL = MI.getDebugLoc();
203211 unsigned Dst = MI.getOperand(0).getReg();
216224 MI.eraseFromParent();
217225 }
218226
219 void SILowerControlFlowPass::Break(MachineInstr &MI) {
227 void SILowerControlFlow::Break(MachineInstr &MI) {
220228 MachineBasicBlock &MBB = *MI.getParent();
221229 DebugLoc DL = MI.getDebugLoc();
222230
230238 MI.eraseFromParent();
231239 }
232240
233 void SILowerControlFlowPass::IfBreak(MachineInstr &MI) {
241 void SILowerControlFlow::IfBreak(MachineInstr &MI) {
234242 MachineBasicBlock &MBB = *MI.getParent();
235243 DebugLoc DL = MI.getDebugLoc();
236244
245253 MI.eraseFromParent();
246254 }
247255
248 void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) {
256 void SILowerControlFlow::ElseBreak(MachineInstr &MI) {
249257 MachineBasicBlock &MBB = *MI.getParent();
250258 DebugLoc DL = MI.getDebugLoc();
251259
260268 MI.eraseFromParent();
261269 }
262270
263 void SILowerControlFlowPass::Loop(MachineInstr &MI) {
271 void SILowerControlFlow::Loop(MachineInstr &MI) {
264272 MachineBasicBlock &MBB = *MI.getParent();
265273 DebugLoc DL = MI.getDebugLoc();
266274 unsigned Src = MI.getOperand(0).getReg();
275283 MI.eraseFromParent();
276284 }
277285
278 void SILowerControlFlowPass::EndCf(MachineInstr &MI) {
286 void SILowerControlFlow::EndCf(MachineInstr &MI) {
279287 MachineBasicBlock &MBB = *MI.getParent();
280288 DebugLoc DL = MI.getDebugLoc();
281289 unsigned Reg = MI.getOperand(0).getReg();
288296 MI.eraseFromParent();
289297 }
290298
291 void SILowerControlFlowPass::Branch(MachineInstr &MI) {
299 void SILowerControlFlow::Branch(MachineInstr &MI) {
292300 if (MI.getOperand(0).getMBB() == MI.getParent()->getNextNode())
293301 MI.eraseFromParent();
294302
295303 // If these aren't equal, this is probably an infinite loop.
296304 }
297305
298 void SILowerControlFlowPass::Kill(MachineInstr &MI) {
306 void SILowerControlFlow::Kill(MachineInstr &MI) {
299307 MachineBasicBlock &MBB = *MI.getParent();
300308 DebugLoc DL = MI.getDebugLoc();
301309 const MachineOperand &Op = MI.getOperand(0);
324332 MI.eraseFromParent();
325333 }
326334
327 void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel, int Offset) {
335 void SILowerControlFlow::LoadM0(MachineInstr &MI, MachineInstr *MovRel, int Offset) {
328336
329337 MachineBasicBlock &MBB = *MI.getParent();
330338 DebugLoc DL = MI.getDebugLoc();
402410 // indirect Index. e.g. v0 = v[VecReg + Offset]
403411 // As an output, this is a constant value that needs
404412 // to be added to the value stored in M0.
405 void SILowerControlFlowPass::computeIndirectRegAndOffset(unsigned VecReg,
406 unsigned &Reg,
407 int &Offset) {
413 void SILowerControlFlow::computeIndirectRegAndOffset(unsigned VecReg,
414 unsigned &Reg,
415 int &Offset) {
408416 unsigned SubReg = TRI->getSubReg(VecReg, AMDGPU::sub0);
409417 if (!SubReg)
410418 SubReg = VecReg;
422430 Reg = RC->getRegister(RegIdx);
423431 }
424432
425 void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) {
433 void SILowerControlFlow::IndirectSrc(MachineInstr &MI) {
426434
427435 MachineBasicBlock &MBB = *MI.getParent();
428436 DebugLoc DL = MI.getDebugLoc();
442450 LoadM0(MI, MovRel, Off);
443451 }
444452
445 void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
453 void SILowerControlFlow::IndirectDst(MachineInstr &MI) {
446454
447455 MachineBasicBlock &MBB = *MI.getParent();
448456 DebugLoc DL = MI.getDebugLoc();
463471 LoadM0(MI, MovRel, Off);
464472 }
465473
466 bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
474 bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
467475 TII = static_cast(MF.getSubtarget().getInstrInfo());
468476 TRI =
469477 static_cast(MF.getSubtarget().getRegisterInfo());