llvm.org GIT mirror llvm / 6a6b4d5
Revert "For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported." It doesn't build with MSVC 2012, because MSVC doesn't allow union members that have non-trivial default constructors. This change added 'SMLoc AlignmentLoc' to MemoryOp, which made MemoryOp's default ctor non-trivial. This reverts commit r205930. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205944 91177308-0d34-0410-b5e6-96231b3b80d8 Reid Kleckner 6 years ago
4 changed file(s) with 447 addition(s) and 9263 deletion(s). Raw diff Collapse all Expand all
990990 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
991991 }
992992
993 // Base class for addrmode6 with specific alignment restrictions.
994 class AddrMode6Align : Operand,
995 ComplexPattern{
996 let PrintMethod = "printAddrMode6Operand";
997 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
998 let EncoderMethod = "getAddrMode6AddressOpValue";
999 let DecoderMethod = "DecodeAddrMode6Operand";
1000 }
1001
1002 // Special version of addrmode6 to handle no allowed alignment encoding for
1003 // VLD/VST instructions and checking the alignment is not specified.
1004 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1005 let Name = "AlignedMemoryNone";
1006 let DiagnosticType = "AlignedMemoryRequiresNone";
1007 }
1008 def addrmode6alignNone : AddrMode6Align {
1009 // The alignment specifier can only be omitted.
1010 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1011 }
1012
1013 // Special version of addrmode6 to handle 16-bit alignment encoding for
1014 // VLD/VST instructions and checking the alignment value.
1015 def AddrMode6Align16AsmOperand : AsmOperandClass {
1016 let Name = "AlignedMemory16";
1017 let DiagnosticType = "AlignedMemoryRequires16";
1018 }
1019 def addrmode6align16 : AddrMode6Align {
1020 // The alignment specifier can only be 16 or omitted.
1021 let ParserMatchClass = AddrMode6Align16AsmOperand;
1022 }
1023
1024 // Special version of addrmode6 to handle 32-bit alignment encoding for
1025 // VLD/VST instructions and checking the alignment value.
1026 def AddrMode6Align32AsmOperand : AsmOperandClass {
1027 let Name = "AlignedMemory32";
1028 let DiagnosticType = "AlignedMemoryRequires32";
1029 }
1030 def addrmode6align32 : AddrMode6Align {
1031 // The alignment specifier can only be 32 or omitted.
1032 let ParserMatchClass = AddrMode6Align32AsmOperand;
1033 }
1034
1035 // Special version of addrmode6 to handle 64-bit alignment encoding for
1036 // VLD/VST instructions and checking the alignment value.
1037 def AddrMode6Align64AsmOperand : AsmOperandClass {
1038 let Name = "AlignedMemory64";
1039 let DiagnosticType = "AlignedMemoryRequires64";
1040 }
1041 def addrmode6align64 : AddrMode6Align {
1042 // The alignment specifier can only be 64 or omitted.
1043 let ParserMatchClass = AddrMode6Align64AsmOperand;
1044 }
1045
1046 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1047 // for VLD/VST instructions and checking the alignment value.
1048 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1049 let Name = "AlignedMemory64or128";
1050 let DiagnosticType = "AlignedMemoryRequires64or128";
1051 }
1052 def addrmode6align64or128 : AddrMode6Align {
1053 // The alignment specifier can only be 64, 128 or omitted.
1054 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1055 }
1056
1057 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1058 // encoding for VLD/VST instructions and checking the alignment value.
1059 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1060 let Name = "AlignedMemory64or128or256";
1061 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1062 }
1063 def addrmode6align64or128or256 : AddrMode6Align {
1064 // The alignment specifier can only be 64, 128, 256 or omitted.
1065 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1066 }
1067
1068993 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1069994 // instructions, specifically VLD4-dup.
1070995 def addrmode6dup : Operand,
10751000 // FIXME: This is close, but not quite right. The alignment specifier is
10761001 // different.
10771002 let ParserMatchClass = AddrMode6AsmOperand;
1078 }
1079
1080 // Base class for addrmode6dup with specific alignment restrictions.
1081 class AddrMode6DupAlign : Operand,
1082 ComplexPattern{
1083 let PrintMethod = "printAddrMode6Operand";
1084 let MIOperandInfo = (ops GPR:$addr, i32imm);
1085 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1086 }
1087
1088 // Special version of addrmode6 to handle no allowed alignment encoding for
1089 // VLD-dup instruction and checking the alignment is not specified.
1090 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1091 let Name = "DupAlignedMemoryNone";
1092 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1093 }
1094 def addrmode6dupalignNone : AddrMode6DupAlign {
1095 // The alignment specifier can only be omitted.
1096 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1097 }
1098
1099 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1100 // instruction and checking the alignment value.
1101 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1102 let Name = "DupAlignedMemory16";
1103 let DiagnosticType = "DupAlignedMemoryRequires16";
1104 }
1105 def addrmode6dupalign16 : AddrMode6DupAlign {
1106 // The alignment specifier can only be 16 or omitted.
1107 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1108 }
1109
1110 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1111 // instruction and checking the alignment value.
1112 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1113 let Name = "DupAlignedMemory32";
1114 let DiagnosticType = "DupAlignedMemoryRequires32";
1115 }
1116 def addrmode6dupalign32 : AddrMode6DupAlign {
1117 // The alignment specifier can only be 32 or omitted.
1118 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1119 }
1120
1121 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1122 // instructions and checking the alignment value.
1123 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1124 let Name = "DupAlignedMemory64";
1125 let DiagnosticType = "DupAlignedMemoryRequires64";
1126 }
1127 def addrmode6dupalign64 : AddrMode6DupAlign {
1128 // The alignment specifier can only be 64 or omitted.
1129 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1130 }
1131
1132 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1133 // for VLD instructions and checking the alignment value.
1134 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1135 let Name = "DupAlignedMemory64or128";
1136 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1137 }
1138 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1139 // The alignment specifier can only be 64, 128 or omitted.
1140 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
11411003 }
11421004
11431005 // addrmodepc := pc + reg
616616 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
617617
618618 // VLD1 : Vector Load (multiple single elements)
619 class VLD1D op7_4, string Dt, Operand AddrMode>
619 class VLD1D op7_4, string Dt>
620620 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
621 (ins AddrMode:$Rn), IIC_VLD1,
621 (ins addrmode6:$Rn), IIC_VLD1,
622622 "vld1", Dt, "$Vd, $Rn", "", []> {
623623 let Rm = 0b1111;
624624 let Inst{4} = Rn{4};
625625 let DecoderMethod = "DecodeVLDST1Instruction";
626626 }
627 class VLD1Q op7_4, string Dt, Operand AddrMode>
627 class VLD1Q op7_4, string Dt>
628628 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
629 (ins AddrMode:$Rn), IIC_VLD1x2,
629 (ins addrmode6:$Rn), IIC_VLD1x2,
630630 "vld1", Dt, "$Vd, $Rn", "", []> {
631631 let Rm = 0b1111;
632632 let Inst{5-4} = Rn{5-4};
633633 let DecoderMethod = "DecodeVLDST1Instruction";
634634 }
635635
636 def VLD1d8 : VLD1D<{0,0,0,?}, "8", addrmode6align64>;
637 def VLD1d16 : VLD1D<{0,1,0,?}, "16", addrmode6align64>;
638 def VLD1d32 : VLD1D<{1,0,0,?}, "32", addrmode6align64>;
639 def VLD1d64 : VLD1D<{1,1,0,?}, "64", addrmode6align64>;
640
641 def VLD1q8 : VLD1Q<{0,0,?,?}, "8", addrmode6align64or128>;
642 def VLD1q16 : VLD1Q<{0,1,?,?}, "16", addrmode6align64or128>;
643 def VLD1q32 : VLD1Q<{1,0,?,?}, "32", addrmode6align64or128>;
644 def VLD1q64 : VLD1Q<{1,1,?,?}, "64", addrmode6align64or128>;
636 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
637 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
638 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
639 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
640
641 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
642 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
643 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
644 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
645645
646646 // ...with address register writeback:
647 multiclass VLD1DWB op7_4, string Dt, Operand AddrMode> {
647 multiclass VLD1DWB op7_4, string Dt> {
648648 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
649 (ins AddrMode:$Rn), IIC_VLD1u,
649 (ins addrmode6:$Rn), IIC_VLD1u,
650650 "vld1", Dt, "$Vd, $Rn!",
651651 "$Rn.addr = $wb", []> {
652652 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
654654 let DecoderMethod = "DecodeVLDST1Instruction";
655655 }
656656 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
657 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
657 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
658658 "vld1", Dt, "$Vd, $Rn, $Rm",
659659 "$Rn.addr = $wb", []> {
660660 let Inst{4} = Rn{4};
661661 let DecoderMethod = "DecodeVLDST1Instruction";
662662 }
663663 }
664 multiclass VLD1QWB op7_4, string Dt, Operand AddrMode> {
664 multiclass VLD1QWB op7_4, string Dt> {
665665 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
666 (ins AddrMode:$Rn), IIC_VLD1x2u,
666 (ins addrmode6:$Rn), IIC_VLD1x2u,
667667 "vld1", Dt, "$Vd, $Rn!",
668668 "$Rn.addr = $wb", []> {
669669 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
671671 let DecoderMethod = "DecodeVLDST1Instruction";
672672 }
673673 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
674 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
674 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
675675 "vld1", Dt, "$Vd, $Rn, $Rm",
676676 "$Rn.addr = $wb", []> {
677677 let Inst{5-4} = Rn{5-4};
679679 }
680680 }
681681
682 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8", addrmode6align64>;
683 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16", addrmode6align64>;
684 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32", addrmode6align64>;
685 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64", addrmode6align64>;
686 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8", addrmode6align64or128>;
687 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16", addrmode6align64or128>;
688 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32", addrmode6align64or128>;
689 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64", addrmode6align64or128>;
682 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
683 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
684 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
685 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
686 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
687 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
688 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
689 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
690690
691691 // ...with 3 registers
692 class VLD1D3 op7_4, string Dt, Operand AddrMode>
692 class VLD1D3 op7_4, string Dt>
693693 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
694 (ins AddrMode:$Rn), IIC_VLD1x3, "vld1", Dt,
694 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
695695 "$Vd, $Rn", "", []> {
696696 let Rm = 0b1111;
697697 let Inst{4} = Rn{4};
698698 let DecoderMethod = "DecodeVLDST1Instruction";
699699 }
700 multiclass VLD1D3WB op7_4, string Dt, Operand AddrMode> {
700 multiclass VLD1D3WB op7_4, string Dt> {
701701 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
702 (ins AddrMode:$Rn), IIC_VLD1x2u,
702 (ins addrmode6:$Rn), IIC_VLD1x2u,
703703 "vld1", Dt, "$Vd, $Rn!",
704704 "$Rn.addr = $wb", []> {
705705 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
707707 let DecoderMethod = "DecodeVLDST1Instruction";
708708 }
709709 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
710 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
710 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
711711 "vld1", Dt, "$Vd, $Rn, $Rm",
712712 "$Rn.addr = $wb", []> {
713713 let Inst{4} = Rn{4};
715715 }
716716 }
717717
718 def VLD1d8T : VLD1D3<{0,0,0,?}, "8", addrmode6align64>;
719 def VLD1d16T : VLD1D3<{0,1,0,?}, "16", addrmode6align64>;
720 def VLD1d32T : VLD1D3<{1,0,0,?}, "32", addrmode6align64>;
721 def VLD1d64T : VLD1D3<{1,1,0,?}, "64", addrmode6align64>;
722
723 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8", addrmode6align64>;
724 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16", addrmode6align64>;
725 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32", addrmode6align64>;
726 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64", addrmode6align64>;
718 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
719 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
720 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
721 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
722
723 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
724 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
725 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
726 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
727727
728728 def VLD1d64TPseudo : VLDQQPseudo;
729729 def VLD1d64TPseudoWB_fixed : VLDQQWBfixedPseudo;
730730 def VLD1d64TPseudoWB_register : VLDQQWBregisterPseudo;
731731
732732 // ...with 4 registers
733 class VLD1D4 op7_4, string Dt, Operand AddrMode>
733 class VLD1D4 op7_4, string Dt>
734734 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
735 (ins AddrMode:$Rn), IIC_VLD1x4, "vld1", Dt,
735 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
736736 "$Vd, $Rn", "", []> {
737737 let Rm = 0b1111;
738738 let Inst{5-4} = Rn{5-4};
739739 let DecoderMethod = "DecodeVLDST1Instruction";
740740 }
741 multiclass VLD1D4WB op7_4, string Dt, Operand AddrMode> {
741 multiclass VLD1D4WB op7_4, string Dt> {
742742 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
743 (ins AddrMode:$Rn), IIC_VLD1x2u,
743 (ins addrmode6:$Rn), IIC_VLD1x2u,
744744 "vld1", Dt, "$Vd, $Rn!",
745745 "$Rn.addr = $wb", []> {
746746 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
748748 let DecoderMethod = "DecodeVLDST1Instruction";
749749 }
750750 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
751 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
751 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
752752 "vld1", Dt, "$Vd, $Rn, $Rm",
753753 "$Rn.addr = $wb", []> {
754754 let Inst{5-4} = Rn{5-4};
756756 }
757757 }
758758
759 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8", addrmode6align64or128or256>;
760 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;
761 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;
762 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;
763
764 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>;
765 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;
766 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;
767 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;
759 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
760 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
761 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
762 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
763
764 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
765 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
766 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
767 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
768768
769769 def VLD1d64QPseudo : VLDQQPseudo;
770770 def VLD1d64QPseudoWB_fixed : VLDQQWBfixedPseudo;
772772
773773 // VLD2 : Vector Load (multiple 2-element structures)
774774 class VLD2 op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
775 InstrItinClass itin, Operand AddrMode>
775 InstrItinClass itin>
776776 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
777 (ins AddrMode:$Rn), itin,
777 (ins addrmode6:$Rn), itin,
778778 "vld2", Dt, "$Vd, $Rn", "", []> {
779779 let Rm = 0b1111;
780780 let Inst{5-4} = Rn{5-4};
781781 let DecoderMethod = "DecodeVLDST2Instruction";
782782 }
783783
784 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2,
785 addrmode6align64or128>;
786 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2,
787 addrmode6align64or128>;
788 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2,
789 addrmode6align64or128>;
790
791 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2,
792 addrmode6align64or128or256>;
793 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2,
794 addrmode6align64or128or256>;
795 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2,
796 addrmode6align64or128or256>;
784 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2>;
785 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2>;
786 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2>;
787
788 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
789 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
790 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
797791
798792 def VLD2q8Pseudo : VLDQQPseudo;
799793 def VLD2q16Pseudo : VLDQQPseudo;
801795
802796 // ...with address register writeback:
803797 multiclass VLD2WB op11_8, bits<4> op7_4, string Dt,
804 RegisterOperand VdTy, InstrItinClass itin, Operand AddrMode> {
798 RegisterOperand VdTy, InstrItinClass itin> {
805799 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
806 (ins AddrMode:$Rn), itin,
800 (ins addrmode6:$Rn), itin,
807801 "vld2", Dt, "$Vd, $Rn!",
808802 "$Rn.addr = $wb", []> {
809803 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
811805 let DecoderMethod = "DecodeVLDST2Instruction";
812806 }
813807 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
814 (ins AddrMode:$Rn, rGPR:$Rm), itin,
808 (ins addrmode6:$Rn, rGPR:$Rm), itin,
815809 "vld2", Dt, "$Vd, $Rn, $Rm",
816810 "$Rn.addr = $wb", []> {
817811 let Inst{5-4} = Rn{5-4};
819813 }
820814 }
821815
822 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u,
823 addrmode6align64or128>;
824 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u,
825 addrmode6align64or128>;
826 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u,
827 addrmode6align64or128>;
828
829 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u,
830 addrmode6align64or128or256>;
831 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u,
832 addrmode6align64or128or256>;
833 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u,
834 addrmode6align64or128or256>;
816 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u>;
817 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u>;
818 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u>;
819
820 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;
821 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;
822 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;
835823
836824 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo;
837825 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo;
841829 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo;
842830
843831 // ...with double-spaced registers
844 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2,
845 addrmode6align64or128>;
846 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2,
847 addrmode6align64or128>;
848 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2,
849 addrmode6align64or128>;
850 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u,
851 addrmode6align64or128>;
852 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u,
853 addrmode6align64or128>;
854 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u,
855 addrmode6align64or128>;
832 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2>;
833 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2>;
834 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2>;
835 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u>;
836 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u>;
837 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u>;
856838
857839 // VLD3 : Vector Load (multiple 3-element structures)
858840 class VLD3D op11_8, bits<4> op7_4, string Dt>
13101292 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
13111293
13121294 // VLD1DUP : Vector Load (single element to all lanes)
1313 class VLD1DUP op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1314 Operand AddrMode>
1295 class VLD1DUP op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
13151296 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1316 (ins AddrMode:$Rn),
1297 (ins addrmode6dup:$Rn),
13171298 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
13181299 [(set VecListOneDAllLanes:$Vd,
1319 (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
1300 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
13201301 let Rm = 0b1111;
13211302 let Inst{4} = Rn{4};
13221303 let DecoderMethod = "DecodeVLD1DupInstruction";
13231304 }
1324 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8,
1325 addrmode6dupalignNone>;
1326 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16,
1327 addrmode6dupalign16>;
1328 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load,
1329 addrmode6dupalign32>;
1305 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1306 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1307 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
13301308
13311309 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
13321310 (VLD1DUPd32 addrmode6:$addr)>;
13331311
1334 class VLD1QDUP op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1335 Operand AddrMode>
1312 class VLD1QDUP op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
13361313 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1337 (ins AddrMode:$Rn), IIC_VLD1dup,
1314 (ins addrmode6dup:$Rn), IIC_VLD1dup,
13381315 "vld1", Dt, "$Vd, $Rn", "",
13391316 [(set VecListDPairAllLanes:$Vd,
1340 (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
1317 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
13411318 let Rm = 0b1111;
13421319 let Inst{4} = Rn{4};
13431320 let DecoderMethod = "DecodeVLD1DupInstruction";
13441321 }
13451322
1346 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8,
1347 addrmode6dupalignNone>;
1348 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16,
1349 addrmode6dupalign16>;
1350 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load,
1351 addrmode6dupalign32>;
1323 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;
1324 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
1325 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
13521326
13531327 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
13541328 (VLD1DUPq32 addrmode6:$addr)>;
13551329
13561330 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
13571331 // ...with address register writeback:
1358 multiclass VLD1DUPWB op7_4, string Dt, Operand AddrMode> {
1332 multiclass VLD1DUPWB op7_4, string Dt> {
13591333 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
13601334 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1361 (ins AddrMode:$Rn), IIC_VLD1dupu,
1335 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
13621336 "vld1", Dt, "$Vd, $Rn!",
13631337 "$Rn.addr = $wb", []> {
13641338 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
13671341 }
13681342 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
13691343 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1370 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1344 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
13711345 "vld1", Dt, "$Vd, $Rn, $Rm",
13721346 "$Rn.addr = $wb", []> {
13731347 let Inst{4} = Rn{4};
13741348 let DecoderMethod = "DecodeVLD1DupInstruction";
13751349 }
13761350 }
1377 multiclass VLD1QDUPWB op7_4, string Dt, Operand AddrMode> {
1351 multiclass VLD1QDUPWB op7_4, string Dt> {
13781352 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
13791353 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1380 (ins AddrMode:$Rn), IIC_VLD1dupu,
1354 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
13811355 "vld1", Dt, "$Vd, $Rn!",
13821356 "$Rn.addr = $wb", []> {
13831357 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
13861360 }
13871361 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
13881362 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1389 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1363 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
13901364 "vld1", Dt, "$Vd, $Rn, $Rm",
13911365 "$Rn.addr = $wb", []> {
13921366 let Inst{4} = Rn{4};
13941368 }
13951369 }
13961370
1397 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8", addrmode6dupalignNone>;
1398 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16", addrmode6dupalign16>;
1399 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32", addrmode6dupalign32>;
1400
1401 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8", addrmode6dupalignNone>;
1402 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16", addrmode6dupalign16>;
1403 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32", addrmode6dupalign32>;
1371 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">;
1372 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">;
1373 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">;
1374
1375 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;
1376 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;
1377 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;
14041378
14051379 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1406 class VLD2DUP op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1380 class VLD2DUP op7_4, string Dt, RegisterOperand VdTy>
14071381 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1408 (ins AddrMode:$Rn), IIC_VLD2dup,
1382 (ins addrmode6dup:$Rn), IIC_VLD2dup,
14091383 "vld2", Dt, "$Vd, $Rn", "", []> {
14101384 let Rm = 0b1111;
14111385 let Inst{4} = Rn{4};
14121386 let DecoderMethod = "DecodeVLD2DupInstruction";
14131387 }
14141388
1415 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1416 addrmode6dupalign16>;
1417 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1418 addrmode6dupalign32>;
1419 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1420 addrmode6dupalign64>;
1421
1422 // HACK this one, VLD2DUPd8x2 must be changed at the same time with VLD2b8 or
1423 // "vld2.8 {d0[], d2[]}, [r4:32]" will become "vld2.8 {d0, d2}, [r4:32]".
1389 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes>;
1390 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes>;
1391 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes>;
1392
14241393 // ...with double-spaced registers
1425 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1426 addrmode6dupalign16>;
1427 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1428 addrmode6dupalign32>;
1429 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
1430 addrmode6dupalign64>;
1394 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes>;
1395 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1396 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
14311397
14321398 // ...with address register writeback:
1433 multiclass VLD2DUPWB op7_4, string Dt, RegisterOperand VdTy,
1434 Operand AddrMode> {
1399 multiclass VLD2DUPWB op7_4, string Dt, RegisterOperand VdTy> {
14351400 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
14361401 (outs VdTy:$Vd, GPR:$wb),
1437 (ins AddrMode:$Rn), IIC_VLD2dupu,
1402 (ins addrmode6dup:$Rn), IIC_VLD2dupu,
14381403 "vld2", Dt, "$Vd, $Rn!",
14391404 "$Rn.addr = $wb", []> {
14401405 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
14431408 }
14441409 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
14451410 (outs VdTy:$Vd, GPR:$wb),
1446 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1411 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu,
14471412 "vld2", Dt, "$Vd, $Rn, $Rm",
14481413 "$Rn.addr = $wb", []> {
14491414 let Inst{4} = Rn{4};
14511416 }
14521417 }
14531418
1454 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes,
1455 addrmode6dupalign16>;
1456 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes,
1457 addrmode6dupalign32>;
1458 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes,
1459 addrmode6dupalign64>;
1460
1461 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes,
1462 addrmode6dupalign16>;
1463 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1464 addrmode6dupalign32>;
1465 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
1466 addrmode6dupalign64>;
1419 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes>;
1420 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes>;
1421 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes>;
1422
1423 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes>;
1424 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1425 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
14671426
14681427 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
14691428 class VLD3DUP op7_4, string Dt>
14891448 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
14901449
14911450 // ...with address register writeback:
1492 class VLD3DUPWB op7_4, string Dt, Operand AddrMode>
1451 class VLD3DUPWB op7_4, string Dt>
14931452 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1494 (ins AddrMode:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1453 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
14951454 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
14961455 "$Rn.addr = $wb", []> {
14971456 let Inst{4} = 0;
14981457 let DecoderMethod = "DecodeVLD3DupInstruction";
14991458 }
15001459
1501 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8", addrmode6dupalign64>;
1502 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16", addrmode6dupalign64>;
1503 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32", addrmode6dupalign64>;
1504
1505 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8", addrmode6dupalign64>;
1506 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16", addrmode6dupalign64>;
1507 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32", addrmode6dupalign64>;
1460 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1461 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1462 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1463
1464 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1465 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1466 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
15081467
15091468 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo;
15101469 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo;
16001559 "$addr.addr = $wb">;
16011560
16021561 // VST1 : Vector Store (multiple single elements)
1603 class VST1D op7_4, string Dt, Operand AddrMode>
1604 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1562 class VST1D op7_4, string Dt>
1563 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
16051564 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
16061565 let Rm = 0b1111;
16071566 let Inst{4} = Rn{4};
16081567 let DecoderMethod = "DecodeVLDST1Instruction";
16091568 }
1610 class VST1Q op7_4, string Dt, Operand AddrMode>
1611 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
1569 class VST1Q op7_4, string Dt>
1570 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListDPair:$Vd),
16121571 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
16131572 let Rm = 0b1111;
16141573 let Inst{5-4} = Rn{5-4};
16151574 let DecoderMethod = "DecodeVLDST1Instruction";
16161575 }
16171576
1618 def VST1d8 : VST1D<{0,0,0,?}, "8", addrmode6align64>;
1619 def VST1d16 : VST1D<{0,1,0,?}, "16", addrmode6align64>;
1620 def VST1d32 : VST1D<{1,0,0,?}, "32", addrmode6align64>;
1621 def VST1d64 : VST1D<{1,1,0,?}, "64", addrmode6align64>;
1622
1623 def VST1q8 : VST1Q<{0,0,?,?}, "8", addrmode6align64or128>;
1624 def VST1q16 : VST1Q<{0,1,?,?}, "16", addrmode6align64or128>;
1625 def VST1q32 : VST1Q<{1,0,?,?}, "32", addrmode6align64or128>;
1626 def VST1q64 : VST1Q<{1,1,?,?}, "64", addrmode6align64or128>;
1577 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1578 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1579 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1580 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1581
1582 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1583 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1584 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1585 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
16271586
16281587 // ...with address register writeback:
1629 multiclass VST1DWB op7_4, string Dt, Operand AddrMode> {
1588 multiclass VST1DWB op7_4, string Dt> {
16301589 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1631 (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1590 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
16321591 "vst1", Dt, "$Vd, $Rn!",
16331592 "$Rn.addr = $wb", []> {
16341593 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
16361595 let DecoderMethod = "DecodeVLDST1Instruction";
16371596 }
16381597 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1639 (ins AddrMode:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1598 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
16401599 IIC_VLD1u,
16411600 "vst1", Dt, "$Vd, $Rn, $Rm",
16421601 "$Rn.addr = $wb", []> {
16441603 let DecoderMethod = "DecodeVLDST1Instruction";
16451604 }
16461605 }
1647 multiclass VST1QWB op7_4, string Dt, Operand AddrMode> {
1606 multiclass VST1QWB op7_4, string Dt> {
16481607 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1649 (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1608 (ins addrmode6:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
16501609 "vst1", Dt, "$Vd, $Rn!",
16511610 "$Rn.addr = $wb", []> {
16521611 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
16541613 let DecoderMethod = "DecodeVLDST1Instruction";
16551614 }
16561615 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1657 (ins AddrMode:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1616 (ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd),
16581617 IIC_VLD1x2u,
16591618 "vst1", Dt, "$Vd, $Rn, $Rm",
16601619 "$Rn.addr = $wb", []> {
16631622 }
16641623 }
16651624
1666 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8", addrmode6align64>;
1667 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16", addrmode6align64>;
1668 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32", addrmode6align64>;
1669 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64", addrmode6align64>;
1670
1671 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8", addrmode6align64or128>;
1672 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16", addrmode6align64or128>;
1673 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32", addrmode6align64or128>;
1674 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64", addrmode6align64or128>;
1625 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1626 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1627 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1628 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
1629
1630 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1631 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1632 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1633 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
16751634
16761635 // ...with 3 registers
1677 class VST1D3 op7_4, string Dt, Operand AddrMode>
1636 class VST1D3 op7_4, string Dt>
16781637 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1679 (ins AddrMode:$Rn, VecListThreeD:$Vd),
1638 (ins addrmode6:$Rn, VecListThreeD:$Vd),
16801639 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
16811640 let Rm = 0b1111;
16821641 let Inst{4} = Rn{4};
16831642 let DecoderMethod = "DecodeVLDST1Instruction";
16841643 }
1685 multiclass VST1D3WB op7_4, string Dt, Operand AddrMode> {
1644 multiclass VST1D3WB op7_4, string Dt> {
16861645 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1687 (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1646 (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
16881647 "vst1", Dt, "$Vd, $Rn!",
16891648 "$Rn.addr = $wb", []> {
16901649 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
16921651 let DecoderMethod = "DecodeVLDST1Instruction";
16931652 }
16941653 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1695 (ins AddrMode:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1654 (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
16961655 IIC_VLD1x3u,
16971656 "vst1", Dt, "$Vd, $Rn, $Rm",
16981657 "$Rn.addr = $wb", []> {
17011660 }
17021661 }
17031662
1704 def VST1d8T : VST1D3<{0,0,0,?}, "8", addrmode6align64>;
1705 def VST1d16T : VST1D3<{0,1,0,?}, "16", addrmode6align64>;
1706 def VST1d32T : VST1D3<{1,0,0,?}, "32", addrmode6align64>;
1707 def VST1d64T : VST1D3<{1,1,0,?}, "64", addrmode6align64>;
1708
1709 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8", addrmode6align64>;
1710 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16", addrmode6align64>;
1711 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32", addrmode6align64>;
1712 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64", addrmode6align64>;
1663 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1664 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1665 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1666 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1667
1668 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
1669 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
1670 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
1671 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
17131672
17141673 def VST1d64TPseudo : VSTQQPseudo;
17151674 def VST1d64TPseudoWB_fixed : VSTQQWBfixedPseudo;
17161675 def VST1d64TPseudoWB_register : VSTQQWBPseudo;
17171676
17181677 // ...with 4 registers
1719 class VST1D4 op7_4, string Dt, Operand AddrMode>
1678 class VST1D4 op7_4, string Dt>
17201679 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1721 (ins AddrMode:$Rn, VecListFourD:$Vd),
1680 (ins addrmode6:$Rn, VecListFourD:$Vd),
17221681 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
17231682 []> {
17241683 let Rm = 0b1111;
17251684 let Inst{5-4} = Rn{5-4};
17261685 let DecoderMethod = "DecodeVLDST1Instruction";
17271686 }
1728 multiclass VST1D4WB op7_4, string Dt, Operand AddrMode> {
1687 multiclass VST1D4WB op7_4, string Dt> {
17291688 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1730 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1689 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
17311690 "vst1", Dt, "$Vd, $Rn!",
17321691 "$Rn.addr = $wb", []> {
17331692 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
17351694 let DecoderMethod = "DecodeVLDST1Instruction";
17361695 }
17371696 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1738 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1697 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
17391698 IIC_VLD1x4u,
17401699 "vst1", Dt, "$Vd, $Rn, $Rm",
17411700 "$Rn.addr = $wb", []> {
17441703 }
17451704 }
17461705
1747 def VST1d8Q : VST1D4<{0,0,?,?}, "8", addrmode6align64or128or256>;
1748 def VST1d16Q : VST1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;
1749 def VST1d32Q : VST1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;
1750 def VST1d64Q : VST1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;
1751
1752 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>;
1753 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;
1754 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;
1755 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;
1706 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1707 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1708 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1709 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1710
1711 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;
1712 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;
1713 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;
1714 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;
17561715
17571716 def VST1d64QPseudo : VSTQQPseudo;
17581717 def VST1d64QPseudoWB_fixed : VSTQQWBfixedPseudo;
17601719
17611720 // VST2 : Vector Store (multiple 2-element structures)
17621721 class VST2 op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1763 InstrItinClass itin, Operand AddrMode>
1764 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, VdTy:$Vd),
1722 InstrItinClass itin>
1723 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd),
17651724 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
17661725 let Rm = 0b1111;
17671726 let Inst{5-4} = Rn{5-4};
17681727 let DecoderMethod = "DecodeVLDST2Instruction";
17691728 }
17701729
1771 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2,
1772 addrmode6align64or128>;
1773 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2,
1774 addrmode6align64or128>;
1775 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2,
1776 addrmode6align64or128>;
1777
1778 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2,
1779 addrmode6align64or128or256>;
1780 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2,
1781 addrmode6align64or128or256>;
1782 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2,
1783 addrmode6align64or128or256>;
1730 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2>;
1731 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2>;
1732 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2>;
1733
1734 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;
1735 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;
1736 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;
17841737
17851738 def VST2q8Pseudo : VSTQQPseudo;
17861739 def VST2q16Pseudo : VSTQQPseudo;
17881741
17891742 // ...with address register writeback:
17901743 multiclass VST2DWB op11_8, bits<4> op7_4, string Dt,
1791 RegisterOperand VdTy, Operand AddrMode> {
1744 RegisterOperand VdTy> {
17921745 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1793 (ins AddrMode:$Rn, VdTy:$Vd), IIC_VLD1u,
1746 (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u,
17941747 "vst2", Dt, "$Vd, $Rn!",
17951748 "$Rn.addr = $wb", []> {
17961749 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
17981751 let DecoderMethod = "DecodeVLDST2Instruction";
17991752 }
18001753 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1801 (ins AddrMode:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1754 (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
18021755 "vst2", Dt, "$Vd, $Rn, $Rm",
18031756 "$Rn.addr = $wb", []> {
18041757 let Inst{5-4} = Rn{5-4};
18051758 let DecoderMethod = "DecodeVLDST2Instruction";
18061759 }
18071760 }
1808 multiclass VST2QWB op7_4, string Dt, Operand AddrMode> {
1761 multiclass VST2QWB op7_4, string Dt> {
18091762 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1810 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1763 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u,
18111764 "vst2", Dt, "$Vd, $Rn!",
18121765 "$Rn.addr = $wb", []> {
18131766 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
18151768 let DecoderMethod = "DecodeVLDST2Instruction";
18161769 }
18171770 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1818 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1771 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
18191772 IIC_VLD1u,
18201773 "vst2", Dt, "$Vd, $Rn, $Rm",
18211774 "$Rn.addr = $wb", []> {
18241777 }
18251778 }
18261779
1827 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair,
1828 addrmode6align64or128>;
1829 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair,
1830 addrmode6align64or128>;
1831 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair,
1832 addrmode6align64or128>;
1833
1834 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8", addrmode6align64or128or256>;
1835 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16", addrmode6align64or128or256>;
1836 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32", addrmode6align64or128or256>;
1780 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair>;
1781 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair>;
1782 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair>;
1783
1784 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
1785 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
1786 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
18371787
18381788 def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo;
18391789 def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo;
18431793 def VST2q32PseudoWB_register : VSTQQWBregisterPseudo;
18441794
18451795 // ...with double-spaced registers
1846 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2,
1847 addrmode6align64or128>;
1848 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2,
1849 addrmode6align64or128>;
1850 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2,
1851 addrmode6align64or128>;
1852 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced,
1853 addrmode6align64or128>;
1854 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced,
1855 addrmode6align64or128>;
1856 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced,
1857 addrmode6align64or128>;
1796 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2>;
1797 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2>;
1798 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2>;
1799 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced>;
1800 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced>;
1801 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced>;
18581802
18591803 // VST3 : Vector Store (multiple 3-element structures)
18601804 class VST3D op11_8, bits<4> op7_4, string Dt>
63666310 // VLD1 single-lane pseudo-instructions. These need special handling for
63676311 // the lane index that an InstAlias can't handle, so we use these instead.
63686312 def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
6369 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6370 pred:$p)>;
6313 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
63716314 def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",
6372 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6373 pred:$p)>;
6315 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
63746316 def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",
6375 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6376 pred:$p)>;
6317 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
63776318
63786319 def VLD1LNdWB_fixed_Asm_8 :
63796320 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",
6380 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6381 pred:$p)>;
6321 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
63826322 def VLD1LNdWB_fixed_Asm_16 :
63836323 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",
6384 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6385 pred:$p)>;
6324 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
63866325 def VLD1LNdWB_fixed_Asm_32 :
63876326 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",
6388 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6389 pred:$p)>;
6327 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
63906328 def VLD1LNdWB_register_Asm_8 :
63916329 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",
6392 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6330 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
63936331 rGPR:$Rm, pred:$p)>;
63946332 def VLD1LNdWB_register_Asm_16 :
63956333 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",
6396 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6334 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
63976335 rGPR:$Rm, pred:$p)>;
63986336 def VLD1LNdWB_register_Asm_32 :
63996337 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",
6400 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6338 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
64016339 rGPR:$Rm, pred:$p)>;
64026340
64036341
64046342 // VST1 single-lane pseudo-instructions. These need special handling for
64056343 // the lane index that an InstAlias can't handle, so we use these instead.
64066344 def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",
6407 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6408 pred:$p)>;
6345 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
64096346 def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",
6410 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6411 pred:$p)>;
6347 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
64126348 def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",
6413 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6414 pred:$p)>;
6349 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
64156350
64166351 def VST1LNdWB_fixed_Asm_8 :
64176352 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",
6418 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6419 pred:$p)>;
6353 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
64206354 def VST1LNdWB_fixed_Asm_16 :
64216355 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",
6422 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6423 pred:$p)>;
6356 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
64246357 def VST1LNdWB_fixed_Asm_32 :
64256358 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",
6426 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6427 pred:$p)>;
6359 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
64286360 def VST1LNdWB_register_Asm_8 :
64296361 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",
6430 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6362 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
64316363 rGPR:$Rm, pred:$p)>;
64326364 def VST1LNdWB_register_Asm_16 :
64336365 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",
6434 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6366 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
64356367 rGPR:$Rm, pred:$p)>;
64366368 def VST1LNdWB_register_Asm_32 :
64376369 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",
6438 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6370 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
64396371 rGPR:$Rm, pred:$p)>;
64406372
64416373 // VLD2 single-lane pseudo-instructions. These need special handling for
64426374 // the lane index that an InstAlias can't handle, so we use these instead.
64436375 def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
6444 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6445 pred:$p)>;
6376 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
64466377 def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6447 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6448 pred:$p)>;
6378 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
64496379 def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6450 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p)>;
6380 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
64516381 def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6452 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6453 pred:$p)>;
6382 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
64546383 def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6455 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6456 pred:$p)>;
6384 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
64576385
64586386 def VLD2LNdWB_fixed_Asm_8 :
64596387 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",
6460 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6461 pred:$p)>;
6388 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
64626389 def VLD2LNdWB_fixed_Asm_16 :
64636390 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6464 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6465 pred:$p)>;
6391 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
64666392 def VLD2LNdWB_fixed_Asm_32 :
64676393 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6468 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6469 pred:$p)>;
6394 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
64706395 def VLD2LNqWB_fixed_Asm_16 :
64716396 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6472 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6473 pred:$p)>;
6397 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
64746398 def VLD2LNqWB_fixed_Asm_32 :
64756399 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6476 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6477 pred:$p)>;
6400 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
64786401 def VLD2LNdWB_register_Asm_8 :
64796402 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",
6480 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6403 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
64816404 rGPR:$Rm, pred:$p)>;
64826405 def VLD2LNdWB_register_Asm_16 :
64836406 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6484 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6407 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
64856408 rGPR:$Rm, pred:$p)>;
64866409 def VLD2LNdWB_register_Asm_32 :
64876410 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6488 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6411 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
64896412 rGPR:$Rm, pred:$p)>;
64906413 def VLD2LNqWB_register_Asm_16 :
64916414 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6492 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6415 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
64936416 rGPR:$Rm, pred:$p)>;
64946417 def VLD2LNqWB_register_Asm_32 :
64956418 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6496 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6419 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
64976420 rGPR:$Rm, pred:$p)>;
64986421
64996422
65006423 // VST2 single-lane pseudo-instructions. These need special handling for
65016424 // the lane index that an InstAlias can't handle, so we use these instead.
65026425 def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",
6503 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6504 pred:$p)>;
6426 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
65056427 def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6506 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6507 pred:$p)>;
6428 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
65086429 def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6509 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6510 pred:$p)>;
6430 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
65116431 def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6512 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6513 pred:$p)>;
6432 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
65146433 def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6515 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6516 pred:$p)>;
6434 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
65176435
65186436 def VST2LNdWB_fixed_Asm_8 :
65196437 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",
6520 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6521 pred:$p)>;
6438 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
65226439 def VST2LNdWB_fixed_Asm_16 :
65236440 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6524 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6525 pred:$p)>;
6441 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
65266442 def VST2LNdWB_fixed_Asm_32 :
65276443 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6528 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6529 pred:$p)>;
6444 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
65306445 def VST2LNqWB_fixed_Asm_16 :
65316446 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6532 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6533 pred:$p)>;
6447 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
65346448 def VST2LNqWB_fixed_Asm_32 :
65356449 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6536 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6537 pred:$p)>;
6450 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
65386451 def VST2LNdWB_register_Asm_8 :
65396452 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",
6540 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6453 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
65416454 rGPR:$Rm, pred:$p)>;
65426455 def VST2LNdWB_register_Asm_16 :
65436456 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6544 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6457 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
65456458 rGPR:$Rm, pred:$p)>;
65466459 def VST2LNdWB_register_Asm_32 :
65476460 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6548 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6461 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
65496462 rGPR:$Rm, pred:$p)>;
65506463 def VST2LNqWB_register_Asm_16 :
65516464 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6552 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6465 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
65536466 rGPR:$Rm, pred:$p)>;
65546467 def VST2LNqWB_register_Asm_32 :
65556468 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6556 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6469 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
65576470 rGPR:$Rm, pred:$p)>;
65586471
65596472 // VLD3 all-lanes pseudo-instructions. These need special handling for
65606473 // the lane index that an InstAlias can't handle, so we use these instead.
65616474 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6562 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6563 pred:$p)>;
6475 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
65646476 def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6565 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6566 pred:$p)>;
6477 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
65676478 def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6568 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6569 pred:$p)>;
6479 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
65706480 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6571 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6572 pred:$p)>;
6481 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
65736482 def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6574 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6575 pred:$p)>;
6483 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
65766484 def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6577 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6578 pred:$p)>;
6485 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
65796486
65806487 def VLD3DUPdWB_fixed_Asm_8 :
65816488 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6582 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6583 pred:$p)>;
6489 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
65846490 def VLD3DUPdWB_fixed_Asm_16 :
65856491 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6586 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6587 pred:$p)>;
6492 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
65886493 def VLD3DUPdWB_fixed_Asm_32 :
65896494 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6590 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6591 pred:$p)>;
6495 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
65926496 def VLD3DUPqWB_fixed_Asm_8 :
65936497 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6594 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6595 pred:$p)>;
6498 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
65966499 def VLD3DUPqWB_fixed_Asm_16 :
65976500 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6598 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6599 pred:$p)>;
6501 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
66006502 def VLD3DUPqWB_fixed_Asm_32 :
66016503 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6602 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6603 pred:$p)>;
6504 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
66046505 def VLD3DUPdWB_register_Asm_8 :
66056506 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6606 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6507 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
66076508 rGPR:$Rm, pred:$p)>;
66086509 def VLD3DUPdWB_register_Asm_16 :
66096510 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6610 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6511 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
66116512 rGPR:$Rm, pred:$p)>;
66126513 def VLD3DUPdWB_register_Asm_32 :
66136514 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6614 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6515 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
66156516 rGPR:$Rm, pred:$p)>;
66166517 def VLD3DUPqWB_register_Asm_8 :
66176518 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6618 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6519 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
66196520 rGPR:$Rm, pred:$p)>;
66206521 def VLD3DUPqWB_register_Asm_16 :
66216522 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6622 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6523 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
66236524 rGPR:$Rm, pred:$p)>;
66246525 def VLD3DUPqWB_register_Asm_32 :
66256526 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6626 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6527 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
66276528 rGPR:$Rm, pred:$p)>;
66286529
66296530
66306531 // VLD3 single-lane pseudo-instructions. These need special handling for
66316532 // the lane index that an InstAlias can't handle, so we use these instead.
66326533 def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6633 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6634 pred:$p)>;
6534 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
66356535 def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6636 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6637 pred:$p)>;
6536 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
66386537 def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6639 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6640 pred:$p)>;
6538 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
66416539 def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6642 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6643 pred:$p)>;
6540 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
66446541 def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6645 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6646 pred:$p)>;
6542 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
66476543
66486544 def VLD3LNdWB_fixed_Asm_8 :
66496545 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6650 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6651 pred:$p)>;
6546 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
66526547 def VLD3LNdWB_fixed_Asm_16 :
66536548 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6654 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6655 pred:$p)>;
6549 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
66566550 def VLD3LNdWB_fixed_Asm_32 :
66576551 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6658 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6659 pred:$p)>;
6552 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
66606553 def VLD3LNqWB_fixed_Asm_16 :
66616554 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6662 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6663 pred:$p)>;
6555 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
66646556 def VLD3LNqWB_fixed_Asm_32 :
66656557 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6666 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6667 pred:$p)>;
6558 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
66686559 def VLD3LNdWB_register_Asm_8 :
66696560 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6670 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6561 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
66716562 rGPR:$Rm, pred:$p)>;
66726563 def VLD3LNdWB_register_Asm_16 :
66736564 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6674 (ins VecListThreeDHWordIndexed:$list,
6675 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
6565 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6566 rGPR:$Rm, pred:$p)>;
66766567 def VLD3LNdWB_register_Asm_32 :
66776568 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6678 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6569 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
66796570 rGPR:$Rm, pred:$p)>;
66806571 def VLD3LNqWB_register_Asm_16 :
66816572 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6682 (ins VecListThreeQHWordIndexed:$list,
6683 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
6573 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6574 rGPR:$Rm, pred:$p)>;
66846575 def VLD3LNqWB_register_Asm_32 :
66856576 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6686 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6577 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
66876578 rGPR:$Rm, pred:$p)>;
66886579
66896580 // VLD3 multiple structure pseudo-instructions. These need special handling for
66906581 // the vector operands that the normal instructions don't yet model.
66916582 // FIXME: Remove these when the register classes and instructions are updated.
66926583 def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6693 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6584 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
66946585 def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6695 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6586 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
66966587 def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6697 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6588 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
66986589 def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6699 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6590 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
67006591 def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6701 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6592 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
67026593 def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6703 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6594 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
67046595
67056596 def VLD3dWB_fixed_Asm_8 :
67066597 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6707 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6598 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
67086599 def VLD3dWB_fixed_Asm_16 :
67096600 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6710 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6601 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
67116602 def VLD3dWB_fixed_Asm_32 :
67126603 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6713 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6604 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
67146605 def VLD3qWB_fixed_Asm_8 :
67156606 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6716 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6607 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
67176608 def VLD3qWB_fixed_Asm_16 :
67186609 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6719 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6610 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
67206611 def VLD3qWB_fixed_Asm_32 :
67216612 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6722 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6613 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
67236614 def VLD3dWB_register_Asm_8 :
67246615 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6725 (ins VecListThreeD:$list, addrmode6align64:$addr,
6616 (ins VecListThreeD:$list, addrmode6:$addr,
67266617 rGPR:$Rm, pred:$p)>;
67276618 def VLD3dWB_register_Asm_16 :
67286619 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6729 (ins VecListThreeD:$list, addrmode6align64:$addr,
6620 (ins VecListThreeD:$list, addrmode6:$addr,
67306621 rGPR:$Rm, pred:$p)>;
67316622 def VLD3dWB_register_Asm_32 :
67326623 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6733 (ins VecListThreeD:$list, addrmode6align64:$addr,
6624 (ins VecListThreeD:$list, addrmode6:$addr,
67346625 rGPR:$Rm, pred:$p)>;
67356626 def VLD3qWB_register_Asm_8 :
67366627 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6737 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6628 (ins VecListThreeQ:$list, addrmode6:$addr,
67386629 rGPR:$Rm, pred:$p)>;
67396630 def VLD3qWB_register_Asm_16 :
67406631 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6741 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6632 (ins VecListThreeQ:$list, addrmode6:$addr,
67426633 rGPR:$Rm, pred:$p)>;
67436634 def VLD3qWB_register_Asm_32 :
67446635 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6745 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6636 (ins VecListThreeQ:$list, addrmode6:$addr,
67466637 rGPR:$Rm, pred:$p)>;
67476638
67486639 // VST3 single-lane pseudo-instructions. These need special handling for
67496640 // the lane index that an InstAlias can't handle, so we use these instead.
67506641 def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6751 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6752 pred:$p)>;
6642 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
67536643 def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6754 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6755 pred:$p)>;
6644 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
67566645 def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6757 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6758 pred:$p)>;
6646 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
67596647 def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6760 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6761 pred:$p)>;
6648 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
67626649 def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6763 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6764 pred:$p)>;
6650 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
67656651
67666652 def VST3LNdWB_fixed_Asm_8 :
67676653 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6768 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6769 pred:$p)>;
6654 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
67706655 def VST3LNdWB_fixed_Asm_16 :
67716656 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6772 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6773 pred:$p)>;
6657 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
67746658 def VST3LNdWB_fixed_Asm_32 :
67756659 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6776 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6777 pred:$p)>;
6660 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
67786661 def VST3LNqWB_fixed_Asm_16 :
67796662 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6780 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6781 pred:$p)>;
6663 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
67826664 def VST3LNqWB_fixed_Asm_32 :
67836665 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6784 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6785 pred:$p)>;
6666 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
67866667 def VST3LNdWB_register_Asm_8 :
67876668 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6788 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6669 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
67896670 rGPR:$Rm, pred:$p)>;
67906671 def VST3LNdWB_register_Asm_16 :
67916672 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6792 (ins VecListThreeDHWordIndexed:$list,
6793 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
6673 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6674 rGPR:$Rm, pred:$p)>;
67946675 def VST3LNdWB_register_Asm_32 :
67956676 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6796 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6677 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
67976678 rGPR:$Rm, pred:$p)>;
67986679 def VST3LNqWB_register_Asm_16 :
67996680 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6800 (ins VecListThreeQHWordIndexed:$list,
6801 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
6681 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6682 rGPR:$Rm, pred:$p)>;
68026683 def VST3LNqWB_register_Asm_32 :
68036684 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6804 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6685 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
68056686 rGPR:$Rm, pred:$p)>;
68066687
68076688
68096690 // the vector operands that the normal instructions don't yet model.
68106691 // FIXME: Remove these when the register classes and instructions are updated.
68116692 def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6812 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6693 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
68136694 def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6814 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6695 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
68156696 def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6816 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6697 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
68176698 def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6818 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6699 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
68196700 def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6820 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6701 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
68216702 def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6822 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6703 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
68236704
68246705 def VST3dWB_fixed_Asm_8 :
68256706 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6826 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6707 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
68276708 def VST3dWB_fixed_Asm_16 :
68286709 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6829 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6710 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
68306711 def VST3dWB_fixed_Asm_32 :
68316712 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6832 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6713 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
68336714 def VST3qWB_fixed_Asm_8 :
68346715 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6835 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6716 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
68366717 def VST3qWB_fixed_Asm_16 :
68376718 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6838 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6719 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
68396720 def VST3qWB_fixed_Asm_32 :
68406721 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6841 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6722 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
68426723 def VST3dWB_register_Asm_8 :
68436724 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6844 (ins VecListThreeD:$list, addrmode6align64:$addr,
6725 (ins VecListThreeD:$list, addrmode6:$addr,
68456726 rGPR:$Rm, pred:$p)>;
68466727 def VST3dWB_register_Asm_16 :
68476728 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6848 (ins VecListThreeD:$list, addrmode6align64:$addr,
6729 (ins VecListThreeD:$list, addrmode6:$addr,
68496730 rGPR:$Rm, pred:$p)>;
68506731 def VST3dWB_register_Asm_32 :
68516732 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6852 (ins VecListThreeD:$list, addrmode6align64:$addr,
6733 (ins VecListThreeD:$list, addrmode6:$addr,
68536734 rGPR:$Rm, pred:$p)>;
68546735 def VST3qWB_register_Asm_8 :
68556736 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6856 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6737 (ins VecListThreeQ:$list, addrmode6:$addr,
68576738 rGPR:$Rm, pred:$p)>;
68586739 def VST3qWB_register_Asm_16 :
68596740 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6860 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6741 (ins VecListThreeQ:$list, addrmode6:$addr,
68616742 rGPR:$Rm, pred:$p)>;
68626743 def VST3qWB_register_Asm_32 :
68636744 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6864 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6745 (ins VecListThreeQ:$list, addrmode6:$addr,
68656746 rGPR:$Rm, pred:$p)>;
68666747
68676748 // VLD4 all-lanes pseudo-instructions. These need special handling for
68686749 // the lane index that an InstAlias can't handle, so we use these instead.
68696750 def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6870 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
6871 pred:$p)>;
6751 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
68726752 def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6873 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
6874 pred:$p)>;
6753 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
68756754 def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6876 (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr,
6877 pred:$p)>;
6755 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
68786756 def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6879 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
6880 pred:$p)>;
6757 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
68816758 def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6882 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
6883 pred:$p)>;
6759 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
68846760 def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6885 (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr,
6886 pred:$p)>;
6761 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
68876762
68886763 def VLD4DUPdWB_fixed_Asm_8 :
68896764 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6890 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
6891 pred:$p)>;
6765 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
68926766 def VLD4DUPdWB_fixed_Asm_16 :
68936767 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6894 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
6895 pred:$p)>;
6768 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
68966769 def VLD4DUPdWB_fixed_Asm_32 :
68976770 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6898 (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr,
6899 pred:$p)>;
6771 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
69006772 def VLD4DUPqWB_fixed_Asm_8 :
69016773 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6902 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
6903 pred:$p)>;
6774 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
69046775 def VLD4DUPqWB_fixed_Asm_16 :
69056776 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6906 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
6907 pred:$p)>;
6777 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
69086778 def VLD4DUPqWB_fixed_Asm_32 :
69096779 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6910 (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr,
6911 pred:$p)>;
6780 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
69126781 def VLD4DUPdWB_register_Asm_8 :
69136782 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6914 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
6783 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
69156784 rGPR:$Rm, pred:$p)>;
69166785 def VLD4DUPdWB_register_Asm_16 :
69176786 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6918 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
6787 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
69196788 rGPR:$Rm, pred:$p)>;
69206789 def VLD4DUPdWB_register_Asm_32 :
69216790 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6922 (ins VecListFourDAllLanes:$list,
6923 addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>;
6791 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6792 rGPR:$Rm, pred:$p)>;
69246793 def VLD4DUPqWB_register_Asm_8 :
69256794 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6926 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
6795 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
69276796 rGPR:$Rm, pred:$p)>;
69286797 def VLD4DUPqWB_register_Asm_16 :
69296798 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6930 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
6799 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
69316800 rGPR:$Rm, pred:$p)>;
69326801 def VLD4DUPqWB_register_Asm_32 :
69336802 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6934 (ins VecListFourQAllLanes:$list,
6935 addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>;
6803 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6804 rGPR:$Rm, pred:$p)>;
69366805
69376806
69386807 // VLD4 single-lane pseudo-instructions. These need special handling for
69396808 // the lane index that an InstAlias can't handle, so we use these instead.
69406809 def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6941 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
6942 pred:$p)>;
6810 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
69436811 def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6944 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
6945 pred:$p)>;
6812 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
69466813 def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6947 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
6948 pred:$p)>;
6814 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
69496815 def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6950 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
6951 pred:$p)>;
6816 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
69526817 def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6953 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
6954 pred:$p)>;
6818 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
69556819
69566820 def VLD4LNdWB_fixed_Asm_8 :
69576821 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6958 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
6959 pred:$p)>;
6822 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
69606823 def VLD4LNdWB_fixed_Asm_16 :
69616824 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6962 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
6963 pred:$p)>;
6825 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
69646826 def VLD4LNdWB_fixed_Asm_32 :
69656827 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6966 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
6967 pred:$p)>;
6828 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
69686829 def VLD4LNqWB_fixed_Asm_16 :
69696830 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6970 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
6971 pred:$p)>;
6831 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
69726832 def VLD4LNqWB_fixed_Asm_32 :
69736833 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6974 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
6975 pred:$p)>;
6834 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
69766835 def VLD4LNdWB_register_Asm_8 :
69776836 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6978 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
6837 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
69796838 rGPR:$Rm, pred:$p)>;
69806839 def VLD4LNdWB_register_Asm_16 :
69816840 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6982 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
6841 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
69836842 rGPR:$Rm, pred:$p)>;
69846843 def VLD4LNdWB_register_Asm_32 :
69856844 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6986 (ins VecListFourDWordIndexed:$list,
6987 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
6845 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6846 rGPR:$Rm, pred:$p)>;
69886847 def VLD4LNqWB_register_Asm_16 :
69896848 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6990 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
6849 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
69916850 rGPR:$Rm, pred:$p)>;
69926851 def VLD4LNqWB_register_Asm_32 :
69936852 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6994 (ins VecListFourQWordIndexed:$list,
6995 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
6853 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6854 rGPR:$Rm, pred:$p)>;
69966855
69976856
69986857
70006859 // the vector operands that the normal instructions don't yet model.
70016860 // FIXME: Remove these when the register classes and instructions are updated.
70026861 def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7003 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7004 pred:$p)>;
6862 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
70056863 def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7006 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7007 pred:$p)>;
6864 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
70086865 def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7009 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7010 pred:$p)>;
6866 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
70116867 def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7012 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7013 pred:$p)>;
6868 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
70146869 def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7015 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7016 pred:$p)>;
6870 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
70176871 def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7018 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7019 pred:$p)>;
6872 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
70206873
70216874 def VLD4dWB_fixed_Asm_8 :
70226875 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7023 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7024 pred:$p)>;
6876 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
70256877 def VLD4dWB_fixed_Asm_16 :
70266878 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7027 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7028 pred:$p)>;
6879 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
70296880 def VLD4dWB_fixed_Asm_32 :
70306881 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7031 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7032 pred:$p)>;
6882 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
70336883 def VLD4qWB_fixed_Asm_8 :
70346884 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7035 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7036 pred:$p)>;
6885 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
70376886 def VLD4qWB_fixed_Asm_16 :
70386887 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7039 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7040 pred:$p)>;
6888 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
70416889 def VLD4qWB_fixed_Asm_32 :
70426890 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7043 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7044 pred:$p)>;
6891 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
70456892 def VLD4dWB_register_Asm_8 :
70466893 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7047 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
6894 (ins VecListFourD:$list, addrmode6:$addr,
70486895 rGPR:$Rm, pred:$p)>;
70496896 def VLD4dWB_register_Asm_16 :
70506897 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7051 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
6898 (ins VecListFourD:$list, addrmode6:$addr,
70526899 rGPR:$Rm, pred:$p)>;
70536900 def VLD4dWB_register_Asm_32 :
70546901 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7055 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
6902 (ins VecListFourD:$list, addrmode6:$addr,
70566903 rGPR:$Rm, pred:$p)>;
70576904 def VLD4qWB_register_Asm_8 :
70586905 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7059 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
6906 (ins VecListFourQ:$list, addrmode6:$addr,
70606907 rGPR:$Rm, pred:$p)>;
70616908 def VLD4qWB_register_Asm_16 :
70626909 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7063 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
6910 (ins VecListFourQ:$list, addrmode6:$addr,
70646911 rGPR:$Rm, pred:$p)>;
70656912 def VLD4qWB_register_Asm_32 :
70666913 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7067 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
6914 (ins VecListFourQ:$list, addrmode6:$addr,
70686915 rGPR:$Rm, pred:$p)>;
70696916
70706917 // VST4 single-lane pseudo-instructions. These need special handling for
70716918 // the lane index that an InstAlias can't handle, so we use these instead.
70726919 def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7073 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7074 pred:$p)>;
6920 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
70756921 def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7076 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7077 pred:$p)>;
6922 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
70786923 def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7079 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7080 pred:$p)>;
6924 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
70816925 def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7082 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7083 pred:$p)>;
6926 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
70846927 def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7085 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7086 pred:$p)>;
6928 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
70876929
70886930 def VST4LNdWB_fixed_Asm_8 :
70896931 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7090 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7091 pred:$p)>;
6932 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
70926933 def VST4LNdWB_fixed_Asm_16 :
70936934 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7094 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7095 pred:$p)>;
6935 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
70966936 def VST4LNdWB_fixed_Asm_32 :
70976937 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7098 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7099 pred:$p)>;
6938 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
71006939 def VST4LNqWB_fixed_Asm_16 :
71016940 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7102 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7103 pred:$p)>;
6941 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
71046942 def VST4LNqWB_fixed_Asm_32 :
71056943 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7106 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7107 pred:$p)>;
6944 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
71086945 def VST4LNdWB_register_Asm_8 :
71096946 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7110 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
6947 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
71116948 rGPR:$Rm, pred:$p)>;
71126949 def VST4LNdWB_register_Asm_16 :
71136950 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7114 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
6951 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
71156952 rGPR:$Rm, pred:$p)>;
71166953 def VST4LNdWB_register_Asm_32 :
71176954 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7118 (ins VecListFourDWordIndexed:$list,
7119 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
6955 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6956 rGPR:$Rm, pred:$p)>;
71206957 def VST4LNqWB_register_Asm_16 :
71216958 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7122 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
6959 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
71236960 rGPR:$Rm, pred:$p)>;
71246961 def VST4LNqWB_register_Asm_32 :
71256962 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7126 (ins VecListFourQWordIndexed:$list,
7127 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
6963 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6964 rGPR:$Rm, pred:$p)>;
71286965
71296966
71306967 // VST4 multiple structure pseudo-instructions. These need special handling for
71316968 // the vector operands that the normal instructions don't yet model.
71326969 // FIXME: Remove these when the register classes and instructions are updated.
71336970 def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7134 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7135 pred:$p)>;
6971 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
71366972 def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7137 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7138 pred:$p)>;
6973 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
71396974 def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7140 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7141 pred:$p)>;
6975 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
71426976 def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7143 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7144 pred:$p)>;
6977 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
71456978 def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7146 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7147 pred:$p)>;
6979 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
71486980 def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7149 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7150 pred:$p)>;
6981 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
71516982
71526983 def VST4dWB_fixed_Asm_8 :
71536984 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7154 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7155 pred:$p)>;
6985 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
71566986 def VST4dWB_fixed_Asm_16 :
71576987 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7158 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7159 pred:$p)>;
6988 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
71606989 def VST4dWB_fixed_Asm_32 :
71616990 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7162 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7163 pred:$p)>;
6991 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
71646992 def VST4qWB_fixed_Asm_8 :
71656993 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7166 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7167 pred:$p)>;
6994 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
71686995 def VST4qWB_fixed_Asm_16 :
71696996 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7170 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7171 pred:$p)>;
6997 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
71726998 def VST4qWB_fixed_Asm_32 :
71736999 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7174 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7175 pred:$p)>;
7000 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
71767001 def VST4dWB_register_Asm_8 :
71777002 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7178 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7003 (ins VecListFourD:$list, addrmode6:$addr,
71797004 rGPR:$Rm, pred:$p)>;
71807005 def VST4dWB_register_Asm_16 :
71817006 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7182 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7007 (ins VecListFourD:$list, addrmode6:$addr,
71837008 rGPR:$Rm, pred:$p)>;
71847009 def VST4dWB_register_Asm_32 :
71857010 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7186 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7011 (ins VecListFourD:$list, addrmode6:$addr,
71877012 rGPR:$Rm, pred:$p)>;
71887013 def VST4qWB_register_Asm_8 :
71897014 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7190 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7015 (ins VecListFourQ:$list, addrmode6:$addr,
71917016 rGPR:$Rm, pred:$p)>;
71927017 def VST4qWB_register_Asm_16 :
71937018 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7194 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7019 (ins VecListFourQ:$list, addrmode6:$addr,
71957020 rGPR:$Rm, pred:$p)>;
71967021 def VST4qWB_register_Asm_32 :
71977022 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7198 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7023 (ins VecListFourQ:$list, addrmode6:$addr,
71997024 rGPR:$Rm, pred:$p)>;
72007025
72017026 // VMOV/VMVN takes an optional datatype suffix
485485 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
486486 unsigned ShiftImm; // shift for OffsetReg.
487487 unsigned Alignment; // 0 = no alignment specified
488 SMLoc AlignmentLoc; // for error reporting if needed.
489488 // n = alignment in bytes (2, 4, 8, 16, or 32)
490489 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
491490 };
633632 /// operand.
634633 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
635634
636 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
637 SMLoc getAlignmentLoc() const {
638 assert(Kind == k_Memory && "Invalid access!");
639 return Memory.AlignmentLoc;
640 }
641
642635 ARMCC::CondCodes getCondCode() const {
643636 assert(Kind == k_CondCode && "Invalid access!");
644637 return CC.Val;
10951088 bool isPostIdxReg() const {
10961089 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
10971090 }
1098 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1091 bool isMemNoOffset(bool alignOK = false) const {
10991092 if (!isMem())
11001093 return false;
11011094 // No offset of any kind.
11021095 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1103 (alignOK || Memory.Alignment == Alignment);
1096 (alignOK || Memory.Alignment == 0);
11041097 }
11051098 bool isMemPCRelImm12() const {
11061099 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
11151108 }
11161109 bool isAlignedMemory() const {
11171110 return isMemNoOffset(true);
1118 }
1119 bool isAlignedMemoryNone() const {
1120 return isMemNoOffset(false, 0);
1121 }
1122 bool isDupAlignedMemoryNone() const {
1123 return isMemNoOffset(false, 0);
1124 }
1125 bool isAlignedMemory16() const {
1126 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1127 return true;
1128 return isMemNoOffset(false, 0);
1129 }
1130 bool isDupAlignedMemory16() const {
1131 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1132 return true;
1133 return isMemNoOffset(false, 0);
1134 }
1135 bool isAlignedMemory32() const {
1136 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1137 return true;
1138 return isMemNoOffset(false, 0);
1139 }
1140 bool isDupAlignedMemory32() const {
1141 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1142 return true;
1143 return isMemNoOffset(false, 0);
1144 }
1145 bool isAlignedMemory64() const {
1146 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1147 return true;
1148 return isMemNoOffset(false, 0);
1149 }
1150 bool isDupAlignedMemory64() const {
1151 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1152 return true;
1153 return isMemNoOffset(false, 0);
1154 }
1155 bool isAlignedMemory64or128() const {
1156 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1157 return true;
1158 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1159 return true;
1160 return isMemNoOffset(false, 0);
1161 }
1162 bool isDupAlignedMemory64or128() const {
1163 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1164 return true;
1165 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1166 return true;
1167 return isMemNoOffset(false, 0);
1168 }
1169 bool isAlignedMemory64or128or256() const {
1170 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1171 return true;
1172 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1173 return true;
1174 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1175 return true;
1176 return isMemNoOffset(false, 0);
11771111 }
11781112 bool isAddrMode2() const {
11791113 if (!isMem() || Memory.Alignment != 0) return false;
19911925 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
19921926 }
19931927
1994 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
1995 addAlignedMemoryOperands(Inst, N);
1996 }
1997
1998 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
1999 addAlignedMemoryOperands(Inst, N);
2000 }
2001
2002 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2003 addAlignedMemoryOperands(Inst, N);
2004 }
2005
2006 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2007 addAlignedMemoryOperands(Inst, N);
2008 }
2009
2010 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2011 addAlignedMemoryOperands(Inst, N);
2012 }
2013
2014 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2015 addAlignedMemoryOperands(Inst, N);
2016 }
2017
2018 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2019 addAlignedMemoryOperands(Inst, N);
2020 }
2021
2022 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2023 addAlignedMemoryOperands(Inst, N);
2024 }
2025
2026 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2027 addAlignedMemoryOperands(Inst, N);
2028 }
2029
2030 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2031 addAlignedMemoryOperands(Inst, N);
2032 }
2033
2034 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2035 addAlignedMemoryOperands(Inst, N);
2036 }
2037
20381928 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
20391929 assert(N == 3 && "Invalid number of operands!");
20401930 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
26322522 unsigned ShiftImm,
26332523 unsigned Alignment,
26342524 bool isNegative,
2635 SMLoc S, SMLoc E,
2636 SMLoc AlignmentLoc = SMLoc()) {
2525 SMLoc S, SMLoc E) {
26372526 ARMOperand *Op = new ARMOperand(k_Memory);
26382527 Op->Memory.BaseRegNum = BaseRegNum;
26392528 Op->Memory.OffsetImm = OffsetImm;
26412530 Op->Memory.ShiftType = ShiftType;
26422531 Op->Memory.ShiftImm = ShiftImm;
26432532 Op->Memory.Alignment = Alignment;
2644 Op->Memory.AlignmentLoc = AlignmentLoc;
26452533 Op->Memory.isNegative = isNegative;
26462534 Op->StartLoc = S;
26472535 Op->EndLoc = E;
44574345 if (Parser.getTok().is(AsmToken::Colon)) {
44584346 Parser.Lex(); // Eat the ':'.
44594347 E = Parser.getTok().getLoc();
4460 SMLoc AlignmentLoc = Tok.getLoc();
44614348
44624349 const MCExpr *Expr;
44634350 if (getParser().parseExpression(Expr))
44924379 // the is*() predicates.
44934380 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
44944381 ARM_AM::no_shift, 0, Align,
4495 false, S, E, AlignmentLoc));
4382 false, S, E));
44964383
44974384 // If there's a pre-indexing writeback marker, '!', just add it as a token
44984385 // operand.
80797966 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
80807967 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
80817968 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8082 }
8083 case Match_AlignedMemoryRequiresNone:
8084 case Match_DupAlignedMemoryRequiresNone:
8085 case Match_AlignedMemoryRequires16:
8086 case Match_DupAlignedMemoryRequires16:
8087 case Match_AlignedMemoryRequires32:
8088 case Match_DupAlignedMemoryRequires32:
8089 case Match_AlignedMemoryRequires64:
8090 case Match_DupAlignedMemoryRequires64:
8091 case Match_AlignedMemoryRequires64or128:
8092 case Match_DupAlignedMemoryRequires64or128:
8093 case Match_AlignedMemoryRequires64or128or256:
8094 {
8095 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getAlignmentLoc();
8096 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8097 switch (MatchResult) {
8098 default:
8099 llvm_unreachable("Missing Match_Aligned type");
8100 case Match_AlignedMemoryRequiresNone:
8101 case Match_DupAlignedMemoryRequiresNone:
8102 return Error(ErrorLoc, "alignment must be omitted");
8103 case Match_AlignedMemoryRequires16:
8104 case Match_DupAlignedMemoryRequires16:
8105 return Error(ErrorLoc, "alignment must be 16 or omitted");
8106 case Match_AlignedMemoryRequires32:
8107 case Match_DupAlignedMemoryRequires32:
8108 return Error(ErrorLoc, "alignment must be 32 or omitted");
8109 case Match_AlignedMemoryRequires64:
8110 case Match_DupAlignedMemoryRequires64:
8111 return Error(ErrorLoc, "alignment must be 64 or omitted");
8112 case Match_AlignedMemoryRequires64or128:
8113 case Match_DupAlignedMemoryRequires64or128:
8114 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8115 case Match_AlignedMemoryRequires64or128or256:
8116 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8117 }
81187969 }
81197970 }
81207971
+0
-8354
test/MC/ARM/neon-vld-vst-align.s less more
None @ RUN: not llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s > %t 2> %e
1 @ RUN: FileCheck < %t %s
2 @ RUN: FileCheck --check-prefix=CHECK-ERRORS < %e %s
3
4 vld1.8 {d0}, [r4]
5 vld1.8 {d0}, [r4:16]
6 vld1.8 {d0}, [r4:32]
7 vld1.8 {d0}, [r4:64]
8 vld1.8 {d0}, [r4:128]
9 vld1.8 {d0}, [r4:256]
10
11 @ CHECK: vld1.8 {d0}, [r4] @ encoding: [0x24,0xf9,0x0f,0x07]
12 @ CHECK-ERRORS: error: alignment must be 64 or omitted
13 @ CHECK-ERRORS: vld1.8 {d0}, [r4:16]
14 @ CHECK-ERRORS: ^
15 @ CHECK-ERRORS: error: alignment must be 64 or omitted
16 @ CHECK-ERRORS: vld1.8 {d0}, [r4:32]
17 @ CHECK-ERRORS: ^
18 @ CHECK: vld1.8 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x07]
19 @ CHECK-ERRORS: error: alignment must be 64 or omitted
20 @ CHECK-ERRORS: vld1.8 {d0}, [r4:128]
21 @ CHECK-ERRORS: ^
22 @ CHECK-ERRORS: error: alignment must be 64 or omitted
23 @ CHECK-ERRORS: vld1.8 {d0}, [r4:256]
24 @ CHECK-ERRORS: ^
25
26 vld1.8 {d0}, [r4]!
27 vld1.8 {d0}, [r4:16]!
28 vld1.8 {d0}, [r4:32]!
29 vld1.8 {d0}, [r4:64]!
30 vld1.8 {d0}, [r4:128]!
31 vld1.8 {d0}, [r4:256]!
32
33 @ CHECK: vld1.8 {d0}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x07]
34 @ CHECK-ERRORS: error: alignment must be 64 or omitted
35 @ CHECK-ERRORS: vld1.8 {d0}, [r4:16]!
36 @ CHECK-ERRORS: ^
37 @ CHECK-ERRORS: error: alignment must be 64 or omitted
38 @ CHECK-ERRORS: vld1.8 {d0}, [r4:32]!
39 @ CHECK-ERRORS: ^
40 @ CHECK: vld1.8 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x07]
41 @ CHECK-ERRORS: error: alignment must be 64 or omitted
42 @ CHECK-ERRORS: vld1.8 {d0}, [r4:128]!
43 @ CHECK-ERRORS: ^
44 @ CHECK-ERRORS: error: alignment must be 64 or omitted
45 @ CHECK-ERRORS: vld1.8 {d0}, [r4:256]!
46 @ CHECK-ERRORS: ^
47
48 vld1.8 {d0}, [r4], r6
49 vld1.8 {d0}, [r4:16], r6
50 vld1.8 {d0}, [r4:32], r6
51 vld1.8 {d0}, [r4:64], r6
52 vld1.8 {d0}, [r4:128], r6
53 vld1.8 {d0}, [r4:256], r6
54
55 @ CHECK: vld1.8 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x07]
56 @ CHECK-ERRORS: error: alignment must be 64 or omitted
57 @ CHECK-ERRORS: vld1.8 {d0}, [r4:16], r6
58 @ CHECK-ERRORS: ^
59 @ CHECK-ERRORS: error: alignment must be 64 or omitted
60 @ CHECK-ERRORS: vld1.8 {d0}, [r4:32], r6
61 @ CHECK-ERRORS: ^
62 @ CHECK: vld1.8 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x07]
63 @ CHECK-ERRORS: error: alignment must be 64 or omitted
64 @ CHECK-ERRORS: vld1.8 {d0}, [r4:128], r6
65 @ CHECK-ERRORS: ^
66 @ CHECK-ERRORS: error: alignment must be 64 or omitted
67 @ CHECK-ERRORS: vld1.8 {d0}, [r4:256], r6
68 @ CHECK-ERRORS: ^
69
70 vld1.8 {d0, d1}, [r4]
71 vld1.8 {d0, d1}, [r4:16]
72 vld1.8 {d0, d1}, [r4:32]
73 vld1.8 {d0, d1}, [r4:64]
74 vld1.8 {d0, d1}, [r4:128]
75 vld1.8 {d0, d1}, [r4:256]
76
77 @ CHECK: vld1.8 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x0f,0x0a]
78 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
79 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16]
80 @ CHECK-ERRORS: ^
81 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
82 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32]
83 @ CHECK-ERRORS: ^
84 @ CHECK: vld1.8 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x0a]
85 @ CHECK: vld1.8 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x0a]
86 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
87 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256]
88 @ CHECK-ERRORS: ^
89
90 vld1.8 {d0, d1}, [r4]!
91 vld1.8 {d0, d1}, [r4:16]!
92 vld1.8 {d0, d1}, [r4:32]!
93 vld1.8 {d0, d1}, [r4:64]!
94 vld1.8 {d0, d1}, [r4:128]!
95 vld1.8 {d0, d1}, [r4:256]!
96
97 @ CHECK: vld1.8 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x0a]
98 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
99 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16]!
100 @ CHECK-ERRORS: ^
101 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
102 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32]!
103 @ CHECK-ERRORS: ^
104 @ CHECK: vld1.8 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x0a]
105 @ CHECK: vld1.8 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x0a]
106 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
107 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256]!
108 @ CHECK-ERRORS: ^
109
110 vld1.8 {d0, d1}, [r4], r6
111 vld1.8 {d0, d1}, [r4:16], r6
112 vld1.8 {d0, d1}, [r4:32], r6
113 vld1.8 {d0, d1}, [r4:64], r6
114 vld1.8 {d0, d1}, [r4:128], r6
115 vld1.8 {d0, d1}, [r4:256], r6
116
117 @ CHECK: vld1.8 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x0a]
118 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
119 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16], r6
120 @ CHECK-ERRORS: ^
121 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
122 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32], r6
123 @ CHECK-ERRORS: ^
124 @ CHECK: vld1.8 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x0a]
125 @ CHECK: vld1.8 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x0a]
126 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
127 @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256], r6
128 @ CHECK-ERRORS: ^
129
130 vld1.8 {d0, d1, d2}, [r4]
131 vld1.8 {d0, d1, d2}, [r4:16]
132 vld1.8 {d0, d1, d2}, [r4:32]
133 vld1.8 {d0, d1, d2}, [r4:64]
134 vld1.8 {d0, d1, d2}, [r4:128]
135 vld1.8 {d0, d1, d2}, [r4:256]
136
137 @ CHECK: vld1.8 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x06]
138 @ CHECK-ERRORS: error: alignment must be 64 or omitted
139 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16]
140 @ CHECK-ERRORS: ^
141 @ CHECK-ERRORS: error: alignment must be 64 or omitted
142 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32]
143 @ CHECK-ERRORS: ^
144 @ CHECK: vld1.8 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x06]
145 @ CHECK-ERRORS: error: alignment must be 64 or omitted
146 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128]
147 @ CHECK-ERRORS: ^
148 @ CHECK-ERRORS: error: alignment must be 64 or omitted
149 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256]
150 @ CHECK-ERRORS: ^
151
152 vld1.8 {d0, d1, d2}, [r4]!
153 vld1.8 {d0, d1, d2}, [r4:16]!
154 vld1.8 {d0, d1, d2}, [r4:32]!
155 vld1.8 {d0, d1, d2}, [r4:64]!
156 vld1.8 {d0, d1, d2}, [r4:128]!
157 vld1.8 {d0, d1, d2}, [r4:256]!
158
159 @ CHECK: vld1.8 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x06]
160 @ CHECK-ERRORS: error: alignment must be 64 or omitted
161 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16]!
162 @ CHECK-ERRORS: ^
163 @ CHECK-ERRORS: error: alignment must be 64 or omitted
164 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32]!
165 @ CHECK-ERRORS: ^
166 @ CHECK: vld1.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x06]
167 @ CHECK-ERRORS: error: alignment must be 64 or omitted
168 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128]!
169 @ CHECK-ERRORS: ^
170 @ CHECK-ERRORS: error: alignment must be 64 or omitted
171 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256]!
172 @ CHECK-ERRORS: ^
173
174 vld1.8 {d0, d1, d2}, [r4], r6
175 vld1.8 {d0, d1, d2}, [r4:16], r6
176 vld1.8 {d0, d1, d2}, [r4:32], r6
177 vld1.8 {d0, d1, d2}, [r4:64], r6
178 vld1.8 {d0, d1, d2}, [r4:128], r6
179 vld1.8 {d0, d1, d2}, [r4:256], r6
180
181 @ CHECK: vld1.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x06]
182 @ CHECK-ERRORS: error: alignment must be 64 or omitted
183 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16], r6
184 @ CHECK-ERRORS: ^
185 @ CHECK-ERRORS: error: alignment must be 64 or omitted
186 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32], r6
187 @ CHECK-ERRORS: ^
188 @ CHECK: vld1.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x06]
189 @ CHECK-ERRORS: error: alignment must be 64 or omitted
190 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128], r6
191 @ CHECK-ERRORS: ^
192 @ CHECK-ERRORS: error: alignment must be 64 or omitted
193 @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256], r6
194 @ CHECK-ERRORS: ^
195
196 vld1.8 {d0, d1, d2, d3}, [r4]
197 vld1.8 {d0, d1, d2, d3}, [r4:16]
198 vld1.8 {d0, d1, d2, d3}, [r4:32]
199 vld1.8 {d0, d1, d2, d3}, [r4:64]
200 vld1.8 {d0, d1, d2, d3}, [r4:128]
201 vld1.8 {d0, d1, d2, d3}, [r4:256]
202
203 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x0f,0x02]
204 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
205 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16]
206 @ CHECK-ERRORS: ^
207 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
208 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32]
209 @ CHECK-ERRORS: ^
210 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x02]
211 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x02]
212 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x3f,0x02]
213
214 vld1.8 {d0, d1, d2, d3}, [r4]!
215 vld1.8 {d0, d1, d2, d3}, [r4:16]!
216 vld1.8 {d0, d1, d2, d3}, [r4:32]!
217 vld1.8 {d0, d1, d2, d3}, [r4:64]!
218 vld1.8 {d0, d1, d2, d3}, [r4:128]!
219 vld1.8 {d0, d1, d2, d3}, [r4:256]!
220
221 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x02]
222 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
223 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16]!
224 @ CHECK-ERRORS: ^
225 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
226 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32]!
227 @ CHECK-ERRORS: ^
228 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x02]
229 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x02]
230 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x3d,0x02]
231
232 vld1.8 {d0, d1, d2, d3}, [r4], r6
233 vld1.8 {d0, d1, d2, d3}, [r4:16], r6
234 vld1.8 {d0, d1, d2, d3}, [r4:32], r6
235 vld1.8 {d0, d1, d2, d3}, [r4:64], r6
236 vld1.8 {d0, d1, d2, d3}, [r4:128], r6
237 vld1.8 {d0, d1, d2, d3}, [r4:256], r6
238
239 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x02]
240 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
241 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16], r6
242 @ CHECK-ERRORS: ^
243 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
244 @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32], r6
245 @ CHECK-ERRORS: ^
246 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x02]
247 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x02]
248 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x36,0x02]
249
250 vld1.8 {d0[2]}, [r4]
251 vld1.8 {d0[2]}, [r4:16]
252 vld1.8 {d0[2]}, [r4:32]
253 vld1.8 {d0[2]}, [r4:64]
254 vld1.8 {d0[2]}, [r4:128]
255 vld1.8 {d0[2]}, [r4:256]
256
257 @ CHECK: vld1.8 {d0[2]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x00]
258 @ CHECK-ERRORS: error: alignment must be omitted
259 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16]
260 @ CHECK-ERRORS: ^
261 @ CHECK-ERRORS: error: alignment must be omitted
262 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32]
263 @ CHECK-ERRORS: ^
264 @ CHECK-ERRORS: error: alignment must be omitted
265 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64]
266 @ CHECK-ERRORS: ^
267 @ CHECK-ERRORS: error: alignment must be omitted
268 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128]
269 @ CHECK-ERRORS: ^
270 @ CHECK-ERRORS: error: alignment must be omitted
271 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256]
272 @ CHECK-ERRORS: ^
273
274 vld1.8 {d0[2]}, [r4]!
275 vld1.8 {d0[2]}, [r4:16]!
276 vld1.8 {d0[2]}, [r4:32]!
277 vld1.8 {d0[2]}, [r4:64]!
278 vld1.8 {d0[2]}, [r4:128]!
279 vld1.8 {d0[2]}, [r4:256]!
280
281 @ CHECK: vld1.8 {d0[2]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x00]
282 @ CHECK-ERRORS: error: alignment must be omitted
283 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16]!
284 @ CHECK-ERRORS: ^
285 @ CHECK-ERRORS: error: alignment must be omitted
286 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32]!
287 @ CHECK-ERRORS: ^
288 @ CHECK-ERRORS: error: alignment must be omitted
289 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64]!
290 @ CHECK-ERRORS: ^
291 @ CHECK-ERRORS: error: alignment must be omitted
292 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128]!
293 @ CHECK-ERRORS: ^
294 @ CHECK-ERRORS: error: alignment must be omitted
295 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256]!
296 @ CHECK-ERRORS: ^
297
298 vld1.8 {d0[2]}, [r4], r6
299 vld1.8 {d0[2]}, [r4:16], r6
300 vld1.8 {d0[2]}, [r4:32], r6
301 vld1.8 {d0[2]}, [r4:64], r6
302 vld1.8 {d0[2]}, [r4:128], r6
303 vld1.8 {d0[2]}, [r4:256], r6
304
305 @ CHECK: vld1.8 {d0[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x00]
306 @ CHECK-ERRORS: error: alignment must be omitted
307 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16], r6
308 @ CHECK-ERRORS: ^
309 @ CHECK-ERRORS: error: alignment must be omitted
310 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32], r6
311 @ CHECK-ERRORS: ^
312 @ CHECK-ERRORS: error: alignment must be omitted
313 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64], r6
314 @ CHECK-ERRORS: ^
315 @ CHECK-ERRORS: error: alignment must be omitted
316 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128], r6
317 @ CHECK-ERRORS: ^
318 @ CHECK-ERRORS: error: alignment must be omitted
319 @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256], r6
320 @ CHECK-ERRORS: ^
321
322 vld1.8 {d0[]}, [r4]
323 vld1.8 {d0[]}, [r4:16]
324 vld1.8 {d0[]}, [r4:32]
325 vld1.8 {d0[]}, [r4:64]
326 vld1.8 {d0[]}, [r4:128]
327 vld1.8 {d0[]}, [r4:256]
328
329 @ CHECK: vld1.8 {d0[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0c]
330 @ CHECK-ERRORS: error: alignment must be omitted
331 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16]
332 @ CHECK-ERRORS: ^
333 @ CHECK-ERRORS: error: alignment must be omitted
334 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32]
335 @ CHECK-ERRORS: ^
336 @ CHECK-ERRORS: error: alignment must be omitted
337 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64]
338 @ CHECK-ERRORS: ^
339 @ CHECK-ERRORS: error: alignment must be omitted
340 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128]
341 @ CHECK-ERRORS: ^
342 @ CHECK-ERRORS: error: alignment must be omitted
343 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256]
344 @ CHECK-ERRORS: ^
345
346 vld1.8 {d0[]}, [r4]!
347 vld1.8 {d0[]}, [r4:16]!
348 vld1.8 {d0[]}, [r4:32]!
349 vld1.8 {d0[]}, [r4:64]!
350 vld1.8 {d0[]}, [r4:128]!
351 vld1.8 {d0[]}, [r4:256]!
352
353 @ CHECK: vld1.8 {d0[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0c]
354 @ CHECK-ERRORS: error: alignment must be omitted
355 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16]!
356 @ CHECK-ERRORS: ^
357 @ CHECK-ERRORS: error: alignment must be omitted
358 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32]!
359 @ CHECK-ERRORS: ^
360 @ CHECK-ERRORS: error: alignment must be omitted
361 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64]!
362 @ CHECK-ERRORS: ^
363 @ CHECK-ERRORS: error: alignment must be omitted
364 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128]!
365 @ CHECK-ERRORS: ^
366 @ CHECK-ERRORS: error: alignment must be omitted
367 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256]!
368 @ CHECK-ERRORS: ^
369
370 vld1.8 {d0[]}, [r4], r6
371 vld1.8 {d0[]}, [r4:16], r6
372 vld1.8 {d0[]}, [r4:32], r6
373 vld1.8 {d0[]}, [r4:64], r6
374 vld1.8 {d0[]}, [r4:128], r6
375 vld1.8 {d0[]}, [r4:256], r6
376
377 @ CHECK: vld1.8 {d0[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0c]
378 @ CHECK-ERRORS: error: alignment must be omitted
379 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16], r6
380 @ CHECK-ERRORS: ^
381 @ CHECK-ERRORS: error: alignment must be omitted
382 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32], r6
383 @ CHECK-ERRORS: ^
384 @ CHECK-ERRORS: error: alignment must be omitted
385 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64], r6
386 @ CHECK-ERRORS: ^
387 @ CHECK-ERRORS: error: alignment must be omitted
388 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128], r6
389 @ CHECK-ERRORS: ^
390 @ CHECK-ERRORS: error: alignment must be omitted
391 @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256], r6
392 @ CHECK-ERRORS: ^
393
394 vld1.8 {d0[], d1[]}, [r4]
395 vld1.8 {d0[], d1[]}, [r4:16]
396 vld1.8 {d0[], d1[]}, [r4:32]
397 vld1.8 {d0[], d1[]}, [r4:64]
398 vld1.8 {d0[], d1[]}, [r4:128]
399 vld1.8 {d0[], d1[]}, [r4:256]
400
401 @ CHECK: vld1.8 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0c]
402 @ CHECK-ERRORS: error: alignment must be omitted
403 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16]
404 @ CHECK-ERRORS: ^
405 @ CHECK-ERRORS: error: alignment must be omitted
406 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32]
407 @ CHECK-ERRORS: ^
408 @ CHECK-ERRORS: error: alignment must be omitted
409 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64]
410 @ CHECK-ERRORS: ^
411 @ CHECK-ERRORS: error: alignment must be omitted
412 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128]
413 @ CHECK-ERRORS: ^
414 @ CHECK-ERRORS: error: alignment must be omitted
415 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256]
416 @ CHECK-ERRORS: ^
417
418 vld1.8 {d0[], d1[]}, [r4]!
419 vld1.8 {d0[], d1[]}, [r4:16]!
420 vld1.8 {d0[], d1[]}, [r4:32]!
421 vld1.8 {d0[], d1[]}, [r4:64]!
422 vld1.8 {d0[], d1[]}, [r4:128]!
423 vld1.8 {d0[], d1[]}, [r4:256]!
424
425 @ CHECK: vld1.8 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0c]
426 @ CHECK-ERRORS: error: alignment must be omitted
427 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16]!
428 @ CHECK-ERRORS: ^
429 @ CHECK-ERRORS: error: alignment must be omitted
430 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32]!
431 @ CHECK-ERRORS: ^
432 @ CHECK-ERRORS: error: alignment must be omitted
433 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64]!
434 @ CHECK-ERRORS: ^
435 @ CHECK-ERRORS: error: alignment must be omitted
436 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128]!
437 @ CHECK-ERRORS: ^
438 @ CHECK-ERRORS: error: alignment must be omitted
439 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256]!
440 @ CHECK-ERRORS: ^
441
442 vld1.8 {d0[], d1[]}, [r4], r6
443 vld1.8 {d0[], d1[]}, [r4:16], r6
444 vld1.8 {d0[], d1[]}, [r4:32], r6
445 vld1.8 {d0[], d1[]}, [r4:64], r6
446 vld1.8 {d0[], d1[]}, [r4:128], r6
447 vld1.8 {d0[], d1[]}, [r4:256], r6
448
449 @ CHECK: vld1.8 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0c]
450 @ CHECK-ERRORS: error: alignment must be omitted
451 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16], r6
452 @ CHECK-ERRORS: ^
453 @ CHECK-ERRORS: error: alignment must be omitted
454 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32], r6
455 @ CHECK-ERRORS: ^
456 @ CHECK-ERRORS: error: alignment must be omitted
457 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64], r6
458 @ CHECK-ERRORS: ^
459 @ CHECK-ERRORS: error: alignment must be omitted
460 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128], r6
461 @ CHECK-ERRORS: ^
462 @ CHECK-ERRORS: error: alignment must be omitted
463 @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256], r6
464 @ CHECK-ERRORS: ^
465
466 vld1.16 {d0}, [r4]
467 vld1.16 {d0}, [r4:16]
468 vld1.16 {d0}, [r4:32]
469 vld1.16 {d0}, [r4:64]
470 vld1.16 {d0}, [r4:128]
471 vld1.16 {d0}, [r4:256]
472
473 @ CHECK: vld1.16 {d0}, [r4] @ encoding: [0x24,0xf9,0x4f,0x07]
474 @ CHECK-ERRORS: error: alignment must be 64 or omitted
475 @ CHECK-ERRORS: vld1.16 {d0}, [r4:16]
476 @ CHECK-ERRORS: ^
477 @ CHECK-ERRORS: error: alignment must be 64 or omitted
478 @ CHECK-ERRORS: vld1.16 {d0}, [r4:32]
479 @ CHECK-ERRORS: ^
480 @ CHECK: vld1.16 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x07]
481 @ CHECK-ERRORS: error: alignment must be 64 or omitted
482 @ CHECK-ERRORS: vld1.16 {d0}, [r4:128]
483 @ CHECK-ERRORS: ^
484 @ CHECK-ERRORS: error: alignment must be 64 or omitted
485 @ CHECK-ERRORS: vld1.16 {d0}, [r4:256]
486 @ CHECK-ERRORS: ^
487
488 vld1.16 {d0}, [r4]!
489 vld1.16 {d0}, [r4:16]!
490 vld1.16 {d0}, [r4:32]!
491 vld1.16 {d0}, [r4:64]!
492 vld1.16 {d0}, [r4:128]!
493 vld1.16 {d0}, [r4:256]!
494
495 @ CHECK: vld1.16 {d0}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x07]
496 @ CHECK-ERRORS: error: alignment must be 64 or omitted
497 @ CHECK-ERRORS: vld1.16 {d0}, [r4:16]!
498 @ CHECK-ERRORS: ^
499 @ CHECK-ERRORS: error: alignment must be 64 or omitted
500 @ CHECK-ERRORS: vld1.16 {d0}, [r4:32]!
501 @ CHECK-ERRORS: ^
502 @ CHECK: vld1.16 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x07]
503 @ CHECK-ERRORS: error: alignment must be 64 or omitted
504 @ CHECK-ERRORS: vld1.16 {d0}, [r4:128]!
505 @ CHECK-ERRORS: ^
506 @ CHECK-ERRORS: error: alignment must be 64 or omitted
507 @ CHECK-ERRORS: vld1.16 {d0}, [r4:256]!
508 @ CHECK-ERRORS: ^
509
510 vld1.16 {d0}, [r4], r6
511 vld1.16 {d0}, [r4:16], r6
512 vld1.16 {d0}, [r4:32], r6
513 vld1.16 {d0}, [r4:64], r6
514 vld1.16 {d0}, [r4:128], r6
515 vld1.16 {d0}, [r4:256], r6
516
517 @ CHECK: vld1.16 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x07]
518 @ CHECK-ERRORS: error: alignment must be 64 or omitted
519 @ CHECK-ERRORS: vld1.16 {d0}, [r4:16], r6
520 @ CHECK-ERRORS: ^
521 @ CHECK-ERRORS: error: alignment must be 64 or omitted
522 @ CHECK-ERRORS: vld1.16 {d0}, [r4:32], r6
523 @ CHECK-ERRORS: ^
524 @ CHECK: vld1.16 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x07]
525 @ CHECK-ERRORS: error: alignment must be 64 or omitted
526 @ CHECK-ERRORS: vld1.16 {d0}, [r4:128], r6
527 @ CHECK-ERRORS: ^
528 @ CHECK-ERRORS: error: alignment must be 64 or omitted
529 @ CHECK-ERRORS: vld1.16 {d0}, [r4:256], r6
530 @ CHECK-ERRORS: ^
531
532 vld1.16 {d0, d1}, [r4]
533 vld1.16 {d0, d1}, [r4:16]
534 vld1.16 {d0, d1}, [r4:32]
535 vld1.16 {d0, d1}, [r4:64]
536 vld1.16 {d0, d1}, [r4:128]
537 vld1.16 {d0, d1}, [r4:256]
538
539 @ CHECK: vld1.16 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x4f,0x0a]
540 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
541 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16]
542 @ CHECK-ERRORS: ^
543 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
544 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32]
545 @ CHECK-ERRORS: ^
546 @ CHECK: vld1.16 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x0a]
547 @ CHECK: vld1.16 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x0a]
548 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
549 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256]
550 @ CHECK-ERRORS: ^
551
552 vld1.16 {d0, d1}, [r4]!
553 vld1.16 {d0, d1}, [r4:16]!
554 vld1.16 {d0, d1}, [r4:32]!
555 vld1.16 {d0, d1}, [r4:64]!
556 vld1.16 {d0, d1}, [r4:128]!
557 vld1.16 {d0, d1}, [r4:256]!
558
559 @ CHECK: vld1.16 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x0a]
560 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
561 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16]!
562 @ CHECK-ERRORS: ^
563 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
564 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32]!
565 @ CHECK-ERRORS: ^
566 @ CHECK: vld1.16 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x0a]
567 @ CHECK: vld1.16 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x0a]
568 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
569 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256]!
570 @ CHECK-ERRORS: ^
571
572 vld1.16 {d0, d1}, [r4], r6
573 vld1.16 {d0, d1}, [r4:16], r6
574 vld1.16 {d0, d1}, [r4:32], r6
575 vld1.16 {d0, d1}, [r4:64], r6
576 vld1.16 {d0, d1}, [r4:128], r6
577 vld1.16 {d0, d1}, [r4:256], r6
578
579 @ CHECK: vld1.16 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x0a]
580 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
581 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16], r6
582 @ CHECK-ERRORS: ^
583 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
584 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32], r6
585 @ CHECK-ERRORS: ^
586 @ CHECK: vld1.16 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x0a]
587 @ CHECK: vld1.16 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x0a]
588 @ CHECK-ERRORS: error: alignment must be 64, 128 or omitted
589 @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256], r6
590 @ CHECK-ERRORS: ^
591
592 vld1.16 {d0, d1, d2}, [r4]
593 vld1.16 {d0, d1, d2}, [r4:16]
594 vld1.16 {d0, d1, d2}, [r4:32]
595 vld1.16 {d0, d1, d2}, [r4:64]
596 vld1.16 {d0, d1, d2}, [r4:128]
597 vld1.16 {d0, d1, d2}, [r4:256]
598
599 @ CHECK: vld1.16 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x4f,0x06]
600 @ CHECK-ERRORS: error: alignment must be 64 or omitted
601 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16]
602 @ CHECK-ERRORS: ^
603 @ CHECK-ERRORS: error: alignment must be 64 or omitted
604 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32]
605 @ CHECK-ERRORS: ^
606 @ CHECK: vld1.16 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x06]
607 @ CHECK-ERRORS: error: alignment must be 64 or omitted
608 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128]
609 @ CHECK-ERRORS: ^
610 @ CHECK-ERRORS: error: alignment must be 64 or omitted
611 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256]
612 @ CHECK-ERRORS: ^
613
614 vld1.16 {d0, d1, d2}, [r4]!
615 vld1.16 {d0, d1, d2}, [r4:16]!
616 vld1.16 {d0, d1, d2}, [r4:32]!
617 vld1.16 {d0, d1, d2}, [r4:64]!
618 vld1.16 {d0, d1, d2}, [r4:128]!
619 vld1.16 {d0, d1, d2}, [r4:256]!
620
621 @ CHECK: vld1.16 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x06]
622 @ CHECK-ERRORS: error: alignment must be 64 or omitted
623 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16]!
624 @ CHECK-ERRORS: ^
625 @ CHECK-ERRORS: error: alignment must be 64 or omitted
626 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32]!
627 @ CHECK-ERRORS: ^
628 @ CHECK: vld1.16 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x06]
629 @ CHECK-ERRORS: error: alignment must be 64 or omitted
630 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128]!
631 @ CHECK-ERRORS: ^
632 @ CHECK-ERRORS: error: alignment must be 64 or omitted
633 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256]!
634 @ CHECK-ERRORS: ^
635
636 vld1.16 {d0, d1, d2}, [r4], r6
637 vld1.16 {d0, d1, d2}, [r4:16], r6
638 vld1.16 {d0, d1, d2}, [r4:32], r6
639 vld1.16 {d0, d1, d2}, [r4:64], r6
640 vld1.16 {d0, d1, d2}, [r4:128], r6
641 vld1.16 {d0, d1, d2}, [r4:256], r6
642
643 @ CHECK: vld1.16 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x06]
644 @ CHECK-ERRORS: error: alignment must be 64 or omitted
645 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16], r6
646 @ CHECK-ERRORS: ^
647 @ CHECK-ERRORS: error: alignment must be 64 or omitted
648 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32], r6
649 @ CHECK-ERRORS: ^
650 @ CHECK: vld1.16 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x06]
651 @ CHECK-ERRORS: error: alignment must be 64 or omitted
652 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128], r6
653 @ CHECK-ERRORS: ^
654 @ CHECK-ERRORS: error: alignment must be 64 or omitted
655 @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256], r6
656 @ CHECK-ERRORS: ^
657
658 vld1.16 {d0, d1, d2, d3}, [r4]
659 vld1.16 {d0, d1, d2, d3}, [r4:16]
660 vld1.16 {d0, d1, d2, d3}, [r4:32]
661 vld1.16 {d0, d1, d2, d3}, [r4:64]
662 vld1.16 {d0, d1, d2, d3}, [r4:128]
663 vld1.16 {d0, d1, d2, d3}, [r4:256]
664
665 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x4f,0x02]
666 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
667 @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16]
668 @ CHECK-ERRORS: ^
669 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
670 @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32]
671 @ CHECK-ERRORS: ^
672 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x02]
673 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x02]
674 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x7f,0x02]
675
676 vld1.16 {d0, d1, d2, d3}, [r4]!
677 vld1.16 {d0, d1, d2, d3}, [r4:16]!
678 vld1.16 {d0, d1, d2, d3}, [r4:32]!
679 vld1.16 {d0, d1, d2, d3}, [r4:64]!
680 vld1.16 {d0, d1, d2, d3}, [r4:128]!
681 vld1.16 {d0, d1, d2, d3}, [r4:256]!
682
683 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x02]
684 @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16]!
685 @ CHECK-ERRORS: ^
686 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
687 @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32]!
688 @ CHECK-ERRORS: ^
689 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x02]
690 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x02]
691 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x7d,0x02]
692
693 vld1.16 {d0, d1, d2, d3}, [r4], r6
694 vld1.16 {d0, d1, d2, d3}, [r4:16], r6
695 vld1.16 {d0, d1, d2, d3}, [r4:32], r6
696 vld1.16 {d0, d1, d2, d3}, [r4:64], r6
697 vld1.16 {d0, d1, d2, d3}, [r4:128], r6
698 vld1.16 {d0, d1, d2, d3}, [r4:256], r6
699
700 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x02]
701 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
702 @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16], r6
703 @ CHECK-ERRORS: ^
704 @ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted
705 @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32], r6
706 @ CHECK-ERRORS: ^
707 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x02]
708 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x02]
709 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x76,0x02]
710
711 vld1.16 {d0[2]}, [r4]
712 vld1.16 {d0[2]}, [r4:16]
713 vld1.16 {d0[2]}, [r4:32]
714 vld1.16 {d0[2]}, [r4:64]
715 vld1.16 {d0[2]}, [r4:128]
716 vld1.16 {d0[2]}, [r4:256]
717
718 @ CHECK: vld1.16 {d0[2]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x04]
719 @ CHECK: vld1.16 {d0[2]}, [r4:16] @ encoding: [0xa4,0xf9,0x9f,0x04]
720 @ CHECK-ERRORS: error: alignment must be 16 or omitted
721 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32]
722 @ CHECK-ERRORS: ^
723 @ CHECK-ERRORS: error: alignment must be 16 or omitted
724 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64]
725 @ CHECK-ERRORS: ^
726 @ CHECK-ERRORS: error: alignment must be 16 or omitted
727 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128]
728 @ CHECK-ERRORS: ^
729 @ CHECK-ERRORS: error: alignment must be 16 or omitted
730 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256]
731 @ CHECK-ERRORS: ^
732
733 vld1.16 {d0[2]}, [r4]!
734 vld1.16 {d0[2]}, [r4:16]!
735 vld1.16 {d0[2]}, [r4:32]!
736 vld1.16 {d0[2]}, [r4:64]!
737 vld1.16 {d0[2]}, [r4:128]!
738 vld1.16 {d0[2]}, [r4:256]!
739
740 @ CHECK: vld1.16 {d0[2]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x04]
741 @ CHECK: vld1.16 {d0[2]}, [r4:16]! @ encoding: [0xa4,0xf9,0x9d,0x04]
742 @ CHECK-ERRORS: error: alignment must be 16 or omitted
743 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32]!
744 @ CHECK-ERRORS: ^
745 @ CHECK-ERRORS: error: alignment must be 16 or omitted
746 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64]!
747 @ CHECK-ERRORS: ^
748 @ CHECK-ERRORS: error: alignment must be 16 or omitted
749 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128]!
750 @ CHECK-ERRORS: ^
751 @ CHECK-ERRORS: error: alignment must be 16 or omitted
752 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256]!
753 @ CHECK-ERRORS: ^
754
755 vld1.16 {d0[2]}, [r4], r6
756 vld1.16 {d0[2]}, [r4:16], r6
757 vld1.16 {d0[2]}, [r4:32], r6
758 vld1.16 {d0[2]}, [r4:64], r6
759 vld1.16 {d0[2]}, [r4:128], r6
760 vld1.16 {d0[2]}, [r4:256], r6
761
762 @ CHECK: vld1.16 {d0[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x04]
763 @ CHECK: vld1.16 {d0[2]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x96,0x04]
764 @ CHECK-ERRORS: error: alignment must be 16 or omitted
765 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32], r6
766 @ CHECK-ERRORS: ^
767 @ CHECK-ERRORS: error: alignment must be 16 or omitted
768 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64], r6
769 @ CHECK-ERRORS: ^
770 @ CHECK-ERRORS: error: alignment must be 16 or omitted
771 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128], r6
772 @ CHECK-ERRORS: ^
773 @ CHECK-ERRORS: error: alignment must be 16 or omitted
774 @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256], r6
775 @ CHECK-ERRORS: ^
776
777 vld1.16 {d0[]}, [r4]
778 vld1.16 {d0[]}, [r4:16]
779 vld1.16 {d0[]}, [r4:32]
780 vld1.16 {d0[]}, [r4:64]
781 vld1.16 {d0[]}, [r4:128]
782 vld1.16 {d0[]}, [r4:256]
783
784 @ CHECK: vld1.16 {d0[]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x0c]
785 @ CHECK: vld1.16 {d0[]}, [r4:16] @ encoding: [0xa4,0xf9,0x5f,0x0c]
786 @ CHECK-ERRORS: error: alignment must be 16 or omitted
787 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:32]
788 @ CHECK-ERRORS: ^
789 @ CHECK-ERRORS: error: alignment must be 16 or omitted
790 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:64]
791 @ CHECK-ERRORS: ^
792 @ CHECK-ERRORS: error: alignment must be 16 or omitted
793 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:128]
794 @ CHECK-ERRORS: ^
795 @ CHECK-ERRORS: error: alignment must be 16 or omitted
796 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:256]
797 @ CHECK-ERRORS: ^
798
799 vld1.16 {d0[]}, [r4]!
800 vld1.16 {d0[]}, [r4:16]!
801 vld1.16 {d0[]}, [r4:32]!
802 vld1.16 {d0[]}, [r4:64]!
803 vld1.16 {d0[]}, [r4:128]!
804 vld1.16 {d0[]}, [r4:256]!
805
806 @ CHECK: vld1.16 {d0[]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x0c]
807 @ CHECK: vld1.16 {d0[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x5d,0x0c]
808 @ CHECK-ERRORS: error: alignment must be 16 or omitted
809 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:32]!
810 @ CHECK-ERRORS: ^
811 @ CHECK-ERRORS: error: alignment must be 16 or omitted
812 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:64]!
813 @ CHECK-ERRORS: ^
814 @ CHECK-ERRORS: error: alignment must be 16 or omitted
815 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:128]!
816 @ CHECK-ERRORS: ^
817 @ CHECK-ERRORS: error: alignment must be 16 or omitted
818 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:256]!
819 @ CHECK-ERRORS: ^
820
821 vld1.16 {d0[]}, [r4], r6
822 vld1.16 {d0[]}, [r4:16], r6
823 vld1.16 {d0[]}, [r4:32], r6
824 vld1.16 {d0[]}, [r4:64], r6
825 vld1.16 {d0[]}, [r4:128], r6
826 vld1.16 {d0[]}, [r4:256], r6
827
828 @ CHECK: vld1.16 {d0[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x0c]
829 @ CHECK: vld1.16 {d0[]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x56,0x0c]
830 @ CHECK-ERRORS: error: alignment must be 16 or omitted
831 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:32], r6
832 @ CHECK-ERRORS: ^
833 @ CHECK-ERRORS: error: alignment must be 16 or omitted
834 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:64], r6
835 @ CHECK-ERRORS: ^
836 @ CHECK-ERRORS: error: alignment must be 16 or omitted
837 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:128], r6
838 @ CHECK-ERRORS: ^
839 @ CHECK-ERRORS: error: alignment must be 16 or omitted
840 @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:256], r6
841 @ CHECK-ERRORS: ^
842
843 vld1.16 {d0[], d1[]}, [r4]
844 vld1.16 {d0[], d1[]}, [r4:16]
845 vld1.16 {d0[], d1[]}, [r4:32]
846 vld1.16 {d0[], d1[]}, [r4:64]
847 vld1.16 {d0[], d1[]}, [r4:128]
848 vld1.16 {d0[], d1[]}, [r4:256]
849
850 @ CHECK: vld1.16 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x0c]
851 @ CHECK: vld1.16 {d0[], d1[]}, [r4:16] @ encoding: [0xa4,0xf9,0x7f,0x0c]
852 @ CHECK-ERRORS: error: alignment must be 16 or omitted
853 @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:32]
854 @ CHECK-ERRORS: ^
855 @ CHECK-ERRORS: error: alignment must be 16 or omitted
856 @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:64]
857 @ CHECK-ERRORS: ^
858 @ CHECK-ERRORS: error: alignment must be 16 or omitted
859 @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:128]
860 @ CHECK-ERRORS: ^
861 @ CHECK-ERRORS: error: alignment must be 16 or omitted
862 @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:256]
863 @ CHECK-ERRORS: ^
864
865 vld1.16 {d0[], d1[]}, [r4]!
866 vld1.16 {d0[], d1[]}, [r4:16]!
867 vld1.16 {d0[], d1[]}, [r4:32]!
868 vld1.16 {d0[], d1[]}, [r4:64]!
869 vld1.16 {d0[], d1[]}, [r4:128]!
870 vld1.16 {d0[], d1[]}, [r4:256]!
871
872 @ CHECK: vld1.16 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x0c]
873 @ CHECK: vld1.16 {d0[], d1[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x7d,0x0c]
874 @ CHECK-ERRORS: error: alignment must be 16 or omitted
875 @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:32]!
876 @ CHECK-ERRORS: ^
877 @ CHECK-ERRORS: error: alignment must be 16 or omitted
878 @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:64]!
879 @ CHECK-ERRORS: ^
880 @ CHECK-ERRORS: error: alignment must be 16 or omitted
881 @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:128]!
882 @ CHECK-ERRORS: ^
883 @ CHECK-ERRORS: error: alignment must be 16 or omitted
884 @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:256]!
885 @ CHECK-ERRORS: ^
886
887 vld1.16 {d0[], d1[]}, [r4], r6