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[ARM] Rename HW div feature to HW div Thumb. NFCI. The hardware div feature refers only to Thumb, but because of its name it is tempting to use it to check for hardware division in general, which may cause problems in ARM mode. See https://reviews.llvm.org/D32005. This patch adds "Thumb" to its name, to make its scope clear. One notable place where I haven't made the change is in the feature flag (used with -mattr), which is still hwdiv. Changing it would also require changes in a lot of tests, including clang tests, and it doesn't seem like it's worth the effort. Differential Revision: https://reviews.llvm.org/D32160 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300827 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 3 years ago
12 changed file(s) with 111 addition(s) and 102 deletion(s). Raw diff Collapse all Expand all
7777 FK_NEON, ARM::AEK_DSP)
7878 ARM_ARCH("armv7ve", AK_ARMV7VE, "7VE", "v7ve", ARMBuildAttrs::CPUArch::v7,
7979 FK_NEON, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
80 ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP))
80 ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP))
8181 ARM_ARCH("armv7-r", AK_ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7,
82 FK_NONE, (ARM::AEK_HWDIV | ARM::AEK_DSP))
82 FK_NONE, (ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP))
8383 ARM_ARCH("armv7-m", AK_ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7,
84 FK_NONE, ARM::AEK_HWDIV)
84 FK_NONE, ARM::AEK_HWDIVTHUMB)
8585 ARM_ARCH("armv7e-m", AK_ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M,
86 FK_NONE, (ARM::AEK_HWDIV | ARM::AEK_DSP))
86 FK_NONE, (ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP))
8787 ARM_ARCH("armv8-a", AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8_A,
8888 FK_CRYPTO_NEON_FP_ARMV8,
8989 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
90 ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC))
90 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC))
9191 ARM_ARCH("armv8.1-a", AK_ARMV8_1A, "8.1-A", "v8.1a",
9292 ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
9393 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
94 ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC))
94 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC))
9595 ARM_ARCH("armv8.2-a", AK_ARMV8_2A, "8.2-A", "v8.2a",
9696 ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
9797 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
98 ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
98 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
9999 ARM_ARCH("armv8-r", AK_ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R,
100100 FK_NEON_FP_ARMV8,
101 (ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIV |
101 (ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
102102 ARM::AEK_DSP | ARM::AEK_CRC))
103103 ARM_ARCH("armv8-m.base", AK_ARMV8MBaseline, "8-M.Baseline", "v8m.base",
104 ARMBuildAttrs::CPUArch::v8_M_Base, FK_NONE, ARM::AEK_HWDIV)
104 ARMBuildAttrs::CPUArch::v8_M_Base, FK_NONE, ARM::AEK_HWDIVTHUMB)
105105 ARM_ARCH("armv8-m.main", AK_ARMV8MMainline, "8-M.Mainline", "v8m.main",
106 ARMBuildAttrs::CPUArch::v8_M_Main, FK_FPV5_D16, ARM::AEK_HWDIV)
106 ARMBuildAttrs::CPUArch::v8_M_Main, FK_FPV5_D16, ARM::AEK_HWDIVTHUMB)
107107 // Non-standard Arch names.
108108 ARM_ARCH("iwmmxt", AK_IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE,
109109 FK_NONE, ARM::AEK_NONE)
127127 ARM_ARCH_EXT_NAME("crypto", ARM::AEK_CRYPTO, "+crypto","-crypto")
128128 ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
129129 ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, nullptr, nullptr)
130 ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIV), nullptr, nullptr)
130 ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), nullptr, nullptr)
131131 ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, nullptr, nullptr)
132132 ARM_ARCH_EXT_NAME("simd", ARM::AEK_SIMD, nullptr, nullptr)
133133 ARM_ARCH_EXT_NAME("sec", ARM::AEK_SEC, nullptr, nullptr)
146146 #endif
147147 ARM_HW_DIV_NAME("invalid", ARM::AEK_INVALID)
148148 ARM_HW_DIV_NAME("none", ARM::AEK_NONE)
149 ARM_HW_DIV_NAME("thumb", ARM::AEK_HWDIV)
149 ARM_HW_DIV_NAME("thumb", ARM::AEK_HWDIVTHUMB)
150150 ARM_HW_DIV_NAME("arm", ARM::AEK_HWDIVARM)
151 ARM_HW_DIV_NAME("arm,thumb", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIV))
151 ARM_HW_DIV_NAME("arm,thumb", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB))
152152 #undef ARM_HW_DIV_NAME
153153
154154 #ifndef ARM_CPU_NAME
204204 (ARM::AEK_SEC | ARM::AEK_MP))
205205 ARM_CPU_NAME("cortex-a7", AK_ARMV7A, FK_NEON_VFPV4, false,
206206 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
207 ARM::AEK_HWDIV))
207 ARM::AEK_HWDIVTHUMB))
208208 ARM_CPU_NAME("cortex-a8", AK_ARMV7A, FK_NEON, true, ARM::AEK_SEC)
209209 ARM_CPU_NAME("cortex-a9", AK_ARMV7A, FK_NEON_FP16, false, (ARM::AEK_SEC | ARM::AEK_MP))
210210 ARM_CPU_NAME("cortex-a12", AK_ARMV7A, FK_NEON_VFPV4, false,
211211 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
212 ARM::AEK_HWDIV))
212 ARM::AEK_HWDIVTHUMB))
213213 ARM_CPU_NAME("cortex-a15", AK_ARMV7A, FK_NEON_VFPV4, false,
214214 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
215 ARM::AEK_HWDIV))
215 ARM::AEK_HWDIVTHUMB))
216216 ARM_CPU_NAME("cortex-a17", AK_ARMV7A, FK_NEON_VFPV4, false,
217217 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
218 ARM::AEK_HWDIV))
218 ARM::AEK_HWDIVTHUMB))
219219 ARM_CPU_NAME("krait", AK_ARMV7A, FK_NEON_VFPV4, false,
220 (ARM::AEK_HWDIVARM | ARM::AEK_HWDIV))
220 (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB))
221221 ARM_CPU_NAME("cortex-r4", AK_ARMV7R, FK_NONE, true, ARM::AEK_NONE)
222222 ARM_CPU_NAME("cortex-r4f", AK_ARMV7R, FK_VFPV3_D16, false, ARM::AEK_NONE)
223223 ARM_CPU_NAME("cortex-r5", AK_ARMV7R, FK_VFPV3_D16, false,
248248 ARM_CPU_NAME("iwmmxt", AK_IWMMXT, FK_NONE, true, ARM::AEK_NONE)
249249 ARM_CPU_NAME("xscale", AK_XSCALE, FK_NONE, true, ARM::AEK_NONE)
250250 ARM_CPU_NAME("swift", AK_ARMV7S, FK_NEON_VFPV4, true,
251 (ARM::AEK_HWDIVARM | ARM::AEK_HWDIV))
251 (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB))
252252 // Invalid CPU
253253 ARM_CPU_NAME("invalid", AK_INVALID, FK_INVALID, true, ARM::AEK_INVALID)
254254 #undef ARM_CPU_NAME
7474 AEK_CRC = 0x2,
7575 AEK_CRYPTO = 0x4,
7676 AEK_FP = 0x8,
77 AEK_HWDIV = 0x10,
77 AEK_HWDIVTHUMB = 0x10,
7878 AEK_HWDIVARM = 0x20,
7979 AEK_MP = 0x40,
8080 AEK_SIMD = 0x80,
209209 else
210210 Features.push_back("-hwdiv-arm");
211211
212 if (HWDivKind & ARM::AEK_HWDIV)
212 if (HWDivKind & ARM::AEK_HWDIVTHUMB)
213213 Features.push_back("+hwdiv");
214214 else
215215 Features.push_back("-hwdiv");
6666 [FeatureFPARMv8]>;
6767 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
6868 "Restrict FP to 16 double registers">;
69 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
70 "Enable divide instructions">;
69 def FeatureHWDivThumb : SubtargetFeature<"hwdiv", "HasHardwareDivideInThumb",
70 "true",
71 "Enable divide instructions in Thumb">;
7172 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
7273 "HasHardwareDivideInARM", "true",
7374 "Enable divide instructions in ARM mode">;
224225 def FeatureVirtualization : SubtargetFeature<"virtualization",
225226 "HasVirtualization", "true",
226227 "Supports Virtualization extension",
227 [FeatureHWDiv, FeatureHWDivARM]>;
228 [FeatureHWDivThumb, FeatureHWDivARM]>;
228229
229230 // M-series ISA
230231 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
432433 def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
433434 FeatureDB,
434435 FeatureDSP,
435 FeatureHWDiv,
436 FeatureHWDivThumb,
436437 FeatureRClass]>;
437438
438439 def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
439440 FeatureThumb2,
440441 FeatureNoARM,
441442 FeatureDB,
442 FeatureHWDiv,
443 FeatureHWDivThumb,
443444 FeatureMClass]>;
444445
445446 def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
446447 FeatureThumb2,
447448 FeatureNoARM,
448449 FeatureDB,
449 FeatureHWDiv,
450 FeatureHWDivThumb,
450451 FeatureMClass,
451452 FeatureDSP]>;
452453
501502 [HasV8MBaselineOps,
502503 FeatureNoARM,
503504 FeatureDB,
504 FeatureHWDiv,
505 FeatureHWDivThumb,
505506 FeatureV7Clrex,
506507 Feature8MSecExt,
507508 FeatureAcquireRelease,
511512 [HasV8MMainlineOps,
512513 FeatureNoARM,
513514 FeatureDB,
514 FeatureHWDiv,
515 FeatureHWDivThumb,
515516 Feature8MSecExt,
516517 FeatureAcquireRelease,
517518 FeatureMClass]>;
677678 FeatureFP16,
678679 FeatureAvoidPartialCPSR,
679680 FeatureVFP4,
680 FeatureHWDiv,
681 FeatureHWDivThumb,
681682 FeatureHWDivARM]>;
682683
683684 def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
685686 FeatureNEONForFP,
686687 FeatureVFP4,
687688 FeatureMP,
688 FeatureHWDiv,
689 FeatureHWDivThumb,
689690 FeatureHWDivARM,
690691 FeatureAvoidPartialCPSR,
691692 FeatureAvoidMOVsShOp,
767768 FeatureVFPOnlySP]>;
768769
769770 def : ProcNoItin<"cortex-a32", [ARMv8a,
770 FeatureHWDiv,
771 FeatureHWDivThumb,
771772 FeatureHWDivARM,
772773 FeatureCrypto,
773774 FeatureCRC]>;
774775
775776 def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
776 FeatureHWDiv,
777 FeatureHWDivThumb,
777778 FeatureHWDivARM,
778779 FeatureCrypto,
779780 FeatureCRC]>;
780781
781782 def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
782 FeatureHWDiv,
783 FeatureHWDivThumb,
783784 FeatureHWDivARM,
784785 FeatureCrypto,
785786 FeatureCRC,
786787 FeatureFPAO]>;
787788
788789 def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
789 FeatureHWDiv,
790 FeatureHWDivThumb,
790791 FeatureHWDivARM,
791792 FeatureCrypto,
792793 FeatureCRC,
793794 FeatureFPAO]>;
794795
795796 def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
796 FeatureHWDiv,
797 FeatureHWDivThumb,
797798 FeatureHWDivARM,
798799 FeatureCrypto,
799800 FeatureCRC]>;
800801
801802 def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
802 FeatureHWDiv,
803 FeatureHWDivThumb,
803804 FeatureHWDivARM,
804805 FeatureCrypto,
805806 FeatureCRC]>;
810811 FeatureNEONForFP,
811812 FeatureVFP4,
812813 FeatureMP,
813 FeatureHWDiv,
814 FeatureHWDivThumb,
814815 FeatureHWDivARM,
815816 FeatureAvoidPartialCPSR,
816817 FeatureAvoidMOVsShOp,
819820 FeatureZCZeroing]>;
820821
821822 def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
822 FeatureHWDiv,
823 FeatureHWDivThumb,
823824 FeatureHWDivARM,
824825 FeatureCrypto,
825826 FeatureCRC]>;
826827
827828 def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynosM1,
828 FeatureHWDiv,
829 FeatureHWDivThumb,
829830 FeatureHWDivARM,
830831 FeatureCrypto,
831832 FeatureCRC]>;
832833
833834 def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynosM1,
834 FeatureHWDiv,
835 FeatureHWDivThumb,
835836 FeatureHWDivARM,
836837 FeatureCrypto,
837838 FeatureCRC]>;
838839
839840 def : ProcNoItin<"kryo", [ARMv8a, ProcKryo,
840 FeatureHWDiv,
841 FeatureHWDivThumb,
841842 FeatureHWDivARM,
842843 FeatureCrypto,
843844 FeatureCRC]>;
17011701 // If we have integer div support we should have selected this automagically.
17021702 // In case we have a real miss go ahead and return false and we'll pick
17031703 // it up later.
1704 if (Subtarget->hasDivide()) return false;
1704 if (Subtarget->hasDivideInThumbMode())
1705 return false;
17051706
17061707 // Otherwise emit a libcall.
17071708 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
851851 if (!Subtarget->hasV6Ops())
852852 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
853853
854 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivide()
854 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
855855 : Subtarget->hasDivideInARMMode();
856856 if (!hasDivide) {
857857 // These are expanded into libcalls if the cpu doesn't have HW divider.
859859 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
860860 }
861861
862 if (Subtarget->isTargetWindows() && !Subtarget->hasDivide()) {
862 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
863863 setOperationAction(ISD::SDIV, MVT::i32, Custom);
864864 setOperationAction(ISD::UDIV, MVT::i32, Custom);
865865
1304213042 // rem = a - b * div
1304313043 // return {div, rem}
1304413044 // This should be lowered into UDIV/SDIV + MLS later on.
13045 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivide()
13045 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1304613046 : Subtarget->hasDivideInARMMode();
1304713047 if (hasDivide && Op->getValueType(0).isSimple() &&
1304813048 Op->getSimpleValueType(0) == MVT::i32) {
258258 AssemblerPredicate<"FeatureFP16","half-float conversions">;
259259 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
260260 AssemblerPredicate<"FeatureFullFP16","full half-float">;
261 def HasDivide : Predicate<"Subtarget->hasDivide()">,
262 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
261 def HasDivideInThumb : Predicate<"Subtarget->hasDivideInThumbMode()">,
262 AssemblerPredicate<"FeatureHWDivThumb", "divide in THUMB">;
263263 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
264264 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
265265 def HasDSP : Predicate<"Subtarget->hasDSP()">,
27962796 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
27972797 "sdiv", "\t$Rd, $Rn, $Rm",
27982798 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2799 Requires<[HasDivide, IsThumb, HasV8MBaseline]>,
2799 Requires<[HasDivideInThumb, IsThumb, HasV8MBaseline]>,
28002800 Sched<[WriteDIV]> {
28012801 let Inst{31-27} = 0b11111;
28022802 let Inst{26-21} = 0b011100;
28082808 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
28092809 "udiv", "\t$Rd, $Rn, $Rm",
28102810 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2811 Requires<[HasDivide, IsThumb, HasV8MBaseline]>,
2811 Requires<[HasDivideInThumb, IsThumb, HasV8MBaseline]>,
28122812 Sched<[WriteDIV]> {
28132813 let Inst{31-27} = 0b11111;
28142814 let Inst{26-21} = 0b011101;
207207 /// FP registers for VFPv3.
208208 bool HasD16 = false;
209209
210 /// HasHardwareDivide - True if subtarget supports [su]div
211 bool HasHardwareDivide = false;
210 /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
211 bool HasHardwareDivideInThumb = false;
212212
213213 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
214214 bool HasHardwareDivideInARM = false;
506506 return hasNEON() && UseNEONForSinglePrecisionFP;
507507 }
508508
509 bool hasDivide() const { return HasHardwareDivide; }
509 bool hasDivideInThumbMode() const { return HasHardwareDivideInThumb; }
510510 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
511511 bool hasDataBarrier() const { return HasDataBarrier; }
512512 bool hasV7Clrex() const { return HasV7Clrex; }
1019510195 { ARM::AEK_CRYPTO, Feature_HasV8,
1019610196 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
1019710197 { ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} },
10198 { (ARM::AEK_HWDIV | ARM::AEK_HWDIVARM), Feature_HasV7 | Feature_IsNotMClass,
10199 {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} },
10198 { (ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM), Feature_HasV7 | Feature_IsNotMClass,
10199 {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM} },
1020010200 { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
1020110201 { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
1020210202 { ARM::AEK_SEC, Feature_HasV6K, {ARM::FeatureTrustZone} },
130130 emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
131131 // We consider krait as a "cortex-a9" + hwdiv CPU
132132 // Enable hwdiv through ".arch_extension idiv"
133 if (STI.hasFeature(ARM::FeatureHWDiv) ||
133 if (STI.hasFeature(ARM::FeatureHWDivThumb) ||
134134 STI.hasFeature(ARM::FeatureHWDivARM))
135 emitArchExtension(ARM::AEK_HWDIV | ARM::AEK_HWDIVARM);
135 emitArchExtension(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM);
136136 } else {
137137 emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
138138 }
148148 EXPECT_TRUE(testARMCPU("cortex-a5", "armv7-a", "neon-vfpv4",
149149 ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_DSP, "7-A"));
150150 EXPECT_TRUE(testARMCPU("cortex-a7", "armv7-a", "neon-vfpv4",
151 ARM::AEK_HWDIV | ARM::AEK_HWDIVARM | ARM::AEK_MP |
152 ARM::AEK_SEC | ARM::AEK_VIRT | ARM::AEK_DSP,
151 ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM | ARM::AEK_MP |
152 ARM::AEK_SEC | ARM::AEK_VIRT | ARM::AEK_DSP,
153153 "7-A"));
154154 EXPECT_TRUE(testARMCPU("cortex-a8", "armv7-a", "neon",
155155 ARM::AEK_SEC | ARM::AEK_DSP, "7-A"));
157157 ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_DSP, "7-A"));
158158 EXPECT_TRUE(testARMCPU("cortex-a12", "armv7-a", "neon-vfpv4",
159159 ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
160 ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP,
160 ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
161 ARM::AEK_DSP,
161162 "7-A"));
162163 EXPECT_TRUE(testARMCPU("cortex-a15", "armv7-a", "neon-vfpv4",
163164 ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
164 ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP,
165 ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
166 ARM::AEK_DSP,
165167 "7-A"));
166168 EXPECT_TRUE(testARMCPU("cortex-a17", "armv7-a", "neon-vfpv4",
167169 ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
168 ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP,
170 ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
171 ARM::AEK_DSP,
169172 "7-A"));
170173 EXPECT_TRUE(testARMCPU("krait", "armv7-a", "neon-vfpv4",
171 ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP,
174 ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
172175 "7-A"));
173176 EXPECT_TRUE(testARMCPU("cortex-r4", "armv7-r", "none",
174 ARM::AEK_HWDIV | ARM::AEK_DSP, "7-R"));
177 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "7-R"));
175178 EXPECT_TRUE(testARMCPU("cortex-r4f", "armv7-r", "vfpv3-d16",
176 ARM::AEK_HWDIV | ARM::AEK_DSP, "7-R"));
179 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "7-R"));
177180 EXPECT_TRUE(testARMCPU("cortex-r5", "armv7-r", "vfpv3-d16",
178 ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIV |
179 ARM::AEK_DSP, "7-R"));
181 ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
182 ARM::AEK_DSP,
183 "7-R"));
180184 EXPECT_TRUE(testARMCPU("cortex-r7", "armv7-r", "vfpv3-d16-fp16",
181 ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIV |
182 ARM::AEK_DSP, "7-R"));
185 ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
186 ARM::AEK_DSP,
187 "7-R"));
183188 EXPECT_TRUE(testARMCPU("cortex-r8", "armv7-r", "vfpv3-d16-fp16",
184 ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIV |
185 ARM::AEK_DSP, "7-R"));
189 ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
190 ARM::AEK_DSP,
191 "7-R"));
186192 EXPECT_TRUE(testARMCPU("cortex-r52", "armv8-r", "neon-fp-armv8",
187193 ARM::AEK_CRC | ARM::AEK_MP | ARM::AEK_VIRT |
188 ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP,
194 ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
195 ARM::AEK_DSP,
189196 "8-R"));
190 EXPECT_TRUE(testARMCPU("sc300", "armv7-m", "none",
191 ARM::AEK_HWDIV, "7-M"));
192 EXPECT_TRUE(testARMCPU("cortex-m3", "armv7-m", "none",
193 ARM::AEK_HWDIV, "7-M"));
197 EXPECT_TRUE(
198 testARMCPU("sc300", "armv7-m", "none", ARM::AEK_HWDIVTHUMB, "7-M"));
199 EXPECT_TRUE(
200 testARMCPU("cortex-m3", "armv7-m", "none", ARM::AEK_HWDIVTHUMB, "7-M"));
194201 EXPECT_TRUE(testARMCPU("cortex-m4", "armv7e-m", "fpv4-sp-d16",
195 ARM::AEK_HWDIV | ARM::AEK_DSP, "7E-M"));
202 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "7E-M"));
196203 EXPECT_TRUE(testARMCPU("cortex-m7", "armv7e-m", "fpv5-d16",
197 ARM::AEK_HWDIV | ARM::AEK_DSP, "7E-M"));
204 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "7E-M"));
198205 EXPECT_TRUE(testARMCPU("cortex-a32", "armv8-a", "crypto-neon-fp-armv8",
199206 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
200 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
201 ARM::AEK_HWDIV | ARM::AEK_DSP,
207 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
208 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
202209 "8-A"));
203210 EXPECT_TRUE(testARMCPU("cortex-a35", "armv8-a", "crypto-neon-fp-armv8",
204211 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
205 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
206 ARM::AEK_HWDIV | ARM::AEK_DSP,
212 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
213 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
207214 "8-A"));
208215 EXPECT_TRUE(testARMCPU("cortex-a53", "armv8-a", "crypto-neon-fp-armv8",
209216 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
210 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
211 ARM::AEK_HWDIV | ARM::AEK_DSP,
217 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
218 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
212219 "8-A"));
213220 EXPECT_TRUE(testARMCPU("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
214221 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
215 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
216 ARM::AEK_HWDIV | ARM::AEK_DSP,
222 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
223 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
217224 "8-A"));
218225 EXPECT_TRUE(testARMCPU("cortex-a72", "armv8-a", "crypto-neon-fp-armv8",
219226 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
220 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
221 ARM::AEK_HWDIV | ARM::AEK_DSP,
227 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
228 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
222229 "8-A"));
223230 EXPECT_TRUE(testARMCPU("cortex-a73", "armv8-a", "crypto-neon-fp-armv8",
224231 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
225 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
226 ARM::AEK_HWDIV | ARM::AEK_DSP,
232 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
233 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
227234 "8-A"));
228235 EXPECT_TRUE(testARMCPU("cyclone", "armv8-a", "crypto-neon-fp-armv8",
229236 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
230 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
231 ARM::AEK_HWDIV | ARM::AEK_DSP,
237 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
238 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
232239 "8-A"));
233240 EXPECT_TRUE(testARMCPU("exynos-m1", "armv8-a", "crypto-neon-fp-armv8",
234241 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
235 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
236 ARM::AEK_HWDIV | ARM::AEK_DSP,
242 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
243 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
237244 "8-A"));
238245 EXPECT_TRUE(testARMCPU("exynos-m2", "armv8-a", "crypto-neon-fp-armv8",
239246 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
240 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
241 ARM::AEK_HWDIV | ARM::AEK_DSP,
247 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
248 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
242249 "8-A"));
243250 EXPECT_TRUE(testARMCPU("exynos-m3", "armv8-a", "crypto-neon-fp-armv8",
244251 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
245 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
246 ARM::AEK_HWDIV | ARM::AEK_DSP,
252 ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
253 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
247254 "8-A"));
248255 EXPECT_TRUE(testARMCPU("cortex-m23", "armv8-m.base", "none",
249 ARM::AEK_HWDIV, "8-M.Baseline"));
256 ARM::AEK_HWDIVTHUMB, "8-M.Baseline"));
250257 EXPECT_TRUE(testARMCPU("cortex-m33", "armv8-m.main", "fpv5-sp-d16",
251 ARM::AEK_HWDIV | ARM::AEK_DSP, "8-M.Mainline"));
258 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "8-M.Mainline"));
252259 EXPECT_TRUE(testARMCPU("iwmmxt", "iwmmxt", "none",
253260 ARM::AEK_NONE, "iwmmxt"));
254261 EXPECT_TRUE(testARMCPU("xscale", "xscale", "none",
255262 ARM::AEK_NONE, "xscale"));
256263 EXPECT_TRUE(testARMCPU("swift", "armv7s", "neon-vfpv4",
257 ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP,
264 ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
258265 "7-S"));
259266 }
260267
453460 TEST(TargetParserTest, ARMExtensionFeatures) {
454461 std::vector Features;
455462 unsigned Extensions = ARM::AEK_CRC | ARM::AEK_CRYPTO | ARM::AEK_DSP |
456 ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_MP |
463 ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_MP |
457464 ARM::AEK_SEC | ARM::AEK_VIRT | ARM::AEK_RAS;
458465
459466 for (unsigned i = 0; i <= Extensions; i++)