llvm.org GIT mirror llvm / 6a0fffd
[Sparc] Add support for inline assembly constraints which specify registers by their aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199786 91177308-0d34-0410-b5e6-96231b3b80d8 Venkatraman Govindaraju 6 years ago
2 changed file(s) with 30 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
29962996 case 'r':
29972997 return std::make_pair(0U, &SP::IntRegsRegClass);
29982998 }
2999 } else if (!Constraint.empty() && Constraint.size() <= 5
3000 && Constraint[0] == '{' && *(Constraint.end()-1) == '}') {
3001 // constraint = '{r}'
3002 // Remove the braces from around the name.
3003 StringRef name(Constraint.data()+1, Constraint.size()-2);
3004 // Handle register aliases:
3005 // r0-r7 -> g0-g7
3006 // r8-r15 -> o0-o7
3007 // r16-r23 -> l0-l7
3008 // r24-r31 -> i0-i7
3009 uint64_t intVal = 0;
3010 if (name.substr(0, 1).equals("r")
3011 && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
3012 const char regTypes[] = { 'g', 'o', 'l', 'i' };
3013 char regType = regTypes[intVal/8];
3014 char regIdx = '0' + (intVal % 8);
3015 char tmp[] = { '{', regType, regIdx, '}', 0 };
3016 std::string newConstraint = std::string(tmp);
3017 return TargetLowering::getRegForInlineAsmConstraint(newConstraint, VT);
3018 }
29993019 }
30003020
30013021 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3232 %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 10000)
3333 ret i32 %0
3434 }
35
36 ; CHECK-LABEL: test_constraint_reg
37 ; CHECK: ldda [%o1] 43, %g2
38 ; CHECK: ldda [%o1] 43, %g3
39 define void @test_constraint_reg(i32 %s, i32* %ptr) {
40 entry:
41 %0 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={r2},r,n"(i32* %ptr, i32 43)
42 %1 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={g3},r,n"(i32* %ptr, i32 43)
43 ret void
44 }