llvm.org GIT mirror llvm / 69e42db
Split TargetLowering into a CodeGen and a SelectionDAG part. This fixes some of the cycles between libCodeGen and libSelectionDAG. It's still a complete mess but as long as the edges consist of virtual call it doesn't cause breakage. BasicTTI did static calls and thus broke some build configurations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172246 91177308-0d34-0410-b5e6-96231b3b80d8 Benjamin Kramer 7 years ago
12 changed file(s) with 2096 addition(s) and 1773 deletion(s). Raw diff Collapse all Expand all
2424 class MachineFunctionPass;
2525 class PassInfo;
2626 class PassManagerBase;
27 class TargetLoweringBase;
2728 class TargetLowering;
2829 class TargetRegisterClass;
2930 class raw_ostream;
283284 ///
284285 /// This pass implements the target transform info analysis using the target
285286 /// independent information available to the LLVM code generator.
286 ImmutablePass *createBasicTargetTransformInfoPass(const TargetLowering *TLI);
287 ImmutablePass *
288 createBasicTargetTransformInfoPass(const TargetLoweringBase *TLI);
287289
288290 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
289291 /// work well with unreachable basic blocks (what live ranges make sense for a
480482
481483 /// createStackProtectorPass - This pass adds stack protectors to functions.
482484 ///
483 FunctionPass *createStackProtectorPass(const TargetLowering *tli);
485 FunctionPass *createStackProtectorPass(const TargetLoweringBase *tli);
484486
485487 /// createMachineVerifierPass - This pass verifies cenerated machine code
486488 /// instructions for correctness.
494496 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
495497 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
496498 ///
497 FunctionPass *createSjLjEHPreparePass(const TargetLowering *tli);
499 FunctionPass *createSjLjEHPreparePass(const TargetLoweringBase *tli);
498500
499501 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
500502 /// slots relative to one another and allocates base registers to access them
6767 };
6868 }
6969
70 //===----------------------------------------------------------------------===//
71 /// TargetLowering - This class defines information used to lower LLVM code to
72 /// legal SelectionDAG operators that the target instruction selector can accept
73 /// natively.
74 ///
75 /// This class also defines callbacks that targets must implement to lower
76 /// target-specific constructs to SelectionDAG operators.
77 ///
78 class TargetLowering {
79 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
80 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
70 /// TargetLoweringBase - This base class for TargetLowering contains the
71 /// SelectionDAG-independent parts that can be used from the rest of CodeGen.
72 class TargetLoweringBase {
73 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
74 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
75
8176 public:
8277 /// LegalizeAction - This enum indicates whether operations are valid for a
8378 /// target, and if not, what action should be used to make them valid.
135130 }
136131
137132 /// NOTE: The constructor takes ownership of TLOF.
138 explicit TargetLowering(const TargetMachine &TM,
139 const TargetLoweringObjectFile *TLOF);
140 virtual ~TargetLowering();
133 explicit TargetLoweringBase(const TargetMachine &TM,
134 const TargetLoweringObjectFile *TLOF);
135 virtual ~TargetLoweringBase();
141136
142137 const TargetMachine &getTargetMachine() const { return TM; }
143138 const DataLayout *getDataLayout() const { return TD; }
828823 return InsertFencesForAtomic;
829824 }
830825
831 /// getPreIndexedAddressParts - returns true by value, base pointer and
832 /// offset pointer and addressing mode by reference if the node's address
833 /// can be legally represented as pre-indexed load / store address.
834 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
835 SDValue &/*Offset*/,
836 ISD::MemIndexedMode &/*AM*/,
837 SelectionDAG &/*DAG*/) const {
838 return false;
839 }
840
841 /// getPostIndexedAddressParts - returns true by value, base pointer and
842 /// offset pointer and addressing mode by reference if this node can be
843 /// combined with a load / store to form a post-indexed load / store.
844 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
845 SDValue &/*Base*/, SDValue &/*Offset*/,
846 ISD::MemIndexedMode &/*AM*/,
847 SelectionDAG &/*DAG*/) const {
848 return false;
849 }
850
851 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
852 /// current function. The returned value is a member of the
853 /// MachineJumpTableInfo::JTEntryKind enum.
854 virtual unsigned getJumpTableEncoding() const;
855
856 virtual const MCExpr *
857 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
858 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
859 MCContext &/*Ctx*/) const {
860 llvm_unreachable("Need to implement this hook if target has custom JTIs");
861 }
862
863 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
864 /// jumptable.
865 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
866 SelectionDAG &DAG) const;
867
868 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
869 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
870 /// MCExpr.
871 virtual const MCExpr *
872 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
873 unsigned JTI, MCContext &Ctx) const;
874
875 /// isOffsetFoldingLegal - Return true if folding a constant offset
876 /// with the given GlobalAddress is legal. It is frequently not legal in
877 /// PIC relocation models.
878 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
879
880826 /// getStackCookieLocation - Return true if the target stores stack
881827 /// protector cookies at a fixed offset in some non-standard address
882828 /// space, and populates the address space and offset as
903849 std::pair getTypeLegalizationCost(Type *Ty) const;
904850
905851 /// @}
906
907 //===--------------------------------------------------------------------===//
908 // TargetLowering Optimization Methods
909 //
910
911 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
912 /// SDValues for returning information from TargetLowering to its clients
913 /// that want to combine
914 struct TargetLoweringOpt {
915 SelectionDAG &DAG;
916 bool LegalTys;
917 bool LegalOps;
918 SDValue Old;
919 SDValue New;
920
921 explicit TargetLoweringOpt(SelectionDAG &InDAG,
922 bool LT, bool LO) :
923 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
924
925 bool LegalTypes() const { return LegalTys; }
926 bool LegalOperations() const { return LegalOps; }
927
928 bool CombineTo(SDValue O, SDValue N) {
929 Old = O;
930 New = N;
931 return true;
932 }
933
934 /// ShrinkDemandedConstant - Check to see if the specified operand of the
935 /// specified instruction is a constant integer. If so, check to see if
936 /// there are any bits set in the constant that are not demanded. If so,
937 /// shrink the constant and return true.
938 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
939
940 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
941 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
942 /// cast, but it could be generalized for targets with other types of
943 /// implicit widening casts.
944 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
945 DebugLoc dl);
946 };
947
948 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
949 /// DemandedMask bits of the result of Op are ever used downstream. If we can
950 /// use this information to simplify Op, create a new simplified DAG node and
951 /// return true, returning the original and new nodes in Old and New.
952 /// Otherwise, analyze the expression and return a mask of KnownOne and
953 /// KnownZero bits for the expression (used to simplify the caller).
954 /// The KnownZero/One bits may only be accurate for those bits in the
955 /// DemandedMask.
956 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
957 APInt &KnownZero, APInt &KnownOne,
958 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
959
960 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
961 /// Mask are known to be either zero or one and return them in the
962 /// KnownZero/KnownOne bitsets.
963 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
964 APInt &KnownZero,
965 APInt &KnownOne,
966 const SelectionDAG &DAG,
967 unsigned Depth = 0) const;
968
969 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
970 /// targets that want to expose additional information about sign bits to the
971 /// DAG Combiner.
972 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
973 unsigned Depth = 0) const;
974
975 struct DAGCombinerInfo {
976 void *DC; // The DAG Combiner object.
977 CombineLevel Level;
978 bool CalledByLegalizer;
979 public:
980 SelectionDAG &DAG;
981
982 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
983 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
984
985 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
986 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
987 bool isAfterLegalizeVectorOps() const {
988 return Level == AfterLegalizeDAG;
989 }
990 CombineLevel getDAGCombineLevel() { return Level; }
991 bool isCalledByLegalizer() const { return CalledByLegalizer; }
992
993 void AddToWorklist(SDNode *N);
994 void RemoveFromWorklist(SDNode *N);
995 SDValue CombineTo(SDNode *N, const std::vector &To,
996 bool AddTo = true);
997 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
998 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
999
1000 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
1001 };
1002
1003 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1004 /// and cc. If it is unable to simplify it, return a null SDValue.
1005 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1006 ISD::CondCode Cond, bool foldBooleans,
1007 DAGCombinerInfo &DCI, DebugLoc dl) const;
1008
1009 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
1010 /// node is a GlobalAddress + offset.
1011 virtual bool
1012 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
1013
1014 /// PerformDAGCombine - This method will be invoked for all target nodes and
1015 /// for any target-independent nodes that the target has registered with
1016 /// invoke it for.
1017 ///
1018 /// The semantics are as follows:
1019 /// Return Value:
1020 /// SDValue.Val == 0 - No change was made
1021 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
1022 /// otherwise - N should be replaced by the returned Operand.
1023 ///
1024 /// In addition, methods provided by DAGCombinerInfo may be used to perform
1025 /// more complex transformations.
1026 ///
1027 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
1028
1029 /// isTypeDesirableForOp - Return true if the target has native support for
1030 /// the specified value type and it is 'desirable' to use the type for the
1031 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
1032 /// instruction encodings are longer and some i16 instructions are slow.
1033 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
1034 // By default, assume all legal types are desirable.
1035 return isTypeLegal(VT);
1036 }
1037
1038 /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner
1039 /// to transform a floating point op of specified opcode to a equivalent op of
1040 /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM.
1041 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
1042 EVT /*VT*/) const {
1043 return false;
1044 }
1045
1046 /// IsDesirableToPromoteOp - This method query the target whether it is
1047 /// beneficial for dag combiner to promote the specified node. If true, it
1048 /// should return the desired promotion type by reference.
1049 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
1050 return false;
1051 }
1052852
1053853 //===--------------------------------------------------------------------===//
1054854 // TargetLowering Configuration Methods - These methods should be invoked by
13011101
13021102 public:
13031103 //===--------------------------------------------------------------------===//
1104 // Addressing mode description hooks (used by LSR etc).
1105 //
1106
1107 /// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the
1108 /// same BB as Load/Store instructions reading the address. This allows as
1109 /// much computation as possible to be done in the address mode for that
1110 /// operand. This hook lets targets also pass back when this should be done
1111 /// on intrinsics which load/store.
1112 virtual bool GetAddrModeArguments(IntrinsicInst *I,
1113 SmallVectorImpl &Ops,
1114 Type *&AccessTy) const {
1115 return false;
1116 }
1117
1118 /// AddrMode - This represents an addressing mode of:
1119 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1120 /// If BaseGV is null, there is no BaseGV.
1121 /// If BaseOffs is zero, there is no base offset.
1122 /// If HasBaseReg is false, there is no base register.
1123 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1124 /// no scale.
1125 ///
1126 struct AddrMode {
1127 GlobalValue *BaseGV;
1128 int64_t BaseOffs;
1129 bool HasBaseReg;
1130 int64_t Scale;
1131 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1132 };
1133
1134 /// isLegalAddressingMode - Return true if the addressing mode represented by
1135 /// AM is legal for this target, for a load/store of the specified type.
1136 /// The type may be VoidTy, in which case only return true if the addressing
1137 /// mode is legal for a load/store of any legal type.
1138 /// TODO: Handle pre/postinc as well.
1139 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1140
1141 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1142 /// icmp immediate, that is the target has icmp instructions which can compare
1143 /// a register against the immediate without having to materialize the
1144 /// immediate into a register.
1145 virtual bool isLegalICmpImmediate(int64_t) const {
1146 return true;
1147 }
1148
1149 /// isLegalAddImmediate - Return true if the specified immediate is legal
1150 /// add immediate, that is the target has add instructions which can add
1151 /// a register with the immediate without having to materialize the
1152 /// immediate into a register.
1153 virtual bool isLegalAddImmediate(int64_t) const {
1154 return true;
1155 }
1156
1157 /// isTruncateFree - Return true if it's free to truncate a value of
1158 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1159 /// register EAX to i16 by referencing its sub-register AX.
1160 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1161 return false;
1162 }
1163
1164 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1165 return false;
1166 }
1167
1168 /// isZExtFree - Return true if any actual instruction that defines a
1169 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1170 /// register. This does not necessarily include registers defined in
1171 /// unknown ways, such as incoming arguments, or copies from unknown
1172 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1173 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1174 /// all instructions that define 32-bit values implicit zero-extend the
1175 /// result out to 64 bits.
1176 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1177 return false;
1178 }
1179
1180 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1181 return false;
1182 }
1183
1184 /// isZExtFree - Return true if zero-extending the specific node Val to type
1185 /// VT2 is free (either because it's implicitly zero-extended such as ARM
1186 /// ldrb / ldrh or because it's folded such as X86 zero-extending loads).
1187 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1188 return isZExtFree(Val.getValueType(), VT2);
1189 }
1190
1191 /// isFNegFree - Return true if an fneg operation is free to the point where
1192 /// it is never worthwhile to replace it with a bitwise operation.
1193 virtual bool isFNegFree(EVT) const {
1194 return false;
1195 }
1196
1197 /// isFAbsFree - Return true if an fneg operation is free to the point where
1198 /// it is never worthwhile to replace it with a bitwise operation.
1199 virtual bool isFAbsFree(EVT) const {
1200 return false;
1201 }
1202
1203 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
1204 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
1205 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
1206 /// is expanded to mul + add.
1207 virtual bool isFMAFasterThanMulAndAdd(EVT) const {
1208 return false;
1209 }
1210
1211 /// isNarrowingProfitable - Return true if it's profitable to narrow
1212 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1213 /// from i32 to i8 but not from i32 to i16.
1214 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1215 return false;
1216 }
1217
1218 //===--------------------------------------------------------------------===//
1219 // Runtime Library hooks
1220 //
1221
1222 /// setLibcallName - Rename the default libcall routine name for the specified
1223 /// libcall.
1224 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1225 LibcallRoutineNames[Call] = Name;
1226 }
1227
1228 /// getLibcallName - Get the libcall routine name for the specified libcall.
1229 ///
1230 const char *getLibcallName(RTLIB::Libcall Call) const {
1231 return LibcallRoutineNames[Call];
1232 }
1233
1234 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1235 /// result of the comparison libcall against zero.
1236 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1237 CmpLibcallCCs[Call] = CC;
1238 }
1239
1240 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1241 /// the comparison libcall against zero.
1242 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1243 return CmpLibcallCCs[Call];
1244 }
1245
1246 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1247 /// specified libcall.
1248 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1249 LibcallCallingConvs[Call] = CC;
1250 }
1251
1252 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1253 /// specified libcall.
1254 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1255 return LibcallCallingConvs[Call];
1256 }
1257
1258 private:
1259 const TargetMachine &TM;
1260 const DataLayout *TD;
1261 const TargetLoweringObjectFile &TLOF;
1262
1263 /// PointerTy - The type to use for pointers for the default address space,
1264 /// usually i32 or i64.
1265 ///
1266 MVT PointerTy;
1267
1268 /// IsLittleEndian - True if this is a little endian target.
1269 ///
1270 bool IsLittleEndian;
1271
1272 /// SelectIsExpensive - Tells the code generator not to expand operations
1273 /// into sequences that use the select operations if possible.
1274 bool SelectIsExpensive;
1275
1276 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1277 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1278 /// a real cost model is in place. If we ever optimize for size, this will be
1279 /// set to true unconditionally.
1280 bool IntDivIsCheap;
1281
1282 /// BypassSlowDivMap - Tells the code generator to bypass slow divide or
1283 /// remainder instructions. For example, BypassSlowDivWidths[32,8] tells the
1284 /// code generator to bypass 32-bit integer div/rem with an 8-bit unsigned
1285 /// integer div/rem when the operands are positive and less than 256.
1286 DenseMap BypassSlowDivWidths;
1287
1288 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1289 /// srl/add/sra for a signed divide by power of two, and let the target handle
1290 /// it.
1291 bool Pow2DivIsCheap;
1292
1293 /// JumpIsExpensive - Tells the code generator that it shouldn't generate
1294 /// extra flow control instructions and should attempt to combine flow
1295 /// control instructions via predication.
1296 bool JumpIsExpensive;
1297
1298 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1299 /// llvm.setjmp. Defaults to false.
1300 bool UseUnderscoreSetJmp;
1301
1302 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1303 /// llvm.longjmp. Defaults to false.
1304 bool UseUnderscoreLongJmp;
1305
1306 /// SupportJumpTables - Whether the target can generate code for jumptables.
1307 /// If it's not true, then each jumptable must be lowered into if-then-else's.
1308 bool SupportJumpTables;
1309
1310 /// MinimumJumpTableEntries - Number of blocks threshold to use jump tables.
1311 int MinimumJumpTableEntries;
1312
1313 /// BooleanContents - Information about the contents of the high-bits in
1314 /// boolean values held in a type wider than i1. See getBooleanContents.
1315 BooleanContent BooleanContents;
1316 /// BooleanVectorContents - Information about the contents of the high-bits
1317 /// in boolean vector values when the element type is wider than i1. See
1318 /// getBooleanContents.
1319 BooleanContent BooleanVectorContents;
1320
1321 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1322 /// total cycles or lowest register usage.
1323 Sched::Preference SchedPreferenceInfo;
1324
1325 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1326 unsigned JumpBufSize;
1327
1328 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1329 /// buffers
1330 unsigned JumpBufAlignment;
1331
1332 /// MinStackArgumentAlignment - The minimum alignment that any argument
1333 /// on the stack needs to have.
1334 ///
1335 unsigned MinStackArgumentAlignment;
1336
1337 /// MinFunctionAlignment - The minimum function alignment (used when
1338 /// optimizing for size, and to prevent explicitly provided alignment
1339 /// from leading to incorrect code).
1340 ///
1341 unsigned MinFunctionAlignment;
1342
1343 /// PrefFunctionAlignment - The preferred function alignment (used when
1344 /// alignment unspecified and optimizing for speed).
1345 ///
1346 unsigned PrefFunctionAlignment;
1347
1348 /// PrefLoopAlignment - The preferred loop alignment.
1349 ///
1350 unsigned PrefLoopAlignment;
1351
1352 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should
1353 /// be folded into the enclosed atomic intrinsic instruction by the
1354 /// combiner.
1355 bool ShouldFoldAtomicFences;
1356
1357 /// InsertFencesForAtomic - Whether the DAG builder should automatically
1358 /// insert fences and reduce ordering for atomics. (This will be set for
1359 /// for most architectures with weak memory ordering.)
1360 bool InsertFencesForAtomic;
1361
1362 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1363 /// specifies the register that llvm.savestack/llvm.restorestack should save
1364 /// and restore.
1365 unsigned StackPointerRegisterToSaveRestore;
1366
1367 /// ExceptionPointerRegister - If set to a physical register, this specifies
1368 /// the register that receives the exception address on entry to a landing
1369 /// pad.
1370 unsigned ExceptionPointerRegister;
1371
1372 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1373 /// the register that receives the exception typeid on entry to a landing
1374 /// pad.
1375 unsigned ExceptionSelectorRegister;
1376
1377 /// RegClassForVT - This indicates the default register class to use for
1378 /// each ValueType the target supports natively.
1379 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1380 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1381 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1382
1383 /// RepRegClassForVT - This indicates the "representative" register class to
1384 /// use for each ValueType the target supports natively. This information is
1385 /// used by the scheduler to track register pressure. By default, the
1386 /// representative register class is the largest legal super-reg register
1387 /// class of the register class of the specified type. e.g. On x86, i8, i16,
1388 /// and i32's representative class would be GR32.
1389 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1390
1391 /// RepRegClassCostForVT - This indicates the "cost" of the "representative"
1392 /// register class for each ValueType. The cost is used by the scheduler to
1393 /// approximate register pressure.
1394 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1395
1396 /// TransformToType - For any value types we are promoting or expanding, this
1397 /// contains the value type that we are changing to. For Expanded types, this
1398 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1399 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1400 /// by the system, this holds the same type (e.g. i32 -> i32).
1401 MVT TransformToType[MVT::LAST_VALUETYPE];
1402
1403 /// OpActions - For each operation and each value type, keep a LegalizeAction
1404 /// that indicates how instruction selection should deal with the operation.
1405 /// Most operations are Legal (aka, supported natively by the target), but
1406 /// operations that are not should be described. Note that operations on
1407 /// non-legal value types are not described here.
1408 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1409
1410 /// LoadExtActions - For each load extension type and each value type,
1411 /// keep a LegalizeAction that indicates how instruction selection should deal
1412 /// with a load of a specific value type and extension type.
1413 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1414
1415 /// TruncStoreActions - For each value type pair keep a LegalizeAction that
1416 /// indicates whether a truncating store of a specific value type and
1417 /// truncating type is legal.
1418 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1419
1420 /// IndexedModeActions - For each indexed mode and each value type,
1421 /// keep a pair of LegalizeAction that indicates how instruction
1422 /// selection should deal with the load / store. The first dimension is the
1423 /// value_type for the reference. The second dimension represents the various
1424 /// modes for load store.
1425 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1426
1427 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1428 /// LegalizeAction that indicates how instruction selection should
1429 /// deal with the condition code.
1430 /// Because each CC action takes up 2 bits, we need to have the array size
1431 /// be large enough to fit all of the value types. This can be done by
1432 /// dividing the MVT::LAST_VALUETYPE by 32 and adding one.
1433 uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) + 1];
1434
1435 ValueTypeActionImpl ValueTypeActions;
1436
1437 public:
1438 LegalizeKind
1439 getTypeConversion(LLVMContext &Context, EVT VT) const {
1440 // If this is a simple type, use the ComputeRegisterProp mechanism.
1441 if (VT.isSimple()) {
1442 MVT SVT = VT.getSimpleVT();
1443 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1444 MVT NVT = TransformToType[SVT.SimpleTy];
1445 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1446
1447 assert(
1448 (LA == TypeLegal ||
1449 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1450 && "Promote may not follow Expand or Promote");
1451
1452 if (LA == TypeSplitVector)
1453 return LegalizeKind(LA, EVT::getVectorVT(Context,
1454 SVT.getVectorElementType(),
1455 SVT.getVectorNumElements()/2));
1456 if (LA == TypeScalarizeVector)
1457 return LegalizeKind(LA, SVT.getVectorElementType());
1458 return LegalizeKind(LA, NVT);
1459 }
1460
1461 // Handle Extended Scalar Types.
1462 if (!VT.isVector()) {
1463 assert(VT.isInteger() && "Float types must be simple");
1464 unsigned BitSize = VT.getSizeInBits();
1465 // First promote to a power-of-two size, then expand if necessary.
1466 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1467 EVT NVT = VT.getRoundIntegerType(Context);
1468 assert(NVT != VT && "Unable to round integer VT");
1469 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1470 // Avoid multi-step promotion.
1471 if (NextStep.first == TypePromoteInteger) return NextStep;
1472 // Return rounded integer type.
1473 return LegalizeKind(TypePromoteInteger, NVT);
1474 }
1475
1476 return LegalizeKind(TypeExpandInteger,
1477 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1478 }
1479
1480 // Handle vector types.
1481 unsigned NumElts = VT.getVectorNumElements();
1482 EVT EltVT = VT.getVectorElementType();
1483
1484 // Vectors with only one element are always scalarized.
1485 if (NumElts == 1)
1486 return LegalizeKind(TypeScalarizeVector, EltVT);
1487
1488 // Try to widen vector elements until a legal type is found.
1489 if (EltVT.isInteger()) {
1490 // Vectors with a number of elements that is not a power of two are always
1491 // widened, for example <3 x float> -> <4 x float>.
1492 if (!VT.isPow2VectorType()) {
1493 NumElts = (unsigned)NextPowerOf2(NumElts);
1494 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1495 return LegalizeKind(TypeWidenVector, NVT);
1496 }
1497
1498 // Examine the element type.
1499 LegalizeKind LK = getTypeConversion(Context, EltVT);
1500
1501 // If type is to be expanded, split the vector.
1502 // <4 x i140> -> <2 x i140>
1503 if (LK.first == TypeExpandInteger)
1504 return LegalizeKind(TypeSplitVector,
1505 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1506
1507 // Promote the integer element types until a legal vector type is found
1508 // or until the element integer type is too big. If a legal type was not
1509 // found, fallback to the usual mechanism of widening/splitting the
1510 // vector.
1511 while (1) {
1512 // Increase the bitwidth of the element to the next pow-of-two
1513 // (which is greater than 8 bits).
1514 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1515 ).getRoundIntegerType(Context);
1516
1517 // Stop trying when getting a non-simple element type.
1518 // Note that vector elements may be greater than legal vector element
1519 // types. Example: X86 XMM registers hold 64bit element on 32bit systems.
1520 if (!EltVT.isSimple()) break;
1521
1522 // Build a new vector type and check if it is legal.
1523 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1524 // Found a legal promoted vector type.
1525 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1526 return LegalizeKind(TypePromoteInteger,
1527 EVT::getVectorVT(Context, EltVT, NumElts));
1528 }
1529 }
1530
1531 // Try to widen the vector until a legal type is found.
1532 // If there is no wider legal type, split the vector.
1533 while (1) {
1534 // Round up to the next power of 2.
1535 NumElts = (unsigned)NextPowerOf2(NumElts);
1536
1537 // If there is no simple vector type with this many elements then there
1538 // cannot be a larger legal vector type. Note that this assumes that
1539 // there are no skipped intermediate vector types in the simple types.
1540 if (!EltVT.isSimple()) break;
1541 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1542 if (LargerVector == MVT()) break;
1543
1544 // If this type is legal then widen the vector.
1545 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1546 return LegalizeKind(TypeWidenVector, LargerVector);
1547 }
1548
1549 // Widen odd vectors to next power of two.
1550 if (!VT.isPow2VectorType()) {
1551 EVT NVT = VT.getPow2VectorType(Context);
1552 return LegalizeKind(TypeWidenVector, NVT);
1553 }
1554
1555 // Vectors with illegal element types are expanded.
1556 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1557 return LegalizeKind(TypeSplitVector, NVT);
1558 }
1559
1560 private:
1561 std::vector > AvailableRegClasses;
1562
1563 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1564 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1565 /// which sets a bit in this array.
1566 unsigned char
1567 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1568
1569 /// PromoteToType - For operations that must be promoted to a specific type,
1570 /// this holds the destination type. This map should be sparse, so don't hold
1571 /// it as an array.
1572 ///
1573 /// Targets add entries to this map with AddPromotedToType(..), clients access
1574 /// this with getTypeToPromoteTo(..).
1575 std::map, MVT::SimpleValueType>
1576 PromoteToType;
1577
1578 /// LibcallRoutineNames - Stores the name each libcall.
1579 ///
1580 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1581
1582 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1583 /// of each of the comparison libcall against zero.
1584 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1585
1586 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1587 /// libcall.
1588 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1589
1590 protected:
1591 /// When lowering \@llvm.memset this field specifies the maximum number of
1592 /// store operations that may be substituted for the call to memset. Targets
1593 /// must set this value based on the cost threshold for that target. Targets
1594 /// should assume that the memset will be done using as many of the largest
1595 /// store operations first, followed by smaller ones, if necessary, per
1596 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1597 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1598 /// store. This only applies to setting a constant array of a constant size.
1599 /// @brief Specify maximum number of store instructions per memset call.
1600 unsigned maxStoresPerMemset;
1601
1602 /// Maximum number of stores operations that may be substituted for the call
1603 /// to memset, used for functions with OptSize attribute.
1604 unsigned maxStoresPerMemsetOptSize;
1605
1606 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1607 /// store operations that may be substituted for a call to memcpy. Targets
1608 /// must set this value based on the cost threshold for that target. Targets
1609 /// should assume that the memcpy will be done using as many of the largest
1610 /// store operations first, followed by smaller ones, if necessary, per
1611 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1612 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1613 /// and one 1-byte store. This only applies to copying a constant array of
1614 /// constant size.
1615 /// @brief Specify maximum bytes of store instructions per memcpy call.
1616 unsigned maxStoresPerMemcpy;
1617
1618 /// Maximum number of store operations that may be substituted for a call
1619 /// to memcpy, used for functions with OptSize attribute.
1620 unsigned maxStoresPerMemcpyOptSize;
1621
1622 /// When lowering \@llvm.memmove this field specifies the maximum number of
1623 /// store instructions that may be substituted for a call to memmove. Targets
1624 /// must set this value based on the cost threshold for that target. Targets
1625 /// should assume that the memmove will be done using as many of the largest
1626 /// store operations first, followed by smaller ones, if necessary, per
1627 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1628 /// with 8-bit alignment would result in nine 1-byte stores. This only
1629 /// applies to copying a constant array of constant size.
1630 /// @brief Specify maximum bytes of store instructions per memmove call.
1631 unsigned maxStoresPerMemmove;
1632
1633 /// Maximum number of store instructions that may be substituted for a call
1634 /// to memmove, used for functions with OpSize attribute.
1635 unsigned maxStoresPerMemmoveOptSize;
1636
1637 /// This field specifies whether the target can benefit from code placement
1638 /// optimization.
1639 bool benefitFromCodePlacementOpt;
1640
1641 /// predictableSelectIsExpensive - Tells the code generator that select is
1642 /// more expensive than a branch if the branch is usually predicted right.
1643 bool predictableSelectIsExpensive;
1644
1645 protected:
1646 /// isLegalRC - Return true if the value types that can be represented by the
1647 /// specified register class are all legal.
1648 bool isLegalRC(const TargetRegisterClass *RC) const;
1649 };
1650
1651 //===----------------------------------------------------------------------===//
1652 /// TargetLowering - This class defines information used to lower LLVM code to
1653 /// legal SelectionDAG operators that the target instruction selector can accept
1654 /// natively.
1655 ///
1656 /// This class also defines callbacks that targets must implement to lower
1657 /// target-specific constructs to SelectionDAG operators.
1658 ///
1659 class TargetLowering : public TargetLoweringBase {
1660 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
1661 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
1662
1663 public:
1664 /// NOTE: The constructor takes ownership of TLOF.
1665 explicit TargetLowering(const TargetMachine &TM,
1666 const TargetLoweringObjectFile *TLOF);
1667
1668 /// getPreIndexedAddressParts - returns true by value, base pointer and
1669 /// offset pointer and addressing mode by reference if the node's address
1670 /// can be legally represented as pre-indexed load / store address.
1671 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1672 SDValue &/*Offset*/,
1673 ISD::MemIndexedMode &/*AM*/,
1674 SelectionDAG &/*DAG*/) const {
1675 return false;
1676 }
1677
1678 /// getPostIndexedAddressParts - returns true by value, base pointer and
1679 /// offset pointer and addressing mode by reference if this node can be
1680 /// combined with a load / store to form a post-indexed load / store.
1681 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
1682 SDValue &/*Base*/, SDValue &/*Offset*/,
1683 ISD::MemIndexedMode &/*AM*/,
1684 SelectionDAG &/*DAG*/) const {
1685 return false;
1686 }
1687
1688 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1689 /// current function. The returned value is a member of the
1690 /// MachineJumpTableInfo::JTEntryKind enum.
1691 virtual unsigned getJumpTableEncoding() const;
1692
1693 virtual const MCExpr *
1694 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
1695 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
1696 MCContext &/*Ctx*/) const {
1697 llvm_unreachable("Need to implement this hook if target has custom JTIs");
1698 }
1699
1700 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1701 /// jumptable.
1702 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
1703 SelectionDAG &DAG) const;
1704
1705 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1706 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1707 /// MCExpr.
1708 virtual const MCExpr *
1709 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1710 unsigned JTI, MCContext &Ctx) const;
1711
1712 /// isOffsetFoldingLegal - Return true if folding a constant offset
1713 /// with the given GlobalAddress is legal. It is frequently not legal in
1714 /// PIC relocation models.
1715 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
1716
1717 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
1718 SDValue &Chain) const;
1719
1720 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
1721 SDValue &NewLHS, SDValue &NewRHS,
1722 ISD::CondCode &CCCode, DebugLoc DL) const;
1723
1724 SDValue makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT,
1725 const SDValue *Ops, unsigned NumOps,
1726 bool isSigned, DebugLoc dl) const;
1727
1728 //===--------------------------------------------------------------------===//
1729 // TargetLowering Optimization Methods
1730 //
1731
1732 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
1733 /// SDValues for returning information from TargetLowering to its clients
1734 /// that want to combine
1735 struct TargetLoweringOpt {
1736 SelectionDAG &DAG;
1737 bool LegalTys;
1738 bool LegalOps;
1739 SDValue Old;
1740 SDValue New;
1741
1742 explicit TargetLoweringOpt(SelectionDAG &InDAG,
1743 bool LT, bool LO) :
1744 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
1745
1746 bool LegalTypes() const { return LegalTys; }
1747 bool LegalOperations() const { return LegalOps; }
1748
1749 bool CombineTo(SDValue O, SDValue N) {
1750 Old = O;
1751 New = N;
1752 return true;
1753 }
1754
1755 /// ShrinkDemandedConstant - Check to see if the specified operand of the
1756 /// specified instruction is a constant integer. If so, check to see if
1757 /// there are any bits set in the constant that are not demanded. If so,
1758 /// shrink the constant and return true.
1759 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
1760
1761 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1762 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1763 /// cast, but it could be generalized for targets with other types of
1764 /// implicit widening casts.
1765 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
1766 DebugLoc dl);
1767 };
1768
1769 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1770 /// DemandedMask bits of the result of Op are ever used downstream. If we can
1771 /// use this information to simplify Op, create a new simplified DAG node and
1772 /// return true, returning the original and new nodes in Old and New.
1773 /// Otherwise, analyze the expression and return a mask of KnownOne and
1774 /// KnownZero bits for the expression (used to simplify the caller).
1775 /// The KnownZero/One bits may only be accurate for those bits in the
1776 /// DemandedMask.
1777 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
1778 APInt &KnownZero, APInt &KnownOne,
1779 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
1780
1781 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
1782 /// Mask are known to be either zero or one and return them in the
1783 /// KnownZero/KnownOne bitsets.
1784 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
1785 APInt &KnownZero,
1786 APInt &KnownOne,
1787 const SelectionDAG &DAG,
1788 unsigned Depth = 0) const;
1789
1790 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1791 /// targets that want to expose additional information about sign bits to the
1792 /// DAG Combiner.
1793 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
1794 unsigned Depth = 0) const;
1795
1796 struct DAGCombinerInfo {
1797 void *DC; // The DAG Combiner object.
1798 CombineLevel Level;
1799 bool CalledByLegalizer;
1800 public:
1801 SelectionDAG &DAG;
1802
1803 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
1804 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
1805
1806 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
1807 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
1808 bool isAfterLegalizeVectorOps() const {
1809 return Level == AfterLegalizeDAG;
1810 }
1811 CombineLevel getDAGCombineLevel() { return Level; }
1812 bool isCalledByLegalizer() const { return CalledByLegalizer; }
1813
1814 void AddToWorklist(SDNode *N);
1815 void RemoveFromWorklist(SDNode *N);
1816 SDValue CombineTo(SDNode *N, const std::vector &To,
1817 bool AddTo = true);
1818 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
1819 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
1820
1821 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
1822 };
1823
1824 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1825 /// and cc. If it is unable to simplify it, return a null SDValue.
1826 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1827 ISD::CondCode Cond, bool foldBooleans,
1828 DAGCombinerInfo &DCI, DebugLoc dl) const;
1829
1830 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
1831 /// node is a GlobalAddress + offset.
1832 virtual bool
1833 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
1834
1835 /// PerformDAGCombine - This method will be invoked for all target nodes and
1836 /// for any target-independent nodes that the target has registered with
1837 /// invoke it for.
1838 ///
1839 /// The semantics are as follows:
1840 /// Return Value:
1841 /// SDValue.Val == 0 - No change was made
1842 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
1843 /// otherwise - N should be replaced by the returned Operand.
1844 ///
1845 /// In addition, methods provided by DAGCombinerInfo may be used to perform
1846 /// more complex transformations.
1847 ///
1848 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
1849
1850 /// isTypeDesirableForOp - Return true if the target has native support for
1851 /// the specified value type and it is 'desirable' to use the type for the
1852 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
1853 /// instruction encodings are longer and some i16 instructions are slow.
1854 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
1855 // By default, assume all legal types are desirable.
1856 return isTypeLegal(VT);
1857 }
1858
1859 /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner
1860 /// to transform a floating point op of specified opcode to a equivalent op of
1861 /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM.
1862 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
1863 EVT /*VT*/) const {
1864 return false;
1865 }
1866
1867 /// IsDesirableToPromoteOp - This method query the target whether it is
1868 /// beneficial for dag combiner to promote the specified node. If true, it
1869 /// should return the desired promotion type by reference.
1870 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
1871 return false;
1872 }
1873
1874 //===--------------------------------------------------------------------===//
13041875 // Lowering methods - These methods must be implemented by targets so that
13051876 // the SelectionDAGBuilder code knows how to lower these.
13061877 //
16622233 SelectionDAG &DAG) const;
16632234
16642235 //===--------------------------------------------------------------------===//
2236 // Div utility functions
2237 //
2238 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
2239 SelectionDAG &DAG) const;
2240 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2241 std::vector *Created) const;
2242 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2243 std::vector *Created) const;
2244
2245 //===--------------------------------------------------------------------===//
16652246 // Instruction Emitting Hooks
16662247 //
16672248
16802261 /// e.g. To fill in optional defs for ARM 's' setting instructions.
16812262 virtual void
16822263 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
1683
1684 //===--------------------------------------------------------------------===//
1685 // Addressing mode description hooks (used by LSR etc).
1686 //
1687
1688 /// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the
1689 /// same BB as Load/Store instructions reading the address. This allows as
1690 /// much computation as possible to be done in the address mode for that
1691 /// operand. This hook lets targets also pass back when this should be done
1692 /// on intrinsics which load/store.
1693 virtual bool GetAddrModeArguments(IntrinsicInst *I,
1694 SmallVectorImpl &Ops,
1695 Type *&AccessTy) const {
1696 return false;
1697 }
1698
1699 /// AddrMode - This represents an addressing mode of:
1700 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1701 /// If BaseGV is null, there is no BaseGV.
1702 /// If BaseOffs is zero, there is no base offset.
1703 /// If HasBaseReg is false, there is no base register.
1704 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1705 /// no scale.
1706 ///
1707 struct AddrMode {
1708 GlobalValue *BaseGV;
1709 int64_t BaseOffs;
1710 bool HasBaseReg;
1711 int64_t Scale;
1712 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1713 };
1714
1715 /// isLegalAddressingMode - Return true if the addressing mode represented by
1716 /// AM is legal for this target, for a load/store of the specified type.
1717 /// The type may be VoidTy, in which case only return true if the addressing
1718 /// mode is legal for a load/store of any legal type.
1719 /// TODO: Handle pre/postinc as well.
1720 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1721
1722 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1723 /// icmp immediate, that is the target has icmp instructions which can compare
1724 /// a register against the immediate without having to materialize the
1725 /// immediate into a register.
1726 virtual bool isLegalICmpImmediate(int64_t) const {
1727 return true;
1728 }
1729
1730 /// isLegalAddImmediate - Return true if the specified immediate is legal
1731 /// add immediate, that is the target has add instructions which can add
1732 /// a register with the immediate without having to materialize the
1733 /// immediate into a register.
1734 virtual bool isLegalAddImmediate(int64_t) const {
1735 return true;
1736 }
1737
1738 /// isTruncateFree - Return true if it's free to truncate a value of
1739 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1740 /// register EAX to i16 by referencing its sub-register AX.
1741 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1742 return false;
1743 }
1744
1745 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1746 return false;
1747 }
1748
1749 /// isZExtFree - Return true if any actual instruction that defines a
1750 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1751 /// register. This does not necessarily include registers defined in
1752 /// unknown ways, such as incoming arguments, or copies from unknown
1753 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1754 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1755 /// all instructions that define 32-bit values implicit zero-extend the
1756 /// result out to 64 bits.
1757 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1758 return false;
1759 }
1760
1761 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1762 return false;
1763 }
1764
1765 /// isZExtFree - Return true if zero-extending the specific node Val to type
1766 /// VT2 is free (either because it's implicitly zero-extended such as ARM
1767 /// ldrb / ldrh or because it's folded such as X86 zero-extending loads).
1768 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1769 return isZExtFree(Val.getValueType(), VT2);
1770 }
1771
1772 /// isFNegFree - Return true if an fneg operation is free to the point where
1773 /// it is never worthwhile to replace it with a bitwise operation.
1774 virtual bool isFNegFree(EVT) const {
1775 return false;
1776 }
1777
1778 /// isFAbsFree - Return true if an fneg operation is free to the point where
1779 /// it is never worthwhile to replace it with a bitwise operation.
1780 virtual bool isFAbsFree(EVT) const {
1781 return false;
1782 }
1783
1784 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
1785 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
1786 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
1787 /// is expanded to mul + add.
1788 virtual bool isFMAFasterThanMulAndAdd(EVT) const {
1789 return false;
1790 }
1791
1792 /// isNarrowingProfitable - Return true if it's profitable to narrow
1793 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1794 /// from i32 to i8 but not from i32 to i16.
1795 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1796 return false;
1797 }
1798
1799 //===--------------------------------------------------------------------===//
1800 // Div utility functions
1801 //
1802 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
1803 SelectionDAG &DAG) const;
1804 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
1805 std::vector *Created) const;
1806 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
1807 std::vector *Created) const;
1808
1809
1810 //===--------------------------------------------------------------------===//
1811 // Runtime Library hooks
1812 //
1813
1814 /// setLibcallName - Rename the default libcall routine name for the specified
1815 /// libcall.
1816 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1817 LibcallRoutineNames[Call] = Name;
1818 }
1819
1820 /// getLibcallName - Get the libcall routine name for the specified libcall.
1821 ///
1822 const char *getLibcallName(RTLIB::Libcall Call) const {
1823 return LibcallRoutineNames[Call];
1824 }
1825
1826 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1827 /// result of the comparison libcall against zero.
1828 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1829 CmpLibcallCCs[Call] = CC;
1830 }
1831
1832 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1833 /// the comparison libcall against zero.
1834 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1835 return CmpLibcallCCs[Call];
1836 }
1837
1838 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1839 /// specified libcall.
1840 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1841 LibcallCallingConvs[Call] = CC;
1842 }
1843
1844 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1845 /// specified libcall.
1846 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1847 return LibcallCallingConvs[Call];
1848 }
1849
1850 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
1851 SDValue &Chain) const;
1852
1853 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
1854 SDValue &NewLHS, SDValue &NewRHS,
1855 ISD::CondCode &CCCode, DebugLoc DL) const;
1856
1857 SDValue makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT,
1858 const SDValue *Ops, unsigned NumOps,
1859 bool isSigned, DebugLoc dl) const;
1860
1861 private:
1862 const TargetMachine &TM;
1863 const DataLayout *TD;
1864 const TargetLoweringObjectFile &TLOF;
1865
1866 /// PointerTy - The type to use for pointers for the default address space,
1867 /// usually i32 or i64.
1868 ///
1869 MVT PointerTy;
1870
1871 /// IsLittleEndian - True if this is a little endian target.
1872 ///
1873 bool IsLittleEndian;
1874
1875 /// SelectIsExpensive - Tells the code generator not to expand operations
1876 /// into sequences that use the select operations if possible.
1877 bool SelectIsExpensive;
1878
1879 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1880 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1881 /// a real cost model is in place. If we ever optimize for size, this will be
1882 /// set to true unconditionally.
1883 bool IntDivIsCheap;
1884
1885 /// BypassSlowDivMap - Tells the code generator to bypass slow divide or
1886 /// remainder instructions. For example, BypassSlowDivWidths[32,8] tells the
1887 /// code generator to bypass 32-bit integer div/rem with an 8-bit unsigned
1888 /// integer div/rem when the operands are positive and less than 256.
1889 DenseMap BypassSlowDivWidths;
1890
1891 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1892 /// srl/add/sra for a signed divide by power of two, and let the target handle
1893 /// it.
1894 bool Pow2DivIsCheap;
1895
1896 /// JumpIsExpensive - Tells the code generator that it shouldn't generate
1897 /// extra flow control instructions and should attempt to combine flow
1898 /// control instructions via predication.
1899 bool JumpIsExpensive;
1900
1901 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1902 /// llvm.setjmp. Defaults to false.
1903 bool UseUnderscoreSetJmp;
1904
1905 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1906 /// llvm.longjmp. Defaults to false.
1907 bool UseUnderscoreLongJmp;
1908
1909 /// SupportJumpTables - Whether the target can generate code for jumptables.
1910 /// If it's not true, then each jumptable must be lowered into if-then-else's.
1911 bool SupportJumpTables;
1912
1913 /// MinimumJumpTableEntries - Number of blocks threshold to use jump tables.
1914 int MinimumJumpTableEntries;
1915
1916 /// BooleanContents - Information about the contents of the high-bits in
1917 /// boolean values held in a type wider than i1. See getBooleanContents.
1918 BooleanContent BooleanContents;
1919 /// BooleanVectorContents - Information about the contents of the high-bits
1920 /// in boolean vector values when the element type is wider than i1. See
1921 /// getBooleanContents.
1922 BooleanContent BooleanVectorContents;
1923
1924 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1925 /// total cycles or lowest register usage.
1926 Sched::Preference SchedPreferenceInfo;
1927
1928 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1929 unsigned JumpBufSize;
1930
1931 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1932 /// buffers
1933 unsigned JumpBufAlignment;
1934
1935 /// MinStackArgumentAlignment - The minimum alignment that any argument
1936 /// on the stack needs to have.
1937 ///
1938 unsigned MinStackArgumentAlignment;
1939
1940 /// MinFunctionAlignment - The minimum function alignment (used when
1941 /// optimizing for size, and to prevent explicitly provided alignment
1942 /// from leading to incorrect code).
1943 ///
1944 unsigned MinFunctionAlignment;
1945
1946 /// PrefFunctionAlignment - The preferred function alignment (used when
1947 /// alignment unspecified and optimizing for speed).
1948 ///
1949 unsigned PrefFunctionAlignment;
1950
1951 /// PrefLoopAlignment - The preferred loop alignment.
1952 ///
1953 unsigned PrefLoopAlignment;
1954
1955 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should
1956 /// be folded into the enclosed atomic intrinsic instruction by the
1957 /// combiner.
1958 bool ShouldFoldAtomicFences;
1959
1960 /// InsertFencesForAtomic - Whether the DAG builder should automatically
1961 /// insert fences and reduce ordering for atomics. (This will be set for
1962 /// for most architectures with weak memory ordering.)
1963 bool InsertFencesForAtomic;
1964
1965 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1966 /// specifies the register that llvm.savestack/llvm.restorestack should save
1967 /// and restore.
1968 unsigned StackPointerRegisterToSaveRestore;
1969
1970 /// ExceptionPointerRegister - If set to a physical register, this specifies
1971 /// the register that receives the exception address on entry to a landing
1972 /// pad.
1973 unsigned ExceptionPointerRegister;
1974
1975 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1976 /// the register that receives the exception typeid on entry to a landing
1977 /// pad.
1978 unsigned ExceptionSelectorRegister;
1979
1980 /// RegClassForVT - This indicates the default register class to use for
1981 /// each ValueType the target supports natively.
1982 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1983 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1984 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1985
1986 /// RepRegClassForVT - This indicates the "representative" register class to
1987 /// use for each ValueType the target supports natively. This information is
1988 /// used by the scheduler to track register pressure. By default, the
1989 /// representative register class is the largest legal super-reg register
1990 /// class of the register class of the specified type. e.g. On x86, i8, i16,
1991 /// and i32's representative class would be GR32.
1992 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1993
1994 /// RepRegClassCostForVT - This indicates the "cost" of the "representative"
1995 /// register class for each ValueType. The cost is used by the scheduler to
1996 /// approximate register pressure.
1997 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1998
1999 /// TransformToType - For any value types we are promoting or expanding, this
2000 /// contains the value type that we are changing to. For Expanded types, this
2001 /// contains one step of the expand (e.g. i64 -> i32), even if there are
2002 /// multiple steps required (e.g. i64 -> i16). For types natively supported
2003 /// by the system, this holds the same type (e.g. i32 -> i32).
2004 MVT TransformToType[MVT::LAST_VALUETYPE];
2005
2006 /// OpActions - For each operation and each value type, keep a LegalizeAction
2007 /// that indicates how instruction selection should deal with the operation.
2008 /// Most operations are Legal (aka, supported natively by the target), but
2009 /// operations that are not should be described. Note that operations on
2010 /// non-legal value types are not described here.
2011 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
2012
2013 /// LoadExtActions - For each load extension type and each value type,
2014 /// keep a LegalizeAction that indicates how instruction selection should deal
2015 /// with a load of a specific value type and extension type.
2016 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
2017
2018 /// TruncStoreActions - For each value type pair keep a LegalizeAction that
2019 /// indicates whether a truncating store of a specific value type and
2020 /// truncating type is legal.
2021 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2022
2023 /// IndexedModeActions - For each indexed mode and each value type,
2024 /// keep a pair of LegalizeAction that indicates how instruction
2025 /// selection should deal with the load / store. The first dimension is the
2026 /// value_type for the reference. The second dimension represents the various
2027 /// modes for load store.
2028 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2029
2030 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
2031 /// LegalizeAction that indicates how instruction selection should
2032 /// deal with the condition code.
2033 /// Because each CC action takes up 2 bits, we need to have the array size
2034 /// be large enough to fit all of the value types. This can be done by
2035 /// dividing the MVT::LAST_VALUETYPE by 32 and adding one.
2036 uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) + 1];
2037
2038 ValueTypeActionImpl ValueTypeActions;
2039
2040 public:
2041 LegalizeKind
2042 getTypeConversion(LLVMContext &Context, EVT VT) const {
2043 // If this is a simple type, use the ComputeRegisterProp mechanism.
2044 if (VT.isSimple()) {
2045 MVT SVT = VT.getSimpleVT();
2046 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
2047 MVT NVT = TransformToType[SVT.SimpleTy];
2048 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
2049
2050 assert(
2051 (LA == TypeLegal ||
2052 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
2053 && "Promote may not follow Expand or Promote");
2054
2055 if (LA == TypeSplitVector)
2056 return LegalizeKind(LA, EVT::getVectorVT(Context,
2057 SVT.getVectorElementType(),
2058 SVT.getVectorNumElements()/2));
2059 if (LA == TypeScalarizeVector)
2060 return LegalizeKind(LA, SVT.getVectorElementType());
2061 return LegalizeKind(LA, NVT);
2062 }
2063
2064 // Handle Extended Scalar Types.
2065 if (!VT.isVector()) {
2066 assert(VT.isInteger() && "Float types must be simple");
2067 unsigned BitSize = VT.getSizeInBits();
2068 // First promote to a power-of-two size, then expand if necessary.
2069 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
2070 EVT NVT = VT.getRoundIntegerType(Context);
2071 assert(NVT != VT && "Unable to round integer VT");
2072 LegalizeKind NextStep = getTypeConversion(Context, NVT);
2073 // Avoid multi-step promotion.
2074 if (NextStep.first == TypePromoteInteger) return NextStep;
2075 // Return rounded integer type.
2076 return LegalizeKind(TypePromoteInteger, NVT);
2077 }
2078
2079 return LegalizeKind(TypeExpandInteger,
2080 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
2081 }
2082
2083 // Handle vector types.
2084 unsigned NumElts = VT.getVectorNumElements();
2085 EVT EltVT = VT.getVectorElementType();
2086
2087 // Vectors with only one element are always scalarized.
2088 if (NumElts == 1)
2089 return LegalizeKind(TypeScalarizeVector, EltVT);
2090
2091 // Try to widen vector elements until a legal type is found.
2092 if (EltVT.isInteger()) {
2093 // Vectors with a number of elements that is not a power of two are always
2094 // widened, for example <3 x float> -> <4 x float>.
2095 if (!VT.isPow2VectorType()) {
2096 NumElts = (unsigned)NextPowerOf2(NumElts);
2097 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
2098 return LegalizeKind(TypeWidenVector, NVT);
2099 }
2100
2101 // Examine the element type.
2102 LegalizeKind LK = getTypeConversion(Context, EltVT);
2103
2104 // If type is to be expanded, split the vector.
2105 // <4 x i140> -> <2 x i140>
2106 if (LK.first == TypeExpandInteger)
2107 return LegalizeKind(TypeSplitVector,
2108 EVT::getVectorVT(Context, EltVT, NumElts / 2));
2109
2110 // Promote the integer element types until a legal vector type is found
2111 // or until the element integer type is too big. If a legal type was not
2112 // found, fallback to the usual mechanism of widening/splitting the
2113 // vector.
2114 while (1) {
2115 // Increase the bitwidth of the element to the next pow-of-two
2116 // (which is greater than 8 bits).
2117 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
2118 ).getRoundIntegerType(Context);
2119
2120 // Stop trying when getting a non-simple element type.
2121 // Note that vector elements may be greater than legal vector element
2122 // types. Example: X86 XMM registers hold 64bit element on 32bit systems.
2123 if (!EltVT.isSimple()) break;
2124
2125 // Build a new vector type and check if it is legal.
2126 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
2127 // Found a legal promoted vector type.
2128 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
2129 return LegalizeKind(TypePromoteInteger,
2130 EVT::getVectorVT(Context, EltVT, NumElts));
2131 }
2132 }
2133
2134 // Try to widen the vector until a legal type is found.
2135 // If there is no wider legal type, split the vector.
2136 while (1) {
2137 // Round up to the next power of 2.
2138 NumElts = (unsigned)NextPowerOf2(NumElts);
2139
2140 // If there is no simple vector type with this many elements then there
2141 // cannot be a larger legal vector type. Note that this assumes that
2142 // there are no skipped intermediate vector types in the simple types.
2143 if (!EltVT.isSimple()) break;
2144 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
2145 if (LargerVector == MVT()) break;
2146
2147 // If this type is legal then widen the vector.
2148 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
2149 return LegalizeKind(TypeWidenVector, LargerVector);
2150 }
2151
2152 // Widen odd vectors to next power of two.
2153 if (!VT.isPow2VectorType()) {
2154 EVT NVT = VT.getPow2VectorType(Context);
2155 return LegalizeKind(TypeWidenVector, NVT);
2156 }
2157
2158 // Vectors with illegal element types are expanded.
2159 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
2160 return LegalizeKind(TypeSplitVector, NVT);
2161 }
2162
2163 private:
2164 std::vector > AvailableRegClasses;
2165
2166 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
2167 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
2168 /// which sets a bit in this array.
2169 unsigned char
2170 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2171
2172 /// PromoteToType - For operations that must be promoted to a specific type,
2173 /// this holds the destination type. This map should be sparse, so don't hold
2174 /// it as an array.
2175 ///
2176 /// Targets add entries to this map with AddPromotedToType(..), clients access
2177 /// this with getTypeToPromoteTo(..).
2178 std::map, MVT::SimpleValueType>
2179 PromoteToType;
2180
2181 /// LibcallRoutineNames - Stores the name each libcall.
2182 ///
2183 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
2184
2185 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
2186 /// of each of the comparison libcall against zero.
2187 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2188
2189 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
2190 /// libcall.
2191 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2192
2193 protected:
2194 /// When lowering \@llvm.memset this field specifies the maximum number of
2195 /// store operations that may be substituted for the call to memset. Targets
2196 /// must set this value based on the cost threshold for that target. Targets
2197 /// should assume that the memset will be done using as many of the largest
2198 /// store operations first, followed by smaller ones, if necessary, per
2199 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2200 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2201 /// store. This only applies to setting a constant array of a constant size.
2202 /// @brief Specify maximum number of store instructions per memset call.
2203 unsigned maxStoresPerMemset;
2204
2205 /// Maximum number of stores operations that may be substituted for the call
2206 /// to memset, used for functions with OptSize attribute.
2207 unsigned maxStoresPerMemsetOptSize;
2208
2209 /// When lowering \@llvm.memcpy this field specifies the maximum number of
2210 /// store operations that may be substituted for a call to memcpy. Targets
2211 /// must set this value based on the cost threshold for that target. Targets
2212 /// should assume that the memcpy will be done using as many of the largest
2213 /// store operations first, followed by smaller ones, if necessary, per
2214 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2215 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2216 /// and one 1-byte store. This only applies to copying a constant array of
2217 /// constant size.
2218 /// @brief Specify maximum bytes of store instructions per memcpy call.
2219 unsigned maxStoresPerMemcpy;
2220
2221 /// Maximum number of store operations that may be substituted for a call
2222 /// to memcpy, used for functions with OptSize attribute.
2223 unsigned maxStoresPerMemcpyOptSize;
2224
2225 /// When lowering \@llvm.memmove this field specifies the maximum number of
2226 /// store instructions that may be substituted for a call to memmove. Targets
2227 /// must set this value based on the cost threshold for that target. Targets
2228 /// should assume that the memmove will be done using as many of the largest
2229 /// store operations first, followed by smaller ones, if necessary, per
2230 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2231 /// with 8-bit alignment would result in nine 1-byte stores. This only
2232 /// applies to copying a constant array of constant size.
2233 /// @brief Specify maximum bytes of store instructions per memmove call.
2234 unsigned maxStoresPerMemmove;
2235
2236 /// Maximum number of store instructions that may be substituted for a call
2237 /// to memmove, used for functions with OpSize attribute.
2238 unsigned maxStoresPerMemmoveOptSize;
2239
2240 /// This field specifies whether the target can benefit from code placement
2241 /// optimization.
2242 bool benefitFromCodePlacementOpt;
2243
2244 /// predictableSelectIsExpensive - Tells the code generator that select is
2245 /// more expensive than a branch if the branch is usually predicted right.
2246 bool predictableSelectIsExpensive;
2247
2248 private:
2249 /// isLegalRC - Return true if the value types that can be represented by the
2250 /// specified register class are all legal.
2251 bool isLegalRC(const TargetRegisterClass *RC) const;
22522264 };
22532265
22542266 /// GetReturnInfo - Given an LLVM IR type and return type attributes,
2525 namespace {
2626
2727 class BasicTTI : public ImmutablePass, public TargetTransformInfo {
28 const TargetLowering *TLI;
28 const TargetLoweringBase *TLI;
2929
3030 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
3131 /// are set if the result needs to be inserted and/or extracted from vectors.
3636 llvm_unreachable("This pass cannot be directly constructed");
3737 }
3838
39 BasicTTI(const TargetLowering *TLI) : ImmutablePass(ID), TLI(TLI) {
39 BasicTTI(const TargetLoweringBase *TLI) : ImmutablePass(ID), TLI(TLI) {
4040 initializeBasicTTIPass(*PassRegistry::getPassRegistry());
4141 }
4242
111111 char BasicTTI::ID = 0;
112112
113113 ImmutablePass *
114 llvm::createBasicTargetTransformInfoPass(const TargetLowering *TLI) {
114 llvm::createBasicTargetTransformInfoPass(const TargetLoweringBase *TLI) {
115115 return new BasicTTI(TLI);
116116 }
117117
127127 bool BasicTTI::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
128128 int64_t BaseOffset, bool HasBaseReg,
129129 int64_t Scale) const {
130 TargetLowering::AddrMode AM;
130 TargetLoweringBase::AddrMode AM;
131131 AM.BaseGV = BaseGV;
132132 AM.BaseOffs = BaseOffset;
133133 AM.HasBaseReg = HasBaseReg;
88 CodeGen.cpp
99 CodePlacementOpt.cpp
1010 CriticalAntiDepBreaker.cpp
11 DFAPacketizer.cpp
1112 DeadMachineInstructionElim.cpp
12 DFAPacketizer.cpp
1313 DwarfEHPrepare.cpp
1414 EarlyIfConversion.cpp
1515 EdgeBundles.cpp
3131 LiveInterval.cpp
3232 LiveIntervalAnalysis.cpp
3333 LiveIntervalUnion.cpp
34 LiveRangeCalc.cpp
35 LiveRangeEdit.cpp
3436 LiveRegMatrix.cpp
3537 LiveStackAnalysis.cpp
3638 LiveVariables.cpp
37 LiveRangeCalc.cpp
38 LiveRangeEdit.cpp
3939 LocalStackSlotAllocation.cpp
4040 MachineBasicBlock.cpp
4141 MachineBlockFrequencyInfo.cpp
4242 MachineBlockPlacement.cpp
4343 MachineBranchProbabilityInfo.cpp
44 MachineCSE.cpp
4445 MachineCodeEmitter.cpp
4546 MachineCopyPropagation.cpp
46 MachineCSE.cpp
4747 MachineDominators.cpp
48 MachinePostDominators.cpp
4948 MachineFunction.cpp
5049 MachineFunctionAnalysis.cpp
5150 MachineFunctionPass.cpp
5756 MachineModuleInfo.cpp
5857 MachineModuleInfoImpls.cpp
5958 MachinePassRegistry.cpp
59 MachinePostDominators.cpp
6060 MachineRegisterInfo.cpp
6161 MachineSSAUpdater.cpp
6262 MachineScheduler.cpp
9090 ShrinkWrapping.cpp
9191 SjLjEHPrepare.cpp
9292 SlotIndexes.cpp
93 SpillPlacement.cpp
9394 Spiller.cpp
94 SpillPlacement.cpp
9595 SplitKit.cpp
96 StackColoring.cpp
9697 StackProtector.cpp
9798 StackSlotColoring.cpp
98 StackColoring.cpp
9999 StrongPHIElimination.cpp
100100 TailDuplication.cpp
101101 TargetFrameLoweringImpl.cpp
102102 TargetInstrInfo.cpp
103 TargetLoweringBase.cpp
103104 TargetLoweringObjectFileImpl.cpp
104105 TargetOptionsImpl.cpp
105106 TargetRegisterInfo.cpp
3232 namespace {
3333 class DwarfEHPrepare : public FunctionPass {
3434 const TargetMachine *TM;
35 const TargetLowering *TLI;
35 const TargetLoweringBase *TLI;
3636
3737 // RewindFunction - _Unwind_Resume or the target equivalent.
3838 Constant *RewindFunction;
150150 /// basic block number.
151151 std::vector BBAnalysis;
152152
153 const TargetLowering *TLI;
153 const TargetLoweringBase *TLI;
154154 const TargetInstrInfo *TII;
155155 const TargetRegisterInfo *TRI;
156156 const InstrItineraryData *InstrItins;
170170 const TargetInstrInfo *TII;
171171
172172 /// \brief A handle to the target's lowering info.
173 const TargetLowering *TLI;
173 const TargetLoweringBase *TLI;
174174
175175 /// \brief Allocator and owner of BlockChain structures.
176176 ///
6161 class MachineLICM : public MachineFunctionPass {
6262 const TargetMachine *TM;
6363 const TargetInstrInfo *TII;
64 const TargetLowering *TLI;
64 const TargetLoweringBase *TLI;
6565 const TargetRegisterInfo *TRI;
6666 const MachineFrameInfo *MFI;
6767 MachineRegisterInfo *MRI;
3131 #include "llvm/Target/TargetRegisterInfo.h"
3232 #include
3333 using namespace llvm;
34
35 /// InitLibcallNames - Set default libcall names.
36 ///
37 static void InitLibcallNames(const char **Names) {
38 Names[RTLIB::SHL_I16] = "__ashlhi3";
39 Names[RTLIB::SHL_I32] = "__ashlsi3";
40 Names[RTLIB::SHL_I64] = "__ashldi3";
41 Names[RTLIB::SHL_I128] = "__ashlti3";
42 Names[RTLIB::SRL_I16] = "__lshrhi3";
43 Names[RTLIB::SRL_I32] = "__lshrsi3";
44 Names[RTLIB::SRL_I64] = "__lshrdi3";
45 Names[RTLIB::SRL_I128] = "__lshrti3";
46 Names[RTLIB::SRA_I16] = "__ashrhi3";
47 Names[RTLIB::SRA_I32] = "__ashrsi3";
48 Names[RTLIB::SRA_I64] = "__ashrdi3";
49 Names[RTLIB::SRA_I128] = "__ashrti3";
50 Names[RTLIB::MUL_I8] = "__mulqi3";
51 Names[RTLIB::MUL_I16] = "__mulhi3";
52 Names[RTLIB::MUL_I32] = "__mulsi3";
53 Names[RTLIB::MUL_I64] = "__muldi3";
54 Names[RTLIB::MUL_I128] = "__multi3";
55 Names[RTLIB::MULO_I32] = "__mulosi4";
56 Names[RTLIB::MULO_I64] = "__mulodi4";
57 Names[RTLIB::MULO_I128] = "__muloti4";
58 Names[RTLIB::SDIV_I8] = "__divqi3";
59 Names[RTLIB::SDIV_I16] = "__divhi3";
60 Names[RTLIB::SDIV_I32] = "__divsi3";
61 Names[RTLIB::SDIV_I64] = "__divdi3";
62 Names[RTLIB::SDIV_I128] = "__divti3";
63 Names[RTLIB::UDIV_I8] = "__udivqi3";
64 Names[RTLIB::UDIV_I16] = "__udivhi3";
65 Names[RTLIB::UDIV_I32] = "__udivsi3";
66 Names[RTLIB::UDIV_I64] = "__udivdi3";
67 Names[RTLIB::UDIV_I128] = "__udivti3";
68 Names[RTLIB::SREM_I8] = "__modqi3";
69 Names[RTLIB::SREM_I16] = "__modhi3";
70 Names[RTLIB::SREM_I32] = "__modsi3";
71 Names[RTLIB::SREM_I64] = "__moddi3";
72 Names[RTLIB::SREM_I128] = "__modti3";
73 Names[RTLIB::UREM_I8] = "__umodqi3";
74 Names[RTLIB::UREM_I16] = "__umodhi3";
75 Names[RTLIB::UREM_I32] = "__umodsi3";
76 Names[RTLIB::UREM_I64] = "__umoddi3";
77 Names[RTLIB::UREM_I128] = "__umodti3";
78
79 // These are generally not available.
80 Names[RTLIB::SDIVREM_I8] = 0;
81 Names[RTLIB::SDIVREM_I16] = 0;
82 Names[RTLIB::SDIVREM_I32] = 0;
83 Names[RTLIB::SDIVREM_I64] = 0;
84 Names[RTLIB::SDIVREM_I128] = 0;
85 Names[RTLIB::UDIVREM_I8] = 0;
86 Names[RTLIB::UDIVREM_I16] = 0;
87 Names[RTLIB::UDIVREM_I32] = 0;
88 Names[RTLIB::UDIVREM_I64] = 0;
89 Names[RTLIB::UDIVREM_I128] = 0;
90
91 Names[RTLIB::NEG_I32] = "__negsi2";
92 Names[RTLIB::NEG_I64] = "__negdi2";
93 Names[RTLIB::ADD_F32] = "__addsf3";
94 Names[RTLIB::ADD_F64] = "__adddf3";
95 Names[RTLIB::ADD_F80] = "__addxf3";
96 Names[RTLIB::ADD_F128] = "__addtf3";
97 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
98 Names[RTLIB::SUB_F32] = "__subsf3";
99 Names[RTLIB::SUB_F64] = "__subdf3";
100 Names[RTLIB::SUB_F80] = "__subxf3";
101 Names[RTLIB::SUB_F128] = "__subtf3";
102 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
103 Names[RTLIB::MUL_F32] = "__mulsf3";
104 Names[RTLIB::MUL_F64] = "__muldf3";
105 Names[RTLIB::MUL_F80] = "__mulxf3";
106 Names[RTLIB::MUL_F128] = "__multf3";
107 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
108 Names[RTLIB::DIV_F32] = "__divsf3";
109 Names[RTLIB::DIV_F64] = "__divdf3";
110 Names[RTLIB::DIV_F80] = "__divxf3";
111 Names[RTLIB::DIV_F128] = "__divtf3";
112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
113 Names[RTLIB::REM_F32] = "fmodf";
114 Names[RTLIB::REM_F64] = "fmod";
115 Names[RTLIB::REM_F80] = "fmodl";
116 Names[RTLIB::REM_F128] = "fmodl";
117 Names[RTLIB::REM_PPCF128] = "fmodl";
118 Names[RTLIB::FMA_F32] = "fmaf";
119 Names[RTLIB::FMA_F64] = "fma";
120 Names[RTLIB::FMA_F80] = "fmal";
121 Names[RTLIB::FMA_F128] = "fmal";
122 Names[RTLIB::FMA_PPCF128] = "fmal";
123 Names[RTLIB::POWI_F32] = "__powisf2";
124 Names[RTLIB::POWI_F64] = "__powidf2";
125 Names[RTLIB::POWI_F80] = "__powixf2";
126 Names[RTLIB::POWI_F128] = "__powitf2";
127 Names[RTLIB::POWI_PPCF128] = "__powitf2";
128 Names[RTLIB::SQRT_F32] = "sqrtf";
129 Names[RTLIB::SQRT_F64] = "sqrt";
130 Names[RTLIB::SQRT_F80] = "sqrtl";
131 Names[RTLIB::SQRT_F128] = "sqrtl";
132 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
133 Names[RTLIB::LOG_F32] = "logf";
134 Names[RTLIB::LOG_F64] = "log";
135 Names[RTLIB::LOG_F80] = "logl";
136 Names[RTLIB::LOG_F128] = "logl";
137 Names[RTLIB::LOG_PPCF128] = "logl";
138 Names[RTLIB::LOG2_F32] = "log2f";
139 Names[RTLIB::LOG2_F64] = "log2";
140 Names[RTLIB::LOG2_F80] = "log2l";
141 Names[RTLIB::LOG2_F128] = "log2l";
142 Names[RTLIB::LOG2_PPCF128] = "log2l";
143 Names[RTLIB::LOG10_F32] = "log10f";
144 Names[RTLIB::LOG10_F64] = "log10";
145 Names[RTLIB::LOG10_F80] = "log10l";
146 Names[RTLIB::LOG10_F128] = "log10l";
147 Names[RTLIB::LOG10_PPCF128] = "log10l";
148 Names[RTLIB::EXP_F32] = "expf";
149 Names[RTLIB::EXP_F64] = "exp";
150 Names[RTLIB::EXP_F80] = "expl";
151 Names[RTLIB::EXP_F128] = "expl";
152 Names[RTLIB::EXP_PPCF128] = "expl";
153 Names[RTLIB::EXP2_F32] = "exp2f";
154 Names[RTLIB::EXP2_F64] = "exp2";
155 Names[RTLIB::EXP2_F80] = "exp2l";
156 Names[RTLIB::EXP2_F128] = "exp2l";
157 Names[RTLIB::EXP2_PPCF128] = "exp2l";
158 Names[RTLIB::SIN_F32] = "sinf";
159 Names[RTLIB::SIN_F64] = "sin";
160 Names[RTLIB::SIN_F80] = "sinl";
161 Names[RTLIB::SIN_F128] = "sinl";
162 Names[RTLIB::SIN_PPCF128] = "sinl";
163 Names[RTLIB::COS_F32] = "cosf";
164 Names[RTLIB::COS_F64] = "cos";
165 Names[RTLIB::COS_F80] = "cosl";
166 Names[RTLIB::COS_F128] = "cosl";
167 Names[RTLIB::COS_PPCF128] = "cosl";
168 Names[RTLIB::POW_F32] = "powf";
169 Names[RTLIB::POW_F64] = "pow";
170 Names[RTLIB::POW_F80] = "powl";
171 Names[RTLIB::POW_F128] = "powl";
172 Names[RTLIB::POW_PPCF128] = "powl";
173 Names[RTLIB::CEIL_F32] = "ceilf";
174 Names[RTLIB::CEIL_F64] = "ceil";
175 Names[RTLIB::CEIL_F80] = "ceill";
176 Names[RTLIB::CEIL_F128] = "ceill";
177 Names[RTLIB::CEIL_PPCF128] = "ceill";
178 Names[RTLIB::TRUNC_F32] = "truncf";
179 Names[RTLIB::TRUNC_F64] = "trunc";
180 Names[RTLIB::TRUNC_F80] = "truncl";
181 Names[RTLIB::TRUNC_F128] = "truncl";
182 Names[RTLIB::TRUNC_PPCF128] = "truncl";
183 Names[RTLIB::RINT_F32] = "rintf";
184 Names[RTLIB::RINT_F64] = "rint";
185 Names[RTLIB::RINT_F80] = "rintl";
186 Names[RTLIB::RINT_F128] = "rintl";
187 Names[RTLIB::RINT_PPCF128] = "rintl";
188 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
189 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
190 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
191 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
192 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
193 Names[RTLIB::FLOOR_F32] = "floorf";
194 Names[RTLIB::FLOOR_F64] = "floor";
195 Names[RTLIB::FLOOR_F80] = "floorl";
196 Names[RTLIB::FLOOR_F128] = "floorl";
197 Names[RTLIB::FLOOR_PPCF128] = "floorl";
198 Names[RTLIB::COPYSIGN_F32] = "copysignf";
199 Names[RTLIB::COPYSIGN_F64] = "copysign";
200 Names[RTLIB::COPYSIGN_F80] = "copysignl";
201 Names[RTLIB::COPYSIGN_F128] = "copysignl";
202 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
203 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
204 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
205 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
206 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
207 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
208 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
209 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
210 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
211 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
212 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
213 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
214 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
215 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
216 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
217 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
218 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
219 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
220 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
221 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
222 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
223 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
224 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
225 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
226 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
227 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
228 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
229 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
230 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
231 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
232 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
233 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
234 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
235 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
236 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
237 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
238 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
239 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
240 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
241 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
242 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
243 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
244 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
245 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
246 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
247 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
248 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
249 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
250 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
251 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
252 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
253 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
254 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
255 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
256 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
257 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
258 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
259 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
260 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
261 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
262 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
263 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
264 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
265 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
266 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
267 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
268 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
269 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
270 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
271 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
272 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
273 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
274 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
275 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
276 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
277 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
278 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
279 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
280 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
281 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
282 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
283 Names[RTLIB::OEQ_F32] = "__eqsf2";
284 Names[RTLIB::OEQ_F64] = "__eqdf2";
285 Names[RTLIB::OEQ_F128] = "__eqtf2";
286 Names[RTLIB::UNE_F32] = "__nesf2";
287 Names[RTLIB::UNE_F64] = "__nedf2";
288 Names[RTLIB::UNE_F128] = "__netf2";
289 Names[RTLIB::OGE_F32] = "__gesf2";
290 Names[RTLIB::OGE_F64] = "__gedf2";
291 Names[RTLIB::OGE_F128] = "__getf2";
292 Names[RTLIB::OLT_F32] = "__ltsf2";
293 Names[RTLIB::OLT_F64] = "__ltdf2";
294 Names[RTLIB::OLT_F128] = "__lttf2";
295 Names[RTLIB::OLE_F32] = "__lesf2";
296 Names[RTLIB::OLE_F64] = "__ledf2";
297 Names[RTLIB::OLE_F128] = "__letf2";
298 Names[RTLIB::OGT_F32] = "__gtsf2";
299 Names[RTLIB::OGT_F64] = "__gtdf2";
300 Names[RTLIB::OGT_F128] = "__gttf2";
301 Names[RTLIB::UO_F32] = "__unordsf2";
302 Names[RTLIB::UO_F64] = "__unorddf2";
303 Names[RTLIB::UO_F128] = "__unordtf2";
304 Names[RTLIB::O_F32] = "__unordsf2";
305 Names[RTLIB::O_F64] = "__unorddf2";
306 Names[RTLIB::O_F128] = "__unordtf2";
307 Names[RTLIB::MEMCPY] = "memcpy";
308 Names[RTLIB::MEMMOVE] = "memmove";
309 Names[RTLIB::MEMSET] = "memset";
310 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
311 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
312 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
313 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
314 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
315 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
316 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
317 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
318 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
319 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
320 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
321 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
322 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
323 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
324 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
325 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
326 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
327 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
328 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
329 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
330 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
331 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
332 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
333 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
334 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
335 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
336 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
337 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
338 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
339 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
340 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
341 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
342 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
343 }
344
345 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
346 ///
347 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
348 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
349 CCs[i] = CallingConv::C;
350 }
351 }
35234
35335 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
35436 /// UNKNOWN_LIBCALL if there is none.
570252 return UNKNOWN_LIBCALL;
571253 }
572254
573 /// InitCmpLibcallCCs - Set default comparison libcall CC.
574 ///
575 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
576 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
577 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
578 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
579 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
580 CCs[RTLIB::UNE_F32] = ISD::SETNE;
581 CCs[RTLIB::UNE_F64] = ISD::SETNE;
582 CCs[RTLIB::UNE_F128] = ISD::SETNE;
583 CCs[RTLIB::OGE_F32] = ISD::SETGE;
584 CCs[RTLIB::OGE_F64] = ISD::SETGE;
585 CCs[RTLIB::OGE_F128] = ISD::SETGE;
586 CCs[RTLIB::OLT_F32] = ISD::SETLT;
587 CCs[RTLIB::OLT_F64] = ISD::SETLT;
588 CCs[RTLIB::OLT_F128] = ISD::SETLT;
589 CCs[RTLIB::OLE_F32] = ISD::SETLE;
590 CCs[RTLIB::OLE_F64] = ISD::SETLE;
591 CCs[RTLIB::OLE_F128] = ISD::SETLE;
592 CCs[RTLIB::OGT_F32] = ISD::SETGT;
593 CCs[RTLIB::OGT_F64] = ISD::SETGT;
594 CCs[RTLIB::OGT_F128] = ISD::SETGT;
595 CCs[RTLIB::UO_F32] = ISD::SETNE;
596 CCs[RTLIB::UO_F64] = ISD::SETNE;
597 CCs[RTLIB::UO_F128] = ISD::SETNE;
598 CCs[RTLIB::O_F32] = ISD::SETEQ;
599 CCs[RTLIB::O_F64] = ISD::SETEQ;
600 CCs[RTLIB::O_F128] = ISD::SETEQ;
601 }
602
603255 /// NOTE: The constructor takes ownership of TLOF.
604256 TargetLowering::TargetLowering(const TargetMachine &tm,
605257 const TargetLoweringObjectFile *tlof)
606 : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) {
607 // All operations default to being supported.
608 memset(OpActions, 0, sizeof(OpActions));
609 memset(LoadExtActions, 0, sizeof(LoadExtActions));
610 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
611 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
612 memset(CondCodeActions, 0, sizeof(CondCodeActions));
613
614 // Set default actions for various operations.
615 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
616 // Default all indexed load / store to expand.
617 for (unsigned IM = (unsigned)ISD::PRE_INC;
618 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
619 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
620 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
621 }
622
623 // These operations default to expand.
624 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
625 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
626 }
627
628 // Most targets ignore the @llvm.prefetch intrinsic.
629 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
630
631 // ConstantFP nodes default to expand. Targets can either change this to
632 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
633 // to optimize expansions for certain constants.
634 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
635 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
636 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
637 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
638 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
639
640 // These library functions default to expand.
641 setOperationAction(ISD::FLOG , MVT::f16, Expand);
642 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
643 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
644 setOperationAction(ISD::FEXP , MVT::f16, Expand);
645 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
646 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
647 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
648 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
649 setOperationAction(ISD::FRINT, MVT::f16, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
651 setOperationAction(ISD::FLOG , MVT::f32, Expand);
652 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
653 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
654 setOperationAction(ISD::FEXP , MVT::f32, Expand);
655 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
656 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
657 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
658 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
659 setOperationAction(ISD::FRINT, MVT::f32, Expand);
660 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
661 setOperationAction(ISD::FLOG , MVT::f64, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
664 setOperationAction(ISD::FEXP , MVT::f64, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
666 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
667 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
668 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
669 setOperationAction(ISD::FRINT, MVT::f64, Expand);
670 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
671 setOperationAction(ISD::FLOG , MVT::f128, Expand);
672 setOperationAction(ISD::FLOG2, MVT::f128, Expand);
673 setOperationAction(ISD::FLOG10, MVT::f128, Expand);
674 setOperationAction(ISD::FEXP , MVT::f128, Expand);
675 setOperationAction(ISD::FEXP2, MVT::f128, Expand);
676 setOperationAction(ISD::FFLOOR, MVT::f128, Expand);
677 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand);
678 setOperationAction(ISD::FCEIL, MVT::f128, Expand);
679 setOperationAction(ISD::FRINT, MVT::f128, Expand);
680 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
681
682 // Default ISD::TRAP to expand (which turns it into abort).
683 setOperationAction(ISD::TRAP, MVT::Other, Expand);
684
685 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
686 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
687 //
688 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
689
690 IsLittleEndian = TD->isLittleEndian();
691 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize(0));
692 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
693 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
694 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
695 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
696 = maxStoresPerMemmoveOptSize = 4;
697 benefitFromCodePlacementOpt = false;
698 UseUnderscoreSetJmp = false;
699 UseUnderscoreLongJmp = false;
700 SelectIsExpensive = false;
701 IntDivIsCheap = false;
702 Pow2DivIsCheap = false;
703 JumpIsExpensive = false;
704 predictableSelectIsExpensive = false;
705 StackPointerRegisterToSaveRestore = 0;
706 ExceptionPointerRegister = 0;
707 ExceptionSelectorRegister = 0;
708 BooleanContents = UndefinedBooleanContent;
709 BooleanVectorContents = UndefinedBooleanContent;
710 SchedPreferenceInfo = Sched::ILP;
711 JumpBufSize = 0;
712 JumpBufAlignment = 0;
713 MinFunctionAlignment = 0;
714 PrefFunctionAlignment = 0;
715 PrefLoopAlignment = 0;
716 MinStackArgumentAlignment = 1;
717 ShouldFoldAtomicFences = false;
718 InsertFencesForAtomic = false;
719 SupportJumpTables = true;
720 MinimumJumpTableEntries = 4;
721
722 InitLibcallNames(LibcallRoutineNames);
723 InitCmpLibcallCCs(CmpLibcallCCs);
724 InitLibcallCallingConvs(LibcallCallingConvs);
725 }
726
727 TargetLowering::~TargetLowering() {
728 delete &TLOF;
729 }
730
731 MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
732 return MVT::getIntegerVT(8*TD->getPointerSize(0));
733 }
734
735 /// canOpTrap - Returns true if the operation can trap for the value type.
736 /// VT must be a legal type.
737 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
738 assert(isTypeLegal(VT));
739 switch (Op) {
740 default:
741 return false;
742 case ISD::FDIV:
743 case ISD::FREM:
744 case ISD::SDIV:
745 case ISD::UDIV:
746 case ISD::SREM:
747 case ISD::UREM:
748 return true;
749 }
750 }
751
752
753 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
754 unsigned &NumIntermediates,
755 MVT &RegisterVT,
756 TargetLowering *TLI) {
757 // Figure out the right, legal destination reg to copy into.
758 unsigned NumElts = VT.getVectorNumElements();
759 MVT EltTy = VT.getVectorElementType();
760
761 unsigned NumVectorRegs = 1;
762
763 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
764 // could break down into LHS/RHS like LegalizeDAG does.
765 if (!isPowerOf2_32(NumElts)) {
766 NumVectorRegs = NumElts;
767 NumElts = 1;
768 }
769
770 // Divide the input until we get to a supported size. This will always
771 // end with a scalar if the target doesn't support vectors.
772 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
773 NumElts >>= 1;
774 NumVectorRegs <<= 1;
775 }
776
777 NumIntermediates = NumVectorRegs;
778
779 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
780 if (!TLI->isTypeLegal(NewVT))
781 NewVT = EltTy;
782 IntermediateVT = NewVT;
783
784 unsigned NewVTSize = NewVT.getSizeInBits();
785
786 // Convert sizes such as i33 to i64.
787 if (!isPowerOf2_32(NewVTSize))
788 NewVTSize = NextPowerOf2(NewVTSize);
789
790 MVT DestVT = TLI->getRegisterType(NewVT);
791 RegisterVT = DestVT;
792 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
793 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
794
795 // Otherwise, promotion or legal types use the same number of registers as
796 // the vector decimated to the appropriate level.
797 return NumVectorRegs;
798 }
799
800 /// isLegalRC - Return true if the value types that can be represented by the
801 /// specified register class are all legal.
802 bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
803 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
804 I != E; ++I) {
805 if (isTypeLegal(*I))
806 return true;
807 }
808 return false;
809 }
810
811 /// findRepresentativeClass - Return the largest legal super-reg register class
812 /// of the register class for the specified type and its associated "cost".
813 std::pair
814 TargetLowering::findRepresentativeClass(MVT VT) const {
815 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
816 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
817 if (!RC)
818 return std::make_pair(RC, 0);
819
820 // Compute the set of all super-register classes.
821 BitVector SuperRegRC(TRI->getNumRegClasses());
822 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
823 SuperRegRC.setBitsInMask(RCI.getMask());
824
825 // Find the first legal register class with the largest spill size.
826 const TargetRegisterClass *BestRC = RC;
827 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
828 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
829 // We want the largest possible spill size.
830 if (SuperRC->getSize() <= BestRC->getSize())
831 continue;
832 if (!isLegalRC(SuperRC))
833 continue;
834 BestRC = SuperRC;
835 }
836 return std::make_pair(BestRC, 1);
837 }
838
839 /// computeRegisterProperties - Once all of the register classes are added,
840 /// this allows us to compute derived properties we expose.
841 void TargetLowering::computeRegisterProperties() {
842 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
843 "Too many value types for ValueTypeActions to hold!");
844
845 // Everything defaults to needing one register.
846 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
847 NumRegistersForVT[i] = 1;
848 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
849 }
850 // ...except isVoid, which doesn't need any registers.
851 NumRegistersForVT[MVT::isVoid] = 0;
852
853 // Find the largest integer register class.
854 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
855 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
856 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
857
858 // Every integer value type larger than this largest register takes twice as
859 // many registers to represent as the previous ValueType.
860 for (unsigned ExpandedReg = LargestIntReg + 1;
861 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
862 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
863 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
864 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
865 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
866 TypeExpandInteger);
867 }
868
869 // Inspect all of the ValueType's smaller than the largest integer
870 // register to see which ones need promotion.
871 unsigned LegalIntReg = LargestIntReg;
872 for (unsigned IntReg = LargestIntReg - 1;
873 IntReg >= (unsigned)MVT::i1; --IntReg) {
874 MVT IVT = (MVT::SimpleValueType)IntReg;
875 if (isTypeLegal(IVT)) {
876 LegalIntReg = IntReg;
877 } else {
878 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
879 (const MVT::SimpleValueType)LegalIntReg;
880 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
881 }
882 }
883
884 // ppcf128 type is really two f64's.
885 if (!isTypeLegal(MVT::ppcf128)) {
886 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
887 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
888 TransformToType[MVT::ppcf128] = MVT::f64;
889 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
890 }
891
892 // Decide how to handle f64. If the target does not have native f64 support,
893 // expand it to i64 and we will be generating soft float library calls.
894 if (!isTypeLegal(MVT::f64)) {
895 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
896 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
897 TransformToType[MVT::f64] = MVT::i64;
898 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
899 }
900
901 // Decide how to handle f32. If the target does not have native support for
902 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
903 if (!isTypeLegal(MVT::f32)) {
904 if (isTypeLegal(MVT::f64)) {
905 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
906 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
907 TransformToType[MVT::f32] = MVT::f64;
908 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
909 } else {
910 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
911 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
912 TransformToType[MVT::f32] = MVT::i32;
913 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
914 }
915 }
916
917 // Loop over all of the vector value types to see which need transformations.
918 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
919 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
920 MVT VT = (MVT::SimpleValueType)i;
921 if (isTypeLegal(VT)) continue;
922
923 // Determine if there is a legal wider type. If so, we should promote to
924 // that wider vector type.
925 MVT EltVT = VT.getVectorElementType();
926 unsigned NElts = VT.getVectorNumElements();
927 if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) {
928 bool IsLegalWiderType = false;
929 // First try to promote the elements of integer vectors. If no legal
930 // promotion was found, fallback to the widen-vector method.
931 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
932 MVT SVT = (MVT::SimpleValueType)nVT;
933 // Promote vectors of integers to vectors with the same number
934 // of elements, with a wider element type.
935 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
936 && SVT.getVectorNumElements() == NElts &&
937 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
938 TransformToType[i] = SVT;
939 RegisterTypeForVT[i] = SVT;
940 NumRegistersForVT[i] = 1;
941 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
942 IsLegalWiderType = true;
943 break;
944 }
945 }
946
947 if (IsLegalWiderType) continue;
948
949 // Try to widen the vector.
950 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
951 MVT SVT = (MVT::SimpleValueType)nVT;
952 if (SVT.getVectorElementType() == EltVT &&
953 SVT.getVectorNumElements() > NElts &&
954 isTypeLegal(SVT)) {
955 TransformToType[i] = SVT;
956 RegisterTypeForVT[i] = SVT;
957 NumRegistersForVT[i] = 1;
958 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
959 IsLegalWiderType = true;
960 break;
961 }
962 }
963 if (IsLegalWiderType) continue;
964 }
965
966 MVT IntermediateVT;
967 MVT RegisterVT;
968 unsigned NumIntermediates;
969 NumRegistersForVT[i] =
970 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
971 RegisterVT, this);
972 RegisterTypeForVT[i] = RegisterVT;
973
974 MVT NVT = VT.getPow2VectorType();
975 if (NVT == VT) {
976 // Type is already a power of 2. The default action is to split.
977 TransformToType[i] = MVT::Other;
978 unsigned NumElts = VT.getVectorNumElements();
979 ValueTypeActions.setTypeAction(VT,
980 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
981 } else {
982 TransformToType[i] = NVT;
983 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
984 }
985 }
986
987 // Determine the 'representative' register class for each value type.
988 // An representative register class is the largest (meaning one which is
989 // not a sub-register class / subreg register class) legal register class for
990 // a group of value types. For example, on i386, i8, i16, and i32
991 // representative would be GR32; while on x86_64 it's GR64.
992 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
993 const TargetRegisterClass* RRC;
994 uint8_t Cost;
995 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
996 RepRegClassForVT[i] = RRC;
997 RepRegClassCostForVT[i] = Cost;
998 }
999 }
258 : TargetLoweringBase(tm, tlof) {}
1000259
1001260 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
1002261 return NULL;
1003 }
1004
1005 EVT TargetLowering::getSetCCResultType(EVT VT) const {
1006 assert(!VT.isVector() && "No default SetCC type for vectors!");
1007 return getPointerTy(0).SimpleTy;
1008 }
1009
1010 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
1011 return MVT::i32; // return the default value
1012262 }
1013263
1014264 /// Check whether a given call node is in tail position within its function. If
1166416 }
1167417 }
1168418
1169 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1170 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1171 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1172 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1173 ///
1174 /// This method returns the number of registers needed, and the VT for each
1175 /// register. It also returns the VT and quantity of the intermediate values
1176 /// before they are promoted/expanded.
1177 ///
1178 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1179 EVT &IntermediateVT,
1180 unsigned &NumIntermediates,
1181 MVT &RegisterVT) const {
1182 unsigned NumElts = VT.getVectorNumElements();
1183
1184 // If there is a wider vector type with the same element type as this one,
1185 // or a promoted vector type that has the same number of elements which
1186 // are wider, then we should convert to that legal vector type.
1187 // This handles things like <2 x float> -> <4 x float> and
1188 // <4 x i1> -> <4 x i32>.
1189 LegalizeTypeAction TA = getTypeAction(Context, VT);
1190 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1191 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1192 if (isTypeLegal(RegisterEVT)) {
1193 IntermediateVT = RegisterEVT;
1194 RegisterVT = RegisterEVT.getSimpleVT();
1195 NumIntermediates = 1;
1196 return 1;
1197 }
1198 }
1199
1200 // Figure out the right, legal destination reg to copy into.
1201 EVT EltTy = VT.getVectorElementType();
1202
1203 unsigned NumVectorRegs = 1;
1204
1205 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1206 // could break down into LHS/RHS like LegalizeDAG does.
1207 if (!isPowerOf2_32(NumElts)) {
1208 NumVectorRegs = NumElts;
1209 NumElts = 1;
1210 }
1211
1212 // Divide the input until we get to a supported size. This will always
1213 // end with a scalar if the target doesn't support vectors.
1214 while (NumElts > 1 && !isTypeLegal(
1215 EVT::getVectorVT(Context, EltTy, NumElts))) {
1216 NumElts >>= 1;
1217 NumVectorRegs <<= 1;
1218 }
1219
1220 NumIntermediates = NumVectorRegs;
1221
1222 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1223 if (!isTypeLegal(NewVT))
1224 NewVT = EltTy;
1225 IntermediateVT = NewVT;
1226
1227 MVT DestVT = getRegisterType(Context, NewVT);
1228 RegisterVT = DestVT;
1229 unsigned NewVTSize = NewVT.getSizeInBits();
1230
1231 // Convert sizes such as i33 to i64.
1232 if (!isPowerOf2_32(NewVTSize))
1233 NewVTSize = NextPowerOf2(NewVTSize);
1234
1235 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1236 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1237
1238 // Otherwise, promotion or legal types use the same number of registers as
1239 // the vector decimated to the appropriate level.
1240 return NumVectorRegs;
1241 }
1242
1243419 /// Get the EVTs and ArgFlags collections that represent the legalized return
1244420 /// type of the given function. This does not require a DAG or a return value,
1245421 /// and is suitable for use before any DAGs for the function are constructed.
1290466 }
1291467 }
1292468
1293 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1294 /// function arguments in the caller parameter area. This is the actual
1295 /// alignment, not its logarithm.
1296 unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
1297 return TD->getCallFrameTypeAlignment(Ty);
1298 }
1299
1300469 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1301470 /// current function. The returned value is a member of the
1302471 /// MachineJumpTableInfo::JTEntryKind enum.
1350519
1351520 // Otherwise assume nothing is safe.
1352521 return false;
1353 }
1354
1355 //===----------------------------------------------------------------------===//
1356 // TargetTransformInfo Helpers
1357 //===----------------------------------------------------------------------===//
1358
1359 int TargetLowering::InstructionOpcodeToISD(unsigned Opcode) const {
1360 enum InstructionOpcodes {
1361 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1362 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1363 #include "llvm/IR/Instruction.def"
1364 };
1365 switch (static_cast(Opcode)) {
1366 case Ret: return 0;
1367 case Br: return 0;
1368 case Switch: return 0;
1369 case IndirectBr: return 0;
1370 case Invoke: return 0;
1371 case Resume: return 0;
1372 case Unreachable: return 0;
1373 case Add: return ISD::ADD;
1374 case FAdd: return ISD::FADD;
1375 case Sub: return ISD::SUB;
1376 case FSub: return ISD::FSUB;
1377 case Mul: return ISD::MUL;
1378 case FMul: return ISD::FMUL;
1379 case UDiv: return ISD::UDIV;
1380 case SDiv: return ISD::UDIV;
1381 case FDiv: return ISD::FDIV;
1382 case URem: return ISD::UREM;
1383 case SRem: return ISD::SREM;
1384 case FRem: return ISD::FREM;
1385 case Shl: return ISD::SHL;
1386 case LShr: return ISD::SRL;
1387 case AShr: return ISD::SRA;
1388 case And: return ISD::AND;
1389 case Or: return ISD::OR;
1390 case Xor: return ISD::XOR;
1391 case Alloca: return 0;
1392 case Load: return ISD::LOAD;
1393 case Store: return ISD::STORE;
1394 case GetElementPtr: return 0;
1395 case Fence: return 0;
1396 case AtomicCmpXchg: return 0;
1397 case AtomicRMW: return 0;
1398 case Trunc: return ISD::TRUNCATE;
1399 case ZExt: return ISD::ZERO_EXTEND;
1400 case SExt: return ISD::SIGN_EXTEND;
1401 case FPToUI: return ISD::FP_TO_UINT;
1402 case FPToSI: return ISD::FP_TO_SINT;
1403 case UIToFP: return ISD::UINT_TO_FP;
1404 case SIToFP: return ISD::SINT_TO_FP;
1405 case FPTrunc: return ISD::FP_ROUND;
1406 case FPExt: return ISD::FP_EXTEND;
1407 case PtrToInt: return ISD::BITCAST;
1408 case IntToPtr: return ISD::BITCAST;
1409 case BitCast: return ISD::BITCAST;
1410 case ICmp: return ISD::SETCC;
1411 case FCmp: return ISD::SETCC;
1412 case PHI: return 0;
1413 case Call: return 0;
1414 case Select: return ISD::SELECT;
1415 case UserOp1: return 0;
1416 case UserOp2: return 0;
1417 case VAArg: return 0;
1418 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1419 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1420 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1421 case ExtractValue: return ISD::MERGE_VALUES;
1422 case InsertValue: return ISD::MERGE_VALUES;
1423 case LandingPad: return 0;
1424 }
1425
1426 llvm_unreachable("Unknown instruction type encountered!");
1427 }
1428
1429 std::pair
1430 TargetLowering::getTypeLegalizationCost(Type *Ty) const {
1431 LLVMContext &C = Ty->getContext();
1432 EVT MTy = getValueType(Ty);
1433
1434 unsigned Cost = 1;
1435 // We keep legalizing the type until we find a legal kind. We assume that
1436 // the only operation that costs anything is the split. After splitting
1437 // we need to handle two types.
1438 while (true) {
1439 LegalizeKind LK = getTypeConversion(C, MTy);
1440
1441 if (LK.first == TypeLegal)
1442 return std::make_pair(Cost, MTy.getSimpleVT());
1443
1444 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1445 Cost *= 2;
1446
1447 // Keep legalizing the type.
1448 MTy = LK.second;
1449 }
1450522 }
1451523
1452524 //===----------------------------------------------------------------------===//
23931465 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
23941466 for (unsigned offset=0; offset
23951467 if ((newMask & Mask) == Mask) {
2396 if (!TD->isLittleEndian())
1468 if (!getDataLayout()->isLittleEndian())
23971469 bestOffset = (origWidth/width - offset - 1) * (width/8);
23981470 else
23991471 bestOffset = (uint64_t)offset * (width/8);
31982270 std::make_pair(0u, static_cast(0));
31992271
32002272 // Figure out which register class contains this reg.
3201 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2273 const TargetRegisterInfo *RI = getTargetMachine().getRegisterInfo();
32022274 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
32032275 E = RI->regclass_end(); RCI != E; ++RCI) {
32042276 const TargetRegisterClass *RC = *RCI;
33222394 // If OpTy is not a single value, it may be a struct/union that we
33232395 // can tile with integers.
33242396 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
3325 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2397 unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
33262398 switch (BitSize) {
33272399 default: break;
33282400 case 1:
33372409 }
33382410 } else if (PointerType *PT = dyn_cast(OpTy)) {
33392411 OpInfo.ConstraintVT = MVT::getIntegerVT(
3340 8*TD->getPointerSize(PT->getAddressSpace()));
2412 8*getDataLayout()->getPointerSize(PT->getAddressSpace()));
33412413 } else {
33422414 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
33432415 }
36322704 }
36332705 }
36342706
3635 //===----------------------------------------------------------------------===//
3636 // Loop Strength Reduction hooks
3637 //===----------------------------------------------------------------------===//
3638
3639 /// isLegalAddressingMode - Return true if the addressing mode represented
3640 /// by AM is legal for this target, for a load/store of the specified type.
3641 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
3642 Type *Ty) const {
3643 // The default implementation of this implements a conservative RISCy, r+r and
3644 // r+i addr mode.
3645
3646 // Allows a sign-extended 16-bit immediate field.
3647 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3648 return false;
3649
3650 // No global is ever allowed as a base.
3651 if (AM.BaseGV)
3652 return false;
3653
3654 // Only support r+r,
3655 switch (AM.Scale) {
3656 case 0: // "r+i" or just "i", depending on HasBaseReg.
3657 break;
3658 case 1:
3659 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3660 return false;
3661 // Otherwise we have r+r or r+i.
3662 break;
3663 case 2:
3664 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3665 return false;
3666 // Allow 2*r as r+r.
3667 break;
3668 }
3669
3670 return true;
3671 }
3672
36732707 /// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
36742708 /// with the multiplicative inverse of the constant.
36752709 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
4242
4343 namespace {
4444 class SjLjEHPrepare : public FunctionPass {
45 const TargetLowering *TLI;
45 const TargetLoweringBase *TLI;
4646 Type *FunctionContextTy;
4747 Constant *RegisterFn;
4848 Constant *UnregisterFn;
5757 AllocaInst *FuncCtx;
5858 public:
5959 static char ID; // Pass identification, replacement for typeid
60 explicit SjLjEHPrepare(const TargetLowering *tli = NULL)
60 explicit SjLjEHPrepare(const TargetLoweringBase *tli = NULL)
6161 : FunctionPass(ID), TLI(tli) { }
6262 bool doInitialization(Module &M);
6363 bool runOnFunction(Function &F);
8181 char SjLjEHPrepare::ID = 0;
8282
8383 // Public Interface To the SjLjEHPrepare pass.
84 FunctionPass *llvm::createSjLjEHPreparePass(const TargetLowering *TLI) {
84 FunctionPass *llvm::createSjLjEHPreparePass(const TargetLoweringBase *TLI) {
8585 return new SjLjEHPrepare(TLI);
8686 }
8787 // doInitialization - Set up decalarations and types needed to process
3535 class StackProtector : public FunctionPass {
3636 /// TLI - Keep a pointer of a TargetLowering to consult for determining
3737 /// target type sizes.
38 const TargetLowering *TLI;
38 const TargetLoweringBase *TLI;
3939
4040 Function *F;
4141 Module *M;
6767 StackProtector() : FunctionPass(ID), TLI(0) {
6868 initializeStackProtectorPass(*PassRegistry::getPassRegistry());
6969 }
70 StackProtector(const TargetLowering *tli)
70 StackProtector(const TargetLoweringBase *tli)
7171 : FunctionPass(ID), TLI(tli) {
7272 initializeStackProtectorPass(*PassRegistry::getPassRegistry());
7373 }
8484 INITIALIZE_PASS(StackProtector, "stack-protector",
8585 "Insert stack protectors", false, false)
8686
87 FunctionPass *llvm::createStackProtectorPass(const TargetLowering *tli) {
87 FunctionPass *llvm::createStackProtectorPass(const TargetLoweringBase *tli) {
8888 return new StackProtector(tli);
8989 }
9090
0 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/Target/TargetLowering.h"
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/CodeGen/Analysis.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineJumpTableInfo.h"
20 #include "llvm/IR/DataLayout.h"
21 #include "llvm/IR/DerivedTypes.h"
22 #include "llvm/IR/GlobalVariable.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetLoweringObjectFile.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include
32 using namespace llvm;
33
34 /// InitLibcallNames - Set default libcall names.
35 ///
36 static void InitLibcallNames(const char **Names) {
37 Names[RTLIB::SHL_I16] = "__ashlhi3";
38 Names[RTLIB::SHL_I32] = "__ashlsi3";
39 Names[RTLIB::SHL_I64] = "__ashldi3";
40 Names[RTLIB::SHL_I128] = "__ashlti3";
41 Names[RTLIB::SRL_I16] = "__lshrhi3";
42 Names[RTLIB::SRL_I32] = "__lshrsi3";
43 Names[RTLIB::SRL_I64] = "__lshrdi3";
44 Names[RTLIB::SRL_I128] = "__lshrti3";
45 Names[RTLIB::SRA_I16] = "__ashrhi3";
46 Names[RTLIB::SRA_I32] = "__ashrsi3";
47 Names[RTLIB::SRA_I64] = "__ashrdi3";
48 Names[RTLIB::SRA_I128] = "__ashrti3";
49 Names[RTLIB::MUL_I8] = "__mulqi3";
50 Names[RTLIB::MUL_I16] = "__mulhi3";
51 Names[RTLIB::MUL_I32] = "__mulsi3";
52 Names[RTLIB::MUL_I64] = "__muldi3";
53 Names[RTLIB::MUL_I128] = "__multi3";
54 Names[RTLIB::MULO_I32] = "__mulosi4";
55 Names[RTLIB::MULO_I64] = "__mulodi4";
56 Names[RTLIB::MULO_I128] = "__muloti4";
57 Names[RTLIB::SDIV_I8] = "__divqi3";
58 Names[RTLIB::SDIV_I16] = "__divhi3";
59 Names[RTLIB::SDIV_I32] = "__divsi3";
60 Names[RTLIB::SDIV_I64] = "__divdi3";
61 Names[RTLIB::SDIV_I128] = "__divti3";
62 Names[RTLIB::UDIV_I8] = "__udivqi3";
63 Names[RTLIB::UDIV_I16] = "__udivhi3";
64 Names[RTLIB::UDIV_I32] = "__udivsi3";
65 Names[RTLIB::UDIV_I64] = "__udivdi3";
66 Names[RTLIB::UDIV_I128] = "__udivti3";
67 Names[RTLIB::SREM_I8] = "__modqi3";
68 Names[RTLIB::SREM_I16] = "__modhi3";
69 Names[RTLIB::SREM_I32] = "__modsi3";
70 Names[RTLIB::SREM_I64] = "__moddi3";
71 Names[RTLIB::SREM_I128] = "__modti3";
72 Names[RTLIB::UREM_I8] = "__umodqi3";
73 Names[RTLIB::UREM_I16] = "__umodhi3";
74 Names[RTLIB::UREM_I32] = "__umodsi3";
75 Names[RTLIB::UREM_I64] = "__umoddi3";
76 Names[RTLIB::UREM_I128] = "__umodti3";
77
78 // These are generally not available.
79 Names[RTLIB::SDIVREM_I8] = 0;
80 Names[RTLIB::SDIVREM_I16] = 0;
81 Names[RTLIB::SDIVREM_I32] = 0;
82 Names[RTLIB::SDIVREM_I64] = 0;
83 Names[RTLIB::SDIVREM_I128] = 0;
84 Names[RTLIB::UDIVREM_I8] = 0;
85 Names[RTLIB::UDIVREM_I16] = 0;
86 Names[RTLIB::UDIVREM_I32] = 0;
87 Names[RTLIB::UDIVREM_I64] = 0;
88 Names[RTLIB::UDIVREM_I128] = 0;
89
90 Names[RTLIB::NEG_I32] = "__negsi2";
91 Names[RTLIB::NEG_I64] = "__negdi2";
92 Names[RTLIB::ADD_F32] = "__addsf3";
93 Names[RTLIB::ADD_F64] = "__adddf3";
94 Names[RTLIB::ADD_F80] = "__addxf3";
95 Names[RTLIB::ADD_F128] = "__addtf3";
96 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
97 Names[RTLIB::SUB_F32] = "__subsf3";
98 Names[RTLIB::SUB_F64] = "__subdf3";
99 Names[RTLIB::SUB_F80] = "__subxf3";
100 Names[RTLIB::SUB_F128] = "__subtf3";
101 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
102 Names[RTLIB::MUL_F32] = "__mulsf3";
103 Names[RTLIB::MUL_F64] = "__muldf3";
104 Names[RTLIB::MUL_F80] = "__mulxf3";
105 Names[RTLIB::MUL_F128] = "__multf3";
106 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
107 Names[RTLIB::DIV_F32] = "__divsf3";
108 Names[RTLIB::DIV_F64] = "__divdf3";
109 Names[RTLIB::DIV_F80] = "__divxf3";
110 Names[RTLIB::DIV_F128] = "__divtf3";
111 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
112 Names[RTLIB::REM_F32] = "fmodf";
113 Names[RTLIB::REM_F64] = "fmod";
114 Names[RTLIB::REM_F80] = "fmodl";
115 Names[RTLIB::REM_F128] = "fmodl";
116 Names[RTLIB::REM_PPCF128] = "fmodl";
117 Names[RTLIB::FMA_F32] = "fmaf";
118 Names[RTLIB::FMA_F64] = "fma";
119 Names[RTLIB::FMA_F80] = "fmal";
120 Names[RTLIB::FMA_F128] = "fmal";
121 Names[RTLIB::FMA_PPCF128] = "fmal";
122 Names[RTLIB::POWI_F32] = "__powisf2";
123 Names[RTLIB::POWI_F64] = "__powidf2";
124 Names[RTLIB::POWI_F80] = "__powixf2";
125 Names[RTLIB::POWI_F128] = "__powitf2";
126 Names[RTLIB::POWI_PPCF128] = "__powitf2";
127 Names[RTLIB::SQRT_F32] = "sqrtf";
128 Names[RTLIB::SQRT_F64] = "sqrt";
129 Names[RTLIB::SQRT_F80] = "sqrtl";
130 Names[RTLIB::SQRT_F128] = "sqrtl";
131 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
132 Names[RTLIB::LOG_F32] = "logf";
133 Names[RTLIB::LOG_F64] = "log";
134 Names[RTLIB::LOG_F80] = "logl";
135 Names[RTLIB::LOG_F128] = "logl";
136 Names[RTLIB::LOG_PPCF128] = "logl";
137 Names[RTLIB::LOG2_F32] = "log2f";
138 Names[RTLIB::LOG2_F64] = "log2";
139 Names[RTLIB::LOG2_F80] = "log2l";
140 Names[RTLIB::LOG2_F128] = "log2l";
141 Names[RTLIB::LOG2_PPCF128] = "log2l";
142 Names[RTLIB::LOG10_F32] = "log10f";
143 Names[RTLIB::LOG10_F64] = "log10";
144 Names[RTLIB::LOG10_F80] = "log10l";
145 Names[RTLIB::LOG10_F128] = "log10l";
146 Names[RTLIB::LOG10_PPCF128] = "log10l";
147 Names[RTLIB::EXP_F32] = "expf";
148 Names[RTLIB::EXP_F64] = "exp";
149 Names[RTLIB::EXP_F80] = "expl";
150 Names[RTLIB::EXP_F128] = "expl";
151 Names[RTLIB::EXP_PPCF128] = "expl";
152 Names[RTLIB::EXP2_F32] = "exp2f";
153 Names[RTLIB::EXP2_F64] = "exp2";
154 Names[RTLIB::EXP2_F80] = "exp2l";
155 Names[RTLIB::EXP2_F128] = "exp2l";
156 Names[RTLIB::EXP2_PPCF128] = "exp2l";
157 Names[RTLIB::SIN_F32] = "sinf";
158 Names[RTLIB::SIN_F64] = "sin";
159 Names[RTLIB::SIN_F80] = "sinl";
160 Names[RTLIB::SIN_F128] = "sinl";
161 Names[RTLIB::SIN_PPCF128] = "sinl";
162 Names[RTLIB::COS_F32] = "cosf";
163 Names[RTLIB::COS_F64] = "cos";
164 Names[RTLIB::COS_F80] = "cosl";
165 Names[RTLIB::COS_F128] = "cosl";
166 Names[RTLIB::COS_PPCF128] = "cosl";
167 Names[RTLIB::POW_F32] = "powf";
168 Names[RTLIB::POW_F64] = "pow";
169 Names[RTLIB::POW_F80] = "powl";
170 Names[RTLIB::POW_F128] = "powl";
171 Names[RTLIB::POW_PPCF128] = "powl";
172 Names[RTLIB::CEIL_F32] = "ceilf";
173 Names[RTLIB::CEIL_F64] = "ceil";
174 Names[RTLIB::CEIL_F80] = "ceill";
175 Names[RTLIB::CEIL_F128] = "ceill";
176 Names[RTLIB::CEIL_PPCF128] = "ceill";
177 Names[RTLIB::TRUNC_F32] = "truncf";
178 Names[RTLIB::TRUNC_F64] = "trunc";
179 Names[RTLIB::TRUNC_F80] = "truncl";
180 Names[RTLIB::TRUNC_F128] = "truncl";
181 Names[RTLIB::TRUNC_PPCF128] = "truncl";
182 Names[RTLIB::RINT_F32] = "rintf";
183 Names[RTLIB::RINT_F64] = "rint";
184 Names[RTLIB::RINT_F80] = "rintl";
185 Names[RTLIB::RINT_F128] = "rintl";
186 Names[RTLIB::RINT_PPCF128] = "rintl";
187 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
188 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
189 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
190 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
191 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
192 Names[RTLIB::FLOOR_F32] = "floorf";
193 Names[RTLIB::FLOOR_F64] = "floor";
194 Names[RTLIB::FLOOR_F80] = "floorl";
195 Names[RTLIB::FLOOR_F128] = "floorl";
196 Names[RTLIB::FLOOR_PPCF128] = "floorl";
197 Names[RTLIB::COPYSIGN_F32] = "copysignf";
198 Names[RTLIB::COPYSIGN_F64] = "copysign";
199 Names[RTLIB::COPYSIGN_F80] = "copysignl";
200 Names[RTLIB::COPYSIGN_F128] = "copysignl";
201 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
202 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
203 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
204 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
205 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
206 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
207 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
208 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
209 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
210 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
211 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
212 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
213 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
214 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
215 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
216 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
217 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
218 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
219 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
220 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
221 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
222 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
223 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
224 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
225 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
226 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
227 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
228 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
229 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
230 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
231 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
232 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
233 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
234 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
235 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
236 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
237 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
238 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
239 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
240 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
241 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
242 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
243 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
244 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
245 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
246 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
247 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
248 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
249 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
250 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
251 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
252 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
253 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
254 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
255 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
256 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
257 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
258 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
259 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
260 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
261 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
262 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
263 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
264 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
265 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
266 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
267 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
268 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
269 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
270 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
271 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
272 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
273 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
274 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
275 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
276 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
277 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
278 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
279 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
280 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
281 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
282 Names[RTLIB::OEQ_F32] = "__eqsf2";
283 Names[RTLIB::OEQ_F64] = "__eqdf2";
284 Names[RTLIB::OEQ_F128] = "__eqtf2";
285 Names[RTLIB::UNE_F32] = "__nesf2";
286 Names[RTLIB::UNE_F64] = "__nedf2";
287 Names[RTLIB::UNE_F128] = "__netf2";
288 Names[RTLIB::OGE_F32] = "__gesf2";
289 Names[RTLIB::OGE_F64] = "__gedf2";
290 Names[RTLIB::OGE_F128] = "__getf2";
291 Names[RTLIB::OLT_F32] = "__ltsf2";
292 Names[RTLIB::OLT_F64] = "__ltdf2";
293 Names[RTLIB::OLT_F128] = "__lttf2";
294 Names[RTLIB::OLE_F32] = "__lesf2";
295 Names[RTLIB::OLE_F64] = "__ledf2";
296 Names[RTLIB::OLE_F128] = "__letf2";
297 Names[RTLIB::OGT_F32] = "__gtsf2";
298 Names[RTLIB::OGT_F64] = "__gtdf2";
299 Names[RTLIB::OGT_F128] = "__gttf2";
300 Names[RTLIB::UO_F32] = "__unordsf2";
301 Names[RTLIB::UO_F64] = "__unorddf2";
302 Names[RTLIB::UO_F128] = "__unordtf2";
303 Names[RTLIB::O_F32] = "__unordsf2";
304 Names[RTLIB::O_F64] = "__unorddf2";
305 Names[RTLIB::O_F128] = "__unordtf2";
306 Names[RTLIB::MEMCPY] = "memcpy";
307 Names[RTLIB::MEMMOVE] = "memmove";
308 Names[RTLIB::MEMSET] = "memset";
309 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
310 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
311 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
312 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
313 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
314 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
315 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
316 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
317 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
318 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
319 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
320 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
321 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
322 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
323 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
324 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
325 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
326 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
327 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
328 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
329 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
330 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
331 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
332 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
333 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
334 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
335 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
336 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
337 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
338 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
339 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
340 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
341 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
342 }
343
344 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
345 ///
346 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
347 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
348 CCs[i] = CallingConv::C;
349 }
350 }
351
352 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
353 /// UNKNOWN_LIBCALL if there is none.
354 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
355 if (OpVT == MVT::f32) {
356 if (RetVT == MVT::f64)
357 return FPEXT_F32_F64;
358 if (RetVT == MVT::f128)
359 return FPEXT_F32_F128;
360 } else if (OpVT == MVT::f64) {
361 if (RetVT == MVT::f128)
362 return FPEXT_F64_F128;
363 }
364
365 return UNKNOWN_LIBCALL;
366 }
367
368 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
369 /// UNKNOWN_LIBCALL if there is none.
370 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
371 if (RetVT == MVT::f32) {
372 if (OpVT == MVT::f64)
373 return FPROUND_F64_F32;
374 if (OpVT == MVT::f80)
375 return FPROUND_F80_F32;
376 if (OpVT == MVT::f128)
377 return FPROUND_F128_F32;
378 if (OpVT == MVT::ppcf128)
379 return FPROUND_PPCF128_F32;
380 } else if (RetVT == MVT::f64) {
381 if (OpVT == MVT::f80)
382 return FPROUND_F80_F64;
383 if (OpVT == MVT::f128)
384 return FPROUND_F128_F64;
385 if (OpVT == MVT::ppcf128)
386 return FPROUND_PPCF128_F64;
387 }
388
389 return UNKNOWN_LIBCALL;
390 }
391
392 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
393 /// UNKNOWN_LIBCALL if there is none.
394 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
395 if (OpVT == MVT::f32) {
396 if (RetVT == MVT::i8)
397 return FPTOSINT_F32_I8;
398 if (RetVT == MVT::i16)
399 return FPTOSINT_F32_I16;
400 if (RetVT == MVT::i32)
401 return FPTOSINT_F32_I32;
402 if (RetVT == MVT::i64)
403 return FPTOSINT_F32_I64;
404 if (RetVT == MVT::i128)
405 return FPTOSINT_F32_I128;
406 } else if (OpVT == MVT::f64) {
407 if (RetVT == MVT::i8)
408 return FPTOSINT_F64_I8;
409 if (RetVT == MVT::i16)
410 return FPTOSINT_F64_I16;
411 if (RetVT == MVT::i32)
412 return FPTOSINT_F64_I32;
413 if (RetVT == MVT::i64)
414 return FPTOSINT_F64_I64;
415 if (RetVT == MVT::i128)
416 return FPTOSINT_F64_I128;
417 } else if (OpVT == MVT::f80) {
418 if (RetVT == MVT::i32)
419 return FPTOSINT_F80_I32;
420 if (RetVT == MVT::i64)
421 return FPTOSINT_F80_I64;
422 if (RetVT == MVT::i128)
423 return FPTOSINT_F80_I128;
424 } else if (OpVT == MVT::f128) {
425 if (RetVT == MVT::i32)
426 return FPTOSINT_F128_I32;
427 if (RetVT == MVT::i64)
428 return FPTOSINT_F128_I64;
429 if (RetVT == MVT::i128)
430 return FPTOSINT_F128_I128;
431 } else if (OpVT == MVT::ppcf128) {
432 if (RetVT == MVT::i32)
433 return FPTOSINT_PPCF128_I32;
434 if (RetVT == MVT::i64)
435 return FPTOSINT_PPCF128_I64;
436 if (RetVT == MVT::i128)
437 return FPTOSINT_PPCF128_I128;
438 }
439 return UNKNOWN_LIBCALL;
440 }
441
442 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
443 /// UNKNOWN_LIBCALL if there is none.
444 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
445 if (OpVT == MVT::f32) {
446 if (RetVT == MVT::i8)
447 return FPTOUINT_F32_I8;
448 if (RetVT == MVT::i16)
449 return FPTOUINT_F32_I16;
450 if (RetVT == MVT::i32)
451 return FPTOUINT_F32_I32;
452 if (RetVT == MVT::i64)
453 return FPTOUINT_F32_I64;
454 if (RetVT == MVT::i128)
455 return FPTOUINT_F32_I128;
456 } else if (OpVT == MVT::f64) {
457 if (RetVT == MVT::i8)
458 return FPTOUINT_F64_I8;
459 if (RetVT == MVT::i16)
460 return FPTOUINT_F64_I16;
461 if (RetVT == MVT::i32)
462 return FPTOUINT_F64_I32;
463 if (RetVT == MVT::i64)
464 return FPTOUINT_F64_I64;
465 if (RetVT == MVT::i128)
466 return FPTOUINT_F64_I128;
467 } else if (OpVT == MVT::f80) {
468 if (RetVT == MVT::i32)
469 return FPTOUINT_F80_I32;
470 if (RetVT == MVT::i64)
471 return FPTOUINT_F80_I64;
472 if (RetVT == MVT::i128)
473 return FPTOUINT_F80_I128;
474 } else if (OpVT == MVT::f128) {
475 if (RetVT == MVT::i32)
476 return FPTOUINT_F128_I32;
477 if (RetVT == MVT::i64)
478 return FPTOUINT_F128_I64;
479 if (RetVT == MVT::i128)
480 return FPTOUINT_F128_I128;
481 } else if (OpVT == MVT::ppcf128) {
482 if (RetVT == MVT::i32)
483 return FPTOUINT_PPCF128_I32;
484 if (RetVT == MVT::i64)
485 return FPTOUINT_PPCF128_I64;
486 if (RetVT == MVT::i128)
487 return FPTOUINT_PPCF128_I128;
488 }
489 return UNKNOWN_LIBCALL;
490 }
491
492 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
493 /// UNKNOWN_LIBCALL if there is none.
494 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
495 if (OpVT == MVT::i32) {
496 if (RetVT == MVT::f32)
497 return SINTTOFP_I32_F32;
498 if (RetVT == MVT::f64)
499 return SINTTOFP_I32_F64;
500 if (RetVT == MVT::f80)
501 return SINTTOFP_I32_F80;
502 if (RetVT == MVT::f128)
503 return SINTTOFP_I32_F128;
504 if (RetVT == MVT::ppcf128)
505 return SINTTOFP_I32_PPCF128;
506 } else if (OpVT == MVT::i64) {
507 if (RetVT == MVT::f32)
508 return SINTTOFP_I64_F32;
509 if (RetVT == MVT::f64)
510 return SINTTOFP_I64_F64;
511 if (RetVT == MVT::f80)
512 return SINTTOFP_I64_F80;
513 if (RetVT == MVT::f128)
514 return SINTTOFP_I64_F128;
515 if (RetVT == MVT::ppcf128)
516 return SINTTOFP_I64_PPCF128;
517 } else if (OpVT == MVT::i128) {
518 if (RetVT == MVT::f32)
519 return SINTTOFP_I128_F32;
520 if (RetVT == MVT::f64)
521 return SINTTOFP_I128_F64;
522 if (RetVT == MVT::f80)
523 return SINTTOFP_I128_F80;
524 if (RetVT == MVT::f128)
525 return SINTTOFP_I128_F128;
526 if (RetVT == MVT::ppcf128)
527 return SINTTOFP_I128_PPCF128;
528 }
529 return UNKNOWN_LIBCALL;
530 }
531
532 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
533 /// UNKNOWN_LIBCALL if there is none.
534 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
535 if (OpVT == MVT::i32) {
536 if (RetVT == MVT::f32)
537 return UINTTOFP_I32_F32;
538 if (RetVT == MVT::f64)
539 return UINTTOFP_I32_F64;
540 if (RetVT == MVT::f80)
541 return UINTTOFP_I32_F80;
542 if (RetVT == MVT::f128)
543 return UINTTOFP_I32_F128;
544 if (RetVT == MVT::ppcf128)
545 return UINTTOFP_I32_PPCF128;
546 } else if (OpVT == MVT::i64) {
547 if (RetVT == MVT::f32)
548 return UINTTOFP_I64_F32;
549 if (RetVT == MVT::f64)
550 return UINTTOFP_I64_F64;
551 if (RetVT == MVT::f80)
552 return UINTTOFP_I64_F80;
553 if (RetVT == MVT::f128)
554 return UINTTOFP_I64_F128;
555 if (RetVT == MVT::ppcf128)
556 return UINTTOFP_I64_PPCF128;
557 } else if (OpVT == MVT::i128) {
558 if (RetVT == MVT::f32)
559 return UINTTOFP_I128_F32;
560 if (RetVT == MVT::f64)
561 return UINTTOFP_I128_F64;
562 if (RetVT == MVT::f80)
563 return UINTTOFP_I128_F80;
564 if (RetVT == MVT::f128)
565 return UINTTOFP_I128_F128;
566 if (RetVT == MVT::ppcf128)
567 return UINTTOFP_I128_PPCF128;
568 }
569 return UNKNOWN_LIBCALL;
570 }
571
572 /// InitCmpLibcallCCs - Set default comparison libcall CC.
573 ///
574 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
575 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
576 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
577 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
578 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
579 CCs[RTLIB::UNE_F32] = ISD::SETNE;
580 CCs[RTLIB::UNE_F64] = ISD::SETNE;
581 CCs[RTLIB::UNE_F128] = ISD::SETNE;
582 CCs[RTLIB::OGE_F32] = ISD::SETGE;
583 CCs[RTLIB::OGE_F64] = ISD::SETGE;
584 CCs[RTLIB::OGE_F128] = ISD::SETGE;
585 CCs[RTLIB::OLT_F32] = ISD::SETLT;
586 CCs[RTLIB::OLT_F64] = ISD::SETLT;
587 CCs[RTLIB::OLT_F128] = ISD::SETLT;
588 CCs[RTLIB::OLE_F32] = ISD::SETLE;
589 CCs[RTLIB::OLE_F64] = ISD::SETLE;
590 CCs[RTLIB::OLE_F128] = ISD::SETLE;
591 CCs[RTLIB::OGT_F32] = ISD::SETGT;
592 CCs[RTLIB::OGT_F64] = ISD::SETGT;
593 CCs[RTLIB::OGT_F128] = ISD::SETGT;
594 CCs[RTLIB::UO_F32] = ISD::SETNE;
595 CCs[RTLIB::UO_F64] = ISD::SETNE;
596 CCs[RTLIB::UO_F128] = ISD::SETNE;
597 CCs[RTLIB::O_F32] = ISD::SETEQ;
598 CCs[RTLIB::O_F64] = ISD::SETEQ;
599 CCs[RTLIB::O_F128] = ISD::SETEQ;
600