llvm.org GIT mirror llvm / 69d3909
Two changes: 1. Treat FMOVD as a copy instruction, to help with coallescing in V9 mode 2. When in V9 mode, insert FMOVD instead of FpMOVD instructions, as we don't ever rewrite FpMOVD instructions into FMOVS instructions, thus we just end up with commented out copies! This should fix a bunch of failures in V9 mode on sparc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25961 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 13 years ago
10 changed file(s) with 48 addition(s) and 34 deletion(s). Raw diff Collapse all Expand all
1616 #include "SparcV8GenInstrInfo.inc"
1717 using namespace llvm;
1818
19 SparcV8InstrInfo::SparcV8InstrInfo()
20 : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])){
19 SparcV8InstrInfo::SparcV8InstrInfo(SparcV8Subtarget &ST)
20 : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])),
21 RI(ST) {
2122 }
2223
23 static bool isZeroImmed (const MachineOperand &op) {
24 return (op.isImmediate() && op.getImmedValue() == 0);
24 static bool isZeroImm(const MachineOperand &op) {
25 return op.isImmediate() && op.getImmedValue() == 0;
2526 }
2627
2728 /// Return true if the instruction is a register to register move and
4344 SrcReg = MI.getOperand(1).getReg();
4445 return true;
4546 }
46 } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) {
47 if (isZeroImmed(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
48 DstReg = MI.getOperand(0).getReg();
49 SrcReg = MI.getOperand(1).getReg();
50 return true;
51 }
52 } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD) {
47 } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri &&
48 isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
49 DstReg = MI.getOperand(0).getReg();
50 SrcReg = MI.getOperand(1).getReg();
51 return true;
52 } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD ||
53 MI.getOpcode() == V8::FMOVD) {
5354 SrcReg = MI.getOperand(1).getReg();
5455 DstReg = MI.getOperand(0).getReg();
5556 return true;
3333 class SparcV8InstrInfo : public TargetInstrInfo {
3434 const SparcV8RegisterInfo RI;
3535 public:
36 SparcV8InstrInfo();
36 SparcV8InstrInfo(SparcV8Subtarget &ST);
3737
3838 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
3939 /// such, whenever a client has an instance of instruction info, it should
1212
1313 #include "SparcV8.h"
1414 #include "SparcV8RegisterInfo.h"
15 #include "SparcV8Subtarget.h"
1516 #include "llvm/CodeGen/MachineInstrBuilder.h"
1617 #include "llvm/CodeGen/MachineFunction.h"
1718 #include "llvm/CodeGen/MachineFrameInfo.h"
2021 #include
2122 using namespace llvm;
2223
23 SparcV8RegisterInfo::SparcV8RegisterInfo()
24 SparcV8RegisterInfo::SparcV8RegisterInfo(SparcV8Subtarget &st)
2425 : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
25 V8::ADJCALLSTACKUP) {}
26 V8::ADJCALLSTACKUP), Subtarget(st) {
27 }
2628
2729 void SparcV8RegisterInfo::
2830 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
6264 else if (RC == V8::FPRegsRegisterClass)
6365 BuildMI(MBB, I, V8::FMOVS, 1, DestReg).addReg(SrcReg);
6466 else if (RC == V8::DFPRegsRegisterClass)
65 BuildMI(MBB, I, V8::FpMOVD, 1, DestReg).addReg(SrcReg);
67 BuildMI(MBB, I, Subtarget.isV9() ? V8::FMOVD : V8::FpMOVD,
68 1, DestReg).addReg(SrcReg);
6669 else
6770 assert (0 && "Can't copy this register");
6871 }
1818
1919 namespace llvm {
2020
21 class SparcV8Subtarget;
2122 class Type;
2223
2324 struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
24 SparcV8RegisterInfo();
25 SparcV8Subtarget &Subtarget;
26
27 SparcV8RegisterInfo(SparcV8Subtarget &st);
2528
2629 /// Code Generation virtual methods...
2730 void storeRegToStackSlot(MachineBasicBlock &MBB,
3434 IntrinsicLowering *IL,
3535 const std::string &FS)
3636 : TargetMachine("SparcV8", IL, false, 4, 4),
37 Subtarget(M, FS),
37 Subtarget(M, FS), InstrInfo(Subtarget),
3838 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
3939 }
4040
1616 #include "SparcV8GenInstrInfo.inc"
1717 using namespace llvm;
1818
19 SparcV8InstrInfo::SparcV8InstrInfo()
20 : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])){
19 SparcV8InstrInfo::SparcV8InstrInfo(SparcV8Subtarget &ST)
20 : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])),
21 RI(ST) {
2122 }
2223
23 static bool isZeroImmed (const MachineOperand &op) {
24 return (op.isImmediate() && op.getImmedValue() == 0);
24 static bool isZeroImm(const MachineOperand &op) {
25 return op.isImmediate() && op.getImmedValue() == 0;
2526 }
2627
2728 /// Return true if the instruction is a register to register move and
4344 SrcReg = MI.getOperand(1).getReg();
4445 return true;
4546 }
46 } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) {
47 if (isZeroImmed(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
48 DstReg = MI.getOperand(0).getReg();
49 SrcReg = MI.getOperand(1).getReg();
50 return true;
51 }
52 } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD) {
47 } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri &&
48 isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
49 DstReg = MI.getOperand(0).getReg();
50 SrcReg = MI.getOperand(1).getReg();
51 return true;
52 } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD ||
53 MI.getOpcode() == V8::FMOVD) {
5354 SrcReg = MI.getOperand(1).getReg();
5455 DstReg = MI.getOperand(0).getReg();
5556 return true;
3333 class SparcV8InstrInfo : public TargetInstrInfo {
3434 const SparcV8RegisterInfo RI;
3535 public:
36 SparcV8InstrInfo();
36 SparcV8InstrInfo(SparcV8Subtarget &ST);
3737
3838 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
3939 /// such, whenever a client has an instance of instruction info, it should
1212
1313 #include "SparcV8.h"
1414 #include "SparcV8RegisterInfo.h"
15 #include "SparcV8Subtarget.h"
1516 #include "llvm/CodeGen/MachineInstrBuilder.h"
1617 #include "llvm/CodeGen/MachineFunction.h"
1718 #include "llvm/CodeGen/MachineFrameInfo.h"
2021 #include
2122 using namespace llvm;
2223
23 SparcV8RegisterInfo::SparcV8RegisterInfo()
24 SparcV8RegisterInfo::SparcV8RegisterInfo(SparcV8Subtarget &st)
2425 : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
25 V8::ADJCALLSTACKUP) {}
26 V8::ADJCALLSTACKUP), Subtarget(st) {
27 }
2628
2729 void SparcV8RegisterInfo::
2830 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
6264 else if (RC == V8::FPRegsRegisterClass)
6365 BuildMI(MBB, I, V8::FMOVS, 1, DestReg).addReg(SrcReg);
6466 else if (RC == V8::DFPRegsRegisterClass)
65 BuildMI(MBB, I, V8::FpMOVD, 1, DestReg).addReg(SrcReg);
67 BuildMI(MBB, I, Subtarget.isV9() ? V8::FMOVD : V8::FpMOVD,
68 1, DestReg).addReg(SrcReg);
6669 else
6770 assert (0 && "Can't copy this register");
6871 }
1818
1919 namespace llvm {
2020
21 class SparcV8Subtarget;
2122 class Type;
2223
2324 struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
24 SparcV8RegisterInfo();
25 SparcV8Subtarget &Subtarget;
26
27 SparcV8RegisterInfo(SparcV8Subtarget &st);
2528
2629 /// Code Generation virtual methods...
2730 void storeRegToStackSlot(MachineBasicBlock &MBB,
3434 IntrinsicLowering *IL,
3535 const std::string &FS)
3636 : TargetMachine("SparcV8", IL, false, 4, 4),
37 Subtarget(M, FS),
37 Subtarget(M, FS), InstrInfo(Subtarget),
3838 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
3939 }
4040