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AArch64: TableGenerate system instruction operands. The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274576 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 3 years ago
21 changed file(s) with 1708 addition(s) and 2043 deletion(s). Raw diff Collapse all Expand all
0 //===- SearchableTable.td ----------------------------------*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the key top-level classes needed to produce a reasonably
10 // generic table that can be binary-searched via int and string entries.
11 //
12 // Each table must instantiate "Mappingkind", listing the fields that should be
13 // included and fields that shoould be searchable. Only two kinds of fields are
14 // searchable at the moment: "strings" (which are compared case-insensitively),
15 // and "bits".
16 //
17 // For each "MappingKind" the generated header will create GET_MAPPINGKIND_DECL
18 // and GET_MAPPINGKIND_IMPL guards.
19 //
20 // Inside the DECL guard will be a set of function declarations:
21 // "lookup{InstanceClass}By{SearchableField}", returning "const {InstanceClass}
22 // *" and accepting either a StringRef or a uintN_t. Additionally, if
23 // EnumNameField is still defined, there will be an "enum {InstanceClass}Values"
24 // allowing C++ code to reference either the primary data table's entries (if
25 // EnumValueField is not defined) or some other field (e.g. encoding) if it is.
26 //
27 // Inside the IMPL guard will be a primary data table "{InstanceClass}sList" and
28 // as many searchable indexes as requested
29 // ("{InstanceClass}sBy{SearchableField}"). Additionally implementations of the
30 // lookup function will be provided.
31 //
32 // See AArch64SystemOperands.td and its generated header for example uses.
33 //
34 //===----------------------------------------------------------------------===//
35
36 class SearchableTable {
37 list SearchableFields;
38 string EnumNameField = "Name";
39 string EnumValueField;
40 }
129129 include "AArch64InstrInfo.td"
130130
131131 def AArch64InstrInfo : InstrInfo;
132
133 //===----------------------------------------------------------------------===//
134 // Named operands for MRS/MSR/TLBI/...
135 //===----------------------------------------------------------------------===//
136
137 include "AArch64SystemOperands.td"
132138
133139 //===----------------------------------------------------------------------===//
134140 // AArch64 Processors supported.
24372437
24382438 // Use the sysreg mapper to map the remaining possible strings to the
24392439 // value for the register to be used for the instruction operand.
2440 AArch64SysReg::MRSMapper mapper;
2441 bool IsValidSpecialReg;
2442 Reg = mapper.fromString(RegString->getString(),
2443 Subtarget->getFeatureBits(),
2444 IsValidSpecialReg);
2445 if (IsValidSpecialReg) {
2440 auto TheReg = AArch64SysReg::lookupSysRegByName(RegString->getString());
2441 if (TheReg && TheReg->Readable &&
2442 TheReg->haveFeatures(Subtarget->getFeatureBits()))
2443 Reg = TheReg->Encoding;
2444 else
2445 Reg = AArch64SysReg::parseGenericRegister(RegString->getString());
2446
2447 if (Reg != -1) {
24462448 ReplaceNode(N, CurDAG->getMachineNode(
24472449 AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other,
24482450 CurDAG->getTargetConstant(Reg, DL, MVT::i32),
24762478 // pstatefield for the MSR (immediate) instruction, we also require that an
24772479 // immediate value has been provided as an argument, we know that this is
24782480 // the case as it has been ensured by semantic checking.
2479 AArch64PState::PStateMapper PMapper;
2480 bool IsValidSpecialReg;
2481 Reg = PMapper.fromString(RegString->getString(),
2482 Subtarget->getFeatureBits(),
2483 IsValidSpecialReg);
2484 if (IsValidSpecialReg) {
2481 auto PMapper = AArch64PState::lookupPStateByName(RegString->getString());;
2482 if (PMapper) {
24852483 assert (isa(N->getOperand(2))
24862484 && "Expected a constant integer expression.");
2485 unsigned Reg = PMapper->Encoding;
24872486 uint64_t Immed = cast(N->getOperand(2))->getZExtValue();
24882487 unsigned State;
24892488 if (Reg == AArch64PState::PAN || Reg == AArch64PState::UAO) {
25042503 // Use the sysreg mapper to attempt to map the remaining possible strings
25052504 // to the value for the register to be used for the MSR (register)
25062505 // instruction operand.
2507 AArch64SysReg::MSRMapper Mapper;
2508 Reg = Mapper.fromString(RegString->getString(),
2509 Subtarget->getFeatureBits(),
2510 IsValidSpecialReg);
2511
2512 if (IsValidSpecialReg) {
2513 ReplaceNode(
2514 N, CurDAG->getMachineNode(AArch64::MSR, DL, MVT::Other,
2515 CurDAG->getTargetConstant(Reg, DL, MVT::i32),
2516 N->getOperand(2), N->getOperand(0)));
2506 auto TheReg = AArch64SysReg::lookupSysRegByName(RegString->getString());
2507 if (TheReg && TheReg->Writeable &&
2508 TheReg->haveFeatures(Subtarget->getFeatureBits()))
2509 Reg = TheReg->Encoding;
2510 else
2511 Reg = AArch64SysReg::parseGenericRegister(RegString->getString());
2512 if (Reg != -1) {
2513 ReplaceNode(N, CurDAG->getMachineNode(
2514 AArch64::MSR, DL, MVT::Other,
2515 CurDAG->getTargetConstant(Reg, DL, MVT::i32),
2516 N->getOperand(2), N->getOperand(0)));
25172517 return true;
25182518 }
25192519
922922 // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.
923923 if (!MCOp.isImm())
924924 return false;
925 bool ValidNamed;
926 (void)AArch64PSBHint::PSBHintMapper().toString(MCOp.getImm(),
927 STI.getFeatureBits(), ValidNamed);
928 return ValidNamed;
925 return AArch64PSBHint::lookupPSBByEncoding(MCOp.getImm()) != nullptr;
929926 }];
930927 }
931928
0 //===- AArch64SystemOperands.td ----------------------------*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the symbolic operands permitted for various kinds of
10 // AArch64 system instruction.
11 //
12 //===----------------------------------------------------------------------===//
13
14 include "llvm/TableGen/SearchableTable.td"
15
16 //===----------------------------------------------------------------------===//
17 // AT (address translate) instruction options.
18 //===----------------------------------------------------------------------===//
19
20 class AT op0, bits<3> op1, bits<4> crn, bits<4> crm,
21 bits<3> op2> : SearchableTable {
22 let SearchableFields = ["Name", "Encoding"];
23 let EnumValueField = "Encoding";
24
25 string Name = name;
26 bits<16> Encoding;
27 let Encoding{15-14} = op0;
28 let Encoding{13-11} = op1;
29 let Encoding{10-7} = crn;
30 let Encoding{6-3} = crm;
31 let Encoding{2-0} = op2;
32 }
33
34 def : AT<"S1E1R", 0b01, 0b000, 0b0111, 0b1000, 0b000>;
35 def : AT<"S1E2R", 0b01, 0b100, 0b0111, 0b1000, 0b000>;
36 def : AT<"S1E3R", 0b01, 0b110, 0b0111, 0b1000, 0b000>;
37 def : AT<"S1E1W", 0b01, 0b000, 0b0111, 0b1000, 0b001>;
38 def : AT<"S1E2W", 0b01, 0b100, 0b0111, 0b1000, 0b001>;
39 def : AT<"S1E3W", 0b01, 0b110, 0b0111, 0b1000, 0b001>;
40 def : AT<"S1E0R", 0b01, 0b000, 0b0111, 0b1000, 0b010>;
41 def : AT<"S1E0W", 0b01, 0b000, 0b0111, 0b1000, 0b011>;
42 def : AT<"S12E1R", 0b01, 0b100, 0b0111, 0b1000, 0b100>;
43 def : AT<"S12E1W", 0b01, 0b100, 0b0111, 0b1000, 0b101>;
44 def : AT<"S12E0R", 0b01, 0b100, 0b0111, 0b1000, 0b110>;
45 def : AT<"S12E0W", 0b01, 0b100, 0b0111, 0b1000, 0b111>;
46 def : AT<"S1E1RP", 0b01, 0b000, 0b0111, 0b1001, 0b000>;
47 def : AT<"S1E1WP", 0b01, 0b000, 0b0111, 0b1001, 0b001>;
48
49
50 //===----------------------------------------------------------------------===//
51 // DMB/DSB (data barrier) instruction options.
52 //===----------------------------------------------------------------------===//
53
54 class DB encoding> : SearchableTable {
55 let SearchableFields = ["Name", "Encoding"];
56 let EnumValueField = "Encoding";
57
58 string Name = name;
59 bits<4> Encoding = encoding;
60 }
61
62 def : DB<"oshld", 0x1>;
63 def : DB<"oshst", 0x2>;
64 def : DB<"osh", 0x3>;
65 def : DB<"nshld", 0x5>;
66 def : DB<"nshst", 0x6>;
67 def : DB<"nsh", 0x7>;
68 def : DB<"ishld", 0x9>;
69 def : DB<"ishst", 0xa>;
70 def : DB<"ish", 0xb>;
71 def : DB<"ld", 0xd>;
72 def : DB<"st", 0xe>;
73 def : DB<"sy", 0xf>;
74
75 //===----------------------------------------------------------------------===//
76 // DC (data cache maintenance) instruction options.
77 //===----------------------------------------------------------------------===//
78
79 class DC op0, bits<3> op1, bits<4> crn, bits<4> crm,
80 bits<3> op2> : SearchableTable {
81 let SearchableFields = ["Name", "Encoding"];
82 let EnumValueField = "Encoding";
83
84 string Name = name;
85 bits<16> Encoding;
86 let Encoding{15-14} = op0;
87 let Encoding{13-11} = op1;
88 let Encoding{10-7} = crn;
89 let Encoding{6-3} = crm;
90 let Encoding{2-0} = op2;
91 }
92
93 def : DC<"ZVA", 0b01, 0b011, 0b0111, 0b0100, 0b001>;
94 def : DC<"IVAC", 0b01, 0b000, 0b0111, 0b0110, 0b001>;
95 def : DC<"ISW", 0b01, 0b000, 0b0111, 0b0110, 0b010>;
96 def : DC<"CVAC", 0b01, 0b011, 0b0111, 0b1010, 0b001>;
97 def : DC<"CSW", 0b01, 0b000, 0b0111, 0b1010, 0b010>;
98 def : DC<"CVAU", 0b01, 0b011, 0b0111, 0b1011, 0b001>;
99 def : DC<"CIVAC", 0b01, 0b011, 0b0111, 0b1110, 0b001>;
100 def : DC<"CISW", 0b01, 0b000, 0b0111, 0b1110, 0b010>;
101
102 //===----------------------------------------------------------------------===//
103 // IC (instruction cache maintenance) instruction options.
104 //===----------------------------------------------------------------------===//
105
106 class IC op1, bits<4> crn, bits<4> crm, bits<3> op2,
107 bit needsreg> : SearchableTable {
108 let SearchableFields = ["Name", "Encoding"];
109 let EnumValueField = "Encoding";
110
111 string Name = name;
112 bits<14> Encoding;
113 let Encoding{13-11} = op1;
114 let Encoding{10-7} = crn;
115 let Encoding{6-3} = crm;
116 let Encoding{2-0} = op2;
117 bit NeedsReg = needsreg;
118 }
119
120 def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>;
121 def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>;
122 def : IC<"IVAU", 0b000, 0b0111, 0b0001, 0b000, 1>;
123
124 //===----------------------------------------------------------------------===//
125 // ISB (instruction-fetch barrier) instruction options.
126 //===----------------------------------------------------------------------===//
127
128 class ISB encoding> : SearchableTable{
129 let SearchableFields = ["Name", "Encoding"];
130 let EnumValueField = "Encoding";
131
132 string Name = name;
133 bits<4> Encoding;
134 let Encoding = encoding;
135 }
136
137 def : ISB<"sy", 0xf>;
138
139 //===----------------------------------------------------------------------===//
140 // PRFM (prefetch) instruction options.
141 //===----------------------------------------------------------------------===//
142
143 class PRFM encoding> : SearchableTable {
144 let SearchableFields = ["Name", "Encoding"];
145 let EnumValueField = "Encoding";
146
147 string Name = name;
148 bits<5> Encoding;
149 let Encoding = encoding;
150 }
151
152 def : PRFM<"pldl1keep", 0x00>;
153 def : PRFM<"pldl1strm", 0x01>;
154 def : PRFM<"pldl2keep", 0x02>;
155 def : PRFM<"pldl2strm", 0x03>;
156 def : PRFM<"pldl3keep", 0x04>;
157 def : PRFM<"pldl3strm", 0x05>;
158 def : PRFM<"plil1keep", 0x08>;
159 def : PRFM<"plil1strm", 0x09>;
160 def : PRFM<"plil2keep", 0x0a>;
161 def : PRFM<"plil2strm", 0x0b>;
162 def : PRFM<"plil3keep", 0x0c>;
163 def : PRFM<"plil3strm", 0x0d>;
164 def : PRFM<"pstl1keep", 0x10>;
165 def : PRFM<"pstl1strm", 0x11>;
166 def : PRFM<"pstl2keep", 0x12>;
167 def : PRFM<"pstl2strm", 0x13>;
168 def : PRFM<"pstl3keep", 0x14>;
169 def : PRFM<"pstl3strm", 0x15>;
170
171 //===----------------------------------------------------------------------===//
172 // PState instruction options.
173 //===----------------------------------------------------------------------===//
174
175 class PState encoding> : SearchableTable {
176 let SearchableFields = ["Name", "Encoding"];
177 let EnumValueField = "Encoding";
178
179 string Name = name;
180 bits<5> Encoding;
181 let Encoding = encoding;
182 code Requires = [{ {} }];
183 }
184
185 def : PState<"SPSel", 0b00101>;
186 def : PState<"DAIFSet", 0b11110>;
187 def : PState<"DAIFClr", 0b11111>;
188 // v8.1a "Privileged Access Never" extension-specific PStates
189 let Requires = [{ {AArch64::HasV8_1aOps} }] in
190 def : PState<"PAN", 0b00100>;
191 // v8.2a "User Access Override" extension-specific PStates
192 let Requires = [{ {AArch64::HasV8_2aOps} }] in
193 def : PState<"UAO", 0b00011>;
194
195
196 //===----------------------------------------------------------------------===//
197 // PSB instruction options.
198 //===----------------------------------------------------------------------===//
199
200 class PSB encoding> : SearchableTable {
201 let SearchableFields = ["Name", "Encoding"];
202 let EnumValueField = "Encoding";
203
204 string Name = name;
205 bits<5> Encoding;
206 let Encoding = encoding;
207 }
208
209 def : PSB<"csync", 0x11>;
210
211 //===----------------------------------------------------------------------===//
212 // TLBI (translation lookaside buffer invalidate) instruction options.
213 //===----------------------------------------------------------------------===//
214
215 class TLBI op0, bits<3> op1, bits<4> crn, bits<4> crm,
216 bits<3> op2, bit needsreg = 1> : SearchableTable {
217 let SearchableFields = ["Name", "Encoding"];
218 let EnumValueField = "Encoding";
219
220 string Name = name;
221 bits<16> Encoding;
222 let Encoding{15-14} = op0;
223 let Encoding{13-11} = op1;
224 let Encoding{10-7} = crn;
225 let Encoding{6-3} = crm;
226 let Encoding{2-0} = op2;
227 bit NeedsReg = needsreg;
228 }
229
230 def : TLBI<"IPAS2E1IS", 0b01, 0b100, 0b1000, 0b0000, 0b001>;
231 def : TLBI<"IPAS2LE1IS", 0b01, 0b100, 0b1000, 0b0000, 0b101>;
232 def : TLBI<"VMALLE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b000, 0>;
233 def : TLBI<"ALLE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b000, 0>;
234 def : TLBI<"ALLE3IS", 0b01, 0b110, 0b1000, 0b0011, 0b000, 0>;
235 def : TLBI<"VAE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b001>;
236 def : TLBI<"VAE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b001>;
237 def : TLBI<"VAE3IS", 0b01, 0b110, 0b1000, 0b0011, 0b001>;
238 def : TLBI<"ASIDE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b010>;
239 def : TLBI<"VAAE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b011>;
240 def : TLBI<"ALLE1IS", 0b01, 0b100, 0b1000, 0b0011, 0b100, 0>;
241 def : TLBI<"VALE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b101>;
242 def : TLBI<"VALE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b101>;
243 def : TLBI<"VALE3IS", 0b01, 0b110, 0b1000, 0b0011, 0b101>;
244 def : TLBI<"VMALLS12E1IS", 0b01, 0b100, 0b1000, 0b0011, 0b110, 0>;
245 def : TLBI<"VAALE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b111>;
246 def : TLBI<"IPAS2E1", 0b01, 0b100, 0b1000, 0b0100, 0b001>;
247 def : TLBI<"IPAS2LE1", 0b01, 0b100, 0b1000, 0b0100, 0b101>;
248 def : TLBI<"VMALLE1", 0b01, 0b000, 0b1000, 0b0111, 0b000, 0>;
249 def : TLBI<"ALLE2", 0b01, 0b100, 0b1000, 0b0111, 0b000, 0>;
250 def : TLBI<"ALLE3", 0b01, 0b110, 0b1000, 0b0111, 0b000, 0>;
251 def : TLBI<"VAE1", 0b01, 0b000, 0b1000, 0b0111, 0b001>;
252 def : TLBI<"VAE2", 0b01, 0b100, 0b1000, 0b0111, 0b001>;
253 def : TLBI<"VAE3", 0b01, 0b110, 0b1000, 0b0111, 0b001>;
254 def : TLBI<"ASIDE1", 0b01, 0b000, 0b1000, 0b0111, 0b010>;
255 def : TLBI<"VAAE1", 0b01, 0b000, 0b1000, 0b0111, 0b011>;
256 def : TLBI<"ALLE1", 0b01, 0b100, 0b1000, 0b0111, 0b100, 0>;
257 def : TLBI<"VALE1", 0b01, 0b000, 0b1000, 0b0111, 0b101>;
258 def : TLBI<"VALE2", 0b01, 0b100, 0b1000, 0b0111, 0b101>;
259 def : TLBI<"VALE3", 0b01, 0b110, 0b1000, 0b0111, 0b101>;
260 def : TLBI<"VMALLS12E1", 0b01, 0b100, 0b1000, 0b0111, 0b110, 0>;
261 def : TLBI<"VAALE1", 0b01, 0b000, 0b1000, 0b0111, 0b111>;
262
263
264 //===----------------------------------------------------------------------===//
265 // MRS/MSR (system register read/write) instruction options.
266 //===----------------------------------------------------------------------===//
267
268 class SysReg op0, bits<3> op1, bits<4> crn, bits<4> crm,
269 bits<3> op2> : SearchableTable {
270 let SearchableFields = ["Name", "Encoding"];
271 let EnumValueField = "Encoding";
272
273 string Name = name;
274 bits<16> Encoding;
275 let Encoding{15-14} = op0;
276 let Encoding{13-11} = op1;
277 let Encoding{10-7} = crn;
278 let Encoding{6-3} = crm;
279 let Encoding{2-0} = op2;
280 bit Readable = ?;
281 bit Writeable = ?;
282 code Requires = [{ {} }];
283 }
284
285 class RWSysReg op0, bits<3> op1, bits<4> crn, bits<4> crm,
286 bits<3> op2>
287 : SysReg {
288 let Readable = 1;
289 let Writeable = 1;
290 }
291
292 class ROSysReg op0, bits<3> op1, bits<4> crn, bits<4> crm,
293 bits<3> op2>
294 : SysReg {
295 let Readable = 1;
296 let Writeable = 0;
297 }
298
299 class WOSysReg op0, bits<3> op1, bits<4> crn, bits<4> crm,
300 bits<3> op2>
301 : SysReg {
302 let Readable = 0;
303 let Writeable = 1;
304 }
305
306 //===----------------------
307 // Read-only regs
308 //===----------------------
309
310 // Op0 Op1 CRn CRm Op2
311 def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>;
312 def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;
313 def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>;
314 def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>;
315 def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>;
316 def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
317 def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
318 def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>;
319 def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>;
320 def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>;
321 def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>;
322 def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>;
323 def : ROSysReg<"REVIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b110>;
324 def : ROSysReg<"AIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b111>;
325 def : ROSysReg<"DCZID_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b111>;
326 def : ROSysReg<"ID_PFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b000>;
327 def : ROSysReg<"ID_PFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b001>;
328 def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>;
329 def : ROSysReg<"ID_AFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b011>;
330 def : ROSysReg<"ID_MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b100>;
331 def : ROSysReg<"ID_MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b101>;
332 def : ROSysReg<"ID_MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b110>;
333 def : ROSysReg<"ID_MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b111>;
334 def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>;
335 def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>;
336 def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>;
337 def : ROSysReg<"ID_ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b011>;
338 def : ROSysReg<"ID_ISAR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b100>;
339 def : ROSysReg<"ID_ISAR5_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b101>;
340 def : ROSysReg<"ID_AA64PFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b000>;
341 def : ROSysReg<"ID_AA64PFR1_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b001>;
342 def : ROSysReg<"ID_AA64DFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b000>;
343 def : ROSysReg<"ID_AA64DFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b001>;
344 def : ROSysReg<"ID_AA64AFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b100>;
345 def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>;
346 def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>;
347 def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>;
348 def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>;
349 def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>;
350 def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010> {
351 let Requires = [{ {AArch64::HasV8_2aOps} }];
352 }
353 def : ROSysReg<"MVFR0_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b000>;
354 def : ROSysReg<"MVFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b001>;
355 def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>;
356 def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>;
357 def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>;
358 def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>;
359 def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>;
360 def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>;
361 def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>;
362 def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>;
363
364 // Trace registers
365 // Op0 Op1 CRn CRm Op2
366 def : ROSysReg<"TRCSTATR", 0b10, 0b001, 0b0000, 0b0011, 0b000>;
367 def : ROSysReg<"TRCIDR8", 0b10, 0b001, 0b0000, 0b0000, 0b110>;
368 def : ROSysReg<"TRCIDR9", 0b10, 0b001, 0b0000, 0b0001, 0b110>;
369 def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>;
370 def : ROSysReg<"TRCIDR11", 0b10, 0b001, 0b0000, 0b0011, 0b110>;
371 def : ROSysReg<"TRCIDR12", 0b10, 0b001, 0b0000, 0b0100, 0b110>;
372 def : ROSysReg<"TRCIDR13", 0b10, 0b001, 0b0000, 0b0101, 0b110>;
373 def : ROSysReg<"TRCIDR0", 0b10, 0b001, 0b0000, 0b1000, 0b111>;
374 def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>;
375 def : ROSysReg<"TRCIDR2", 0b10, 0b001, 0b0000, 0b1010, 0b111>;
376 def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>;
377 def : ROSysReg<"TRCIDR4", 0b10, 0b001, 0b0000, 0b1100, 0b111>;
378 def : ROSysReg<"TRCIDR5", 0b10, 0b001, 0b0000, 0b1101, 0b111>;
379 def : ROSysReg<"TRCIDR6", 0b10, 0b001, 0b0000, 0b1110, 0b111>;
380 def : ROSysReg<"TRCIDR7", 0b10, 0b001, 0b0000, 0b1111, 0b111>;
381 def : ROSysReg<"TRCOSLSR", 0b10, 0b001, 0b0001, 0b0001, 0b100>;
382 def : ROSysReg<"TRCPDSR", 0b10, 0b001, 0b0001, 0b0101, 0b100>;
383 def : ROSysReg<"TRCDEVAFF0", 0b10, 0b001, 0b0111, 0b1010, 0b110>;
384 def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>;
385 def : ROSysReg<"TRCLSR", 0b10, 0b001, 0b0111, 0b1101, 0b110>;
386 def : ROSysReg<"TRCAUTHSTATUS", 0b10, 0b001, 0b0111, 0b1110, 0b110>;
387 def : ROSysReg<"TRCDEVARCH", 0b10, 0b001, 0b0111, 0b1111, 0b110>;
388 def : ROSysReg<"TRCDEVID", 0b10, 0b001, 0b0111, 0b0010, 0b111>;
389 def : ROSysReg<"TRCDEVTYPE", 0b10, 0b001, 0b0111, 0b0011, 0b111>;
390 def : ROSysReg<"TRCPIDR4", 0b10, 0b001, 0b0111, 0b0100, 0b111>;
391 def : ROSysReg<"TRCPIDR5", 0b10, 0b001, 0b0111, 0b0101, 0b111>;
392 def : ROSysReg<"TRCPIDR6", 0b10, 0b001, 0b0111, 0b0110, 0b111>;
393 def : ROSysReg<"TRCPIDR7", 0b10, 0b001, 0b0111, 0b0111, 0b111>;
394 def : ROSysReg<"TRCPIDR0", 0b10, 0b001, 0b0111, 0b1000, 0b111>;
395 def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>;
396 def : ROSysReg<"TRCPIDR2", 0b10, 0b001, 0b0111, 0b1010, 0b111>;
397 def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>;
398 def : ROSysReg<"TRCCIDR0", 0b10, 0b001, 0b0111, 0b1100, 0b111>;
399 def : ROSysReg<"TRCCIDR1", 0b10, 0b001, 0b0111, 0b1101, 0b111>;
400 def : ROSysReg<"TRCCIDR2", 0b10, 0b001, 0b0111, 0b1110, 0b111>;
401 def : ROSysReg<"TRCCIDR3", 0b10, 0b001, 0b0111, 0b1111, 0b111>;
402
403 // GICv3 registers
404 // Op0 Op1 CRn CRm Op2
405 def : ROSysReg<"ICC_IAR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b000>;
406 def : ROSysReg<"ICC_IAR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b000>;
407 def : ROSysReg<"ICC_HPPIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b010>;
408 def : ROSysReg<"ICC_HPPIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b010>;
409 def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>;
410 def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>;
411 def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>;
412 def : ROSysReg<"ICH_ELSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>;
413
414 // v8.1a "Limited Ordering Regions" extension-specific system register
415 // Op0 Op1 CRn CRm Op2
416 let Requires = [{ {AArch64::HasV8_1aOps} }] in
417 def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>;
418
419 // v8.2a "RAS extension" registers
420 // Op0 Op1 CRn CRm Op2
421 let Requires = [{ {AArch64::FeatureRAS} }] in {
422 def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b000>;
423 def : ROSysReg<"ERXFR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b000>;
424 }
425
426 //===----------------------
427 // Write-only regs
428 //===----------------------
429
430 // Op0 Op1 CRn CRm Op2
431 def : WOSysReg<"DBGDTRTX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;
432 def : WOSysReg<"OSLAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b100>;
433 def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>;
434
435 // Trace Registers
436 // Op0 Op1 CRn CRm Op2
437 def : WOSysReg<"TRCOSLAR", 0b10, 0b001, 0b0001, 0b0000, 0b100>;
438 def : WOSysReg<"TRCLAR", 0b10, 0b001, 0b0111, 0b1100, 0b110>;
439
440 // GICv3 registers
441 // Op0 Op1 CRn CRm Op2
442 def : WOSysReg<"ICC_EOIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b001>;
443 def : WOSysReg<"ICC_EOIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b001>;
444 def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>;
445 def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>;
446 def : WOSysReg<"ICC_ASGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b110>;
447 def : WOSysReg<"ICC_SGI0R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b111>;
448
449 //===----------------------
450 // Read-write regs
451 //===----------------------
452
453 // Op0 Op1 CRn CRm Op2
454 def : RWSysReg<"OSDTRRX_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b010>;
455 def : RWSysReg<"OSDTRTX_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b010>;
456 def : RWSysReg<"TEECR32_EL1", 0b10, 0b010, 0b0000, 0b0000, 0b000>;
457 def : RWSysReg<"MDCCINT_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b000>;
458 def : RWSysReg<"MDSCR_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b010>;
459 def : RWSysReg<"DBGDTR_EL0", 0b10, 0b011, 0b0000, 0b0100, 0b000>;
460 def : RWSysReg<"OSECCR_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b010>;
461 def : RWSysReg<"DBGVCR32_EL2", 0b10, 0b100, 0b0000, 0b0111, 0b000>;
462 def : RWSysReg<"DBGBVR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b100>;
463 def : RWSysReg<"DBGBVR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b100>;
464 def : RWSysReg<"DBGBVR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b100>;
465 def : RWSysReg<"DBGBVR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b100>;
466 def : RWSysReg<"DBGBVR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b100>;
467 def : RWSysReg<"DBGBVR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b100>;
468 def : RWSysReg<"DBGBVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b100>;
469 def : RWSysReg<"DBGBVR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b100>;
470 def : RWSysReg<"DBGBVR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b100>;
471 def : RWSysReg<"DBGBVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b100>;
472 def : RWSysReg<"DBGBVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b100>;
473 def : RWSysReg<"DBGBVR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b100>;
474 def : RWSysReg<"DBGBVR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b100>;
475 def : RWSysReg<"DBGBVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b100>;
476 def : RWSysReg<"DBGBVR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b100>;
477 def : RWSysReg<"DBGBVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b100>;
478 def : RWSysReg<"DBGBCR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b101>;
479 def : RWSysReg<"DBGBCR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b101>;
480 def : RWSysReg<"DBGBCR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b101>;
481 def : RWSysReg<"DBGBCR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b101>;
482 def : RWSysReg<"DBGBCR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b101>;
483 def : RWSysReg<"DBGBCR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b101>;
484 def : RWSysReg<"DBGBCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b101>;
485 def : RWSysReg<"DBGBCR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b101>;
486 def : RWSysReg<"DBGBCR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b101>;
487 def : RWSysReg<"DBGBCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b101>;
488 def : RWSysReg<"DBGBCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b101>;
489 def : RWSysReg<"DBGBCR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b101>;
490 def : RWSysReg<"DBGBCR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b101>;
491 def : RWSysReg<"DBGBCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b101>;
492 def : RWSysReg<"DBGBCR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b101>;
493 def : RWSysReg<"DBGBCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b101>;
494 def : RWSysReg<"DBGWVR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b110>;
495 def : RWSysReg<"DBGWVR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b110>;
496 def : RWSysReg<"DBGWVR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b110>;
497 def : RWSysReg<"DBGWVR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b110>;
498 def : RWSysReg<"DBGWVR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b110>;
499 def : RWSysReg<"DBGWVR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b110>;
500 def : RWSysReg<"DBGWVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b110>;
501 def : RWSysReg<"DBGWVR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b110>;
502 def : RWSysReg<"DBGWVR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b110>;
503 def : RWSysReg<"DBGWVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b110>;
504 def : RWSysReg<"DBGWVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b110>;
505 def : RWSysReg<"DBGWVR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b110>;
506 def : RWSysReg<"DBGWVR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b110>;
507 def : RWSysReg<"DBGWVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b110>;
508 def : RWSysReg<"DBGWVR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b110>;
509 def : RWSysReg<"DBGWVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b110>;
510 def : RWSysReg<"DBGWCR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b111>;
511 def : RWSysReg<"DBGWCR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b111>;
512 def : RWSysReg<"DBGWCR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b111>;
513 def : RWSysReg<"DBGWCR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b111>;
514 def : RWSysReg<"DBGWCR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b111>;
515 def : RWSysReg<"DBGWCR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b111>;
516 def : RWSysReg<"DBGWCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b111>;
517 def : RWSysReg<"DBGWCR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b111>;
518 def : RWSysReg<"DBGWCR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b111>;
519 def : RWSysReg<"DBGWCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b111>;
520 def : RWSysReg<"DBGWCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b111>;
521 def : RWSysReg<"DBGWCR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b111>;
522 def : RWSysReg<"DBGWCR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b111>;
523 def : RWSysReg<"DBGWCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b111>;
524 def : RWSysReg<"DBGWCR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b111>;
525 def : RWSysReg<"DBGWCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b111>;
526 def : RWSysReg<"TEEHBR32_EL1", 0b10, 0b010, 0b0001, 0b0000, 0b000>;
527 def : RWSysReg<"OSDLR_EL1", 0b10, 0b000, 0b0001, 0b0011, 0b100>;
528 def : RWSysReg<"DBGPRCR_EL1", 0b10, 0b000, 0b0001, 0b0100, 0b100>;
529 def : RWSysReg<"DBGCLAIMSET_EL1", 0b10, 0b000, 0b0111, 0b1000, 0b110>;
530 def : RWSysReg<"DBGCLAIMCLR_EL1", 0b10, 0b000, 0b0111, 0b1001, 0b110>;
531 def : RWSysReg<"CSSELR_EL1", 0b11, 0b010, 0b0000, 0b0000, 0b000>;
532 def : RWSysReg<"VPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b000>;
533 def : RWSysReg<"VMPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b101>;
534 def : RWSysReg<"CPACR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b010>;
535 def : RWSysReg<"SCTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b000>;
536 def : RWSysReg<"SCTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b000>;
537 def : RWSysReg<"SCTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b000>;
538 def : RWSysReg<"ACTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b001>;
539 def : RWSysReg<"ACTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b001>;
540 def : RWSysReg<"ACTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b001>;
541 def : RWSysReg<"HCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b000>;
542 def : RWSysReg<"SCR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b000>;
543 def : RWSysReg<"MDCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b001>;
544 def : RWSysReg<"SDER32_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b001>;
545 def : RWSysReg<"CPTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b010>;
546 def : RWSysReg<"CPTR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b010>;
547 def : RWSysReg<"HSTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b011>;
548 def : RWSysReg<"HACR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b111>;
549 def : RWSysReg<"MDCR_EL3", 0b11, 0b110, 0b0001, 0b0011, 0b001>;
550 def : RWSysReg<"TTBR0_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b000>;
551 def : RWSysReg<"TTBR0_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000>;
552 def : RWSysReg<"TTBR0_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b000>;
553 def : RWSysReg<"TTBR1_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b001>;
554 def : RWSysReg<"TCR_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b010>;
555 def : RWSysReg<"TCR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b010>;
556 def : RWSysReg<"TCR_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b010>;
557 def : RWSysReg<"VTTBR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b000>;
558 def : RWSysReg<"VTCR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b010>;
559 def : RWSysReg<"DACR32_EL2", 0b11, 0b100, 0b0011, 0b0000, 0b000>;
560 def : RWSysReg<"SPSR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b000>;
561 def : RWSysReg<"SPSR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b000>;
562 def : RWSysReg<"SPSR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b000>;
563 def : RWSysReg<"ELR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b001>;
564 def : RWSysReg<"ELR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b001>;
565 def : RWSysReg<"ELR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b001>;
566 def : RWSysReg<"SP_EL0", 0b11, 0b000, 0b0100, 0b0001, 0b000>;
567 def : RWSysReg<"SP_EL1", 0b11, 0b100, 0b0100, 0b0001, 0b000>;
568 def : RWSysReg<"SP_EL2", 0b11, 0b110, 0b0100, 0b0001, 0b000>;
569 def : RWSysReg<"SPSel", 0b11, 0b000, 0b0100, 0b0010, 0b000>;
570 def : RWSysReg<"NZCV", 0b11, 0b011, 0b0100, 0b0010, 0b000>;
571 def : RWSysReg<"DAIF", 0b11, 0b011, 0b0100, 0b0010, 0b001>;
572 def : RWSysReg<"CurrentEL", 0b11, 0b000, 0b0100, 0b0010, 0b010>;
573 def : RWSysReg<"SPSR_irq", 0b11, 0b100, 0b0100, 0b0011, 0b000>;
574 def : RWSysReg<"SPSR_abt", 0b11, 0b100, 0b0100, 0b0011, 0b001>;
575 def : RWSysReg<"SPSR_und", 0b11, 0b100, 0b0100, 0b0011, 0b010>;
576 def : RWSysReg<"SPSR_fiq", 0b11, 0b100, 0b0100, 0b0011, 0b011>;
577 def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>;
578 def : RWSysReg<"FPSR", 0b11, 0b011, 0b0100, 0b0100, 0b001>;
579 def : RWSysReg<"DSPSR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b000>;
580 def : RWSysReg<"DLR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b001>;
581 def : RWSysReg<"IFSR32_EL2", 0b11, 0b100, 0b0101, 0b0000, 0b001>;
582 def : RWSysReg<"AFSR0_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b000>;
583 def : RWSysReg<"AFSR0_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b000>;
584 def : RWSysReg<"AFSR0_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b000>;
585 def : RWSysReg<"AFSR1_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b001>;
586 def : RWSysReg<"AFSR1_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b001>;
587 def : RWSysReg<"AFSR1_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b001>;
588 def : RWSysReg<"ESR_EL1", 0b11, 0b000, 0b0101, 0b0010, 0b000>;
589 def : RWSysReg<"ESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b000>;
590 def : RWSysReg<"ESR_EL3", 0b11, 0b110, 0b0101, 0b0010, 0b000>;
591 def : RWSysReg<"FPEXC32_EL2", 0b11, 0b100, 0b0101, 0b0011, 0b000>;
592 def : RWSysReg<"FAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b000>;
593 def : RWSysReg<"FAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b000>;
594 def : RWSysReg<"FAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b000>;
595 def : RWSysReg<"HPFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b100>;
596 def : RWSysReg<"PAR_EL1", 0b11, 0b000, 0b0111, 0b0100, 0b000>;
597 def : RWSysReg<"PMCR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b000>;
598 def : RWSysReg<"PMCNTENSET_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b001>;
599 def : RWSysReg<"PMCNTENCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b010>;
600 def : RWSysReg<"PMOVSCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b011>;
601 def : RWSysReg<"PMSELR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b101>;
602 def : RWSysReg<"PMCCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b000>;
603 def : RWSysReg<"PMXEVTYPER_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b001>;
604 def : RWSysReg<"PMXEVCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b010>;
605 def : RWSysReg<"PMUSERENR_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b000>;
606 def : RWSysReg<"PMINTENSET_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b001>;
607 def : RWSysReg<"PMINTENCLR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b010>;
608 def : RWSysReg<"PMOVSSET_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b011>;
609 def : RWSysReg<"MAIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b000>;
610 def : RWSysReg<"MAIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b000>;
611 def : RWSysReg<"MAIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b000>;
612 def : RWSysReg<"AMAIR_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b000>;
613 def : RWSysReg<"AMAIR_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b000>;
614 def : RWSysReg<"AMAIR_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b000>;
615 def : RWSysReg<"VBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b000>;
616 def : RWSysReg<"VBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b000>;
617 def : RWSysReg<"VBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b000>;
618 def : RWSysReg<"RMR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b010>;
619 def : RWSysReg<"RMR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b010>;
620 def : RWSysReg<"RMR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b010>;
621 def : RWSysReg<"CONTEXTIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b001>;
622 def : RWSysReg<"TPIDR_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b010>;
623 def : RWSysReg<"TPIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b010>;
624 def : RWSysReg<"TPIDR_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b010>;
625 def : RWSysReg<"TPIDRRO_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b011>;
626 def : RWSysReg<"TPIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b100>;
627 def : RWSysReg<"CNTFRQ_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b000>;
628 def : RWSysReg<"CNTVOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b011>;
629 def : RWSysReg<"CNTKCTL_EL1", 0b11, 0b000, 0b1110, 0b0001, 0b000>;
630 def : RWSysReg<"CNTHCTL_EL2", 0b11, 0b100, 0b1110, 0b0001, 0b000>;
631 def : RWSysReg<"CNTP_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b000>;
632 def : RWSysReg<"CNTHP_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b000>;
633 def : RWSysReg<"CNTPS_TVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b000>;
634 def : RWSysReg<"CNTP_CTL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b001>;
635 def : RWSysReg<"CNTHP_CTL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b001>;
636 def : RWSysReg<"CNTPS_CTL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b001>;
637 def : RWSysReg<"CNTP_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b010>;
638 def : RWSysReg<"CNTHP_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b010>;
639 def : RWSysReg<"CNTPS_CVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b010>;
640 def : RWSysReg<"CNTV_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b000>;
641 def : RWSysReg<"CNTV_CTL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b001>;
642 def : RWSysReg<"CNTV_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b010>;
643 def : RWSysReg<"PMEVCNTR0_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b000>;
644 def : RWSysReg<"PMEVCNTR1_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b001>;
645 def : RWSysReg<"PMEVCNTR2_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b010>;
646 def : RWSysReg<"PMEVCNTR3_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b011>;
647 def : RWSysReg<"PMEVCNTR4_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b100>;
648 def : RWSysReg<"PMEVCNTR5_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b101>;
649 def : RWSysReg<"PMEVCNTR6_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b110>;
650 def : RWSysReg<"PMEVCNTR7_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b111>;
651 def : RWSysReg<"PMEVCNTR8_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b000>;
652 def : RWSysReg<"PMEVCNTR9_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b001>;
653 def : RWSysReg<"PMEVCNTR10_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b010>;
654 def : RWSysReg<"PMEVCNTR11_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b011>;
655 def : RWSysReg<"PMEVCNTR12_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b100>;
656 def : RWSysReg<"PMEVCNTR13_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b101>;
657 def : RWSysReg<"PMEVCNTR14_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b110>;
658 def : RWSysReg<"PMEVCNTR15_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b111>;
659 def : RWSysReg<"PMEVCNTR16_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b000>;
660 def : RWSysReg<"PMEVCNTR17_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b001>;
661 def : RWSysReg<"PMEVCNTR18_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b010>;
662 def : RWSysReg<"PMEVCNTR19_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b011>;
663 def : RWSysReg<"PMEVCNTR20_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b100>;
664 def : RWSysReg<"PMEVCNTR21_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b101>;
665 def : RWSysReg<"PMEVCNTR22_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b110>;
666 def : RWSysReg<"PMEVCNTR23_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b111>;
667 def : RWSysReg<"PMEVCNTR24_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b000>;
668 def : RWSysReg<"PMEVCNTR25_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b001>;
669 def : RWSysReg<"PMEVCNTR26_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b010>;
670 def : RWSysReg<"PMEVCNTR27_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b011>;
671 def : RWSysReg<"PMEVCNTR28_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b100>;
672 def : RWSysReg<"PMEVCNTR29_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b101>;
673 def : RWSysReg<"PMEVCNTR30_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b110>;
674 def : RWSysReg<"PMCCFILTR_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b111>;
675 def : RWSysReg<"PMEVTYPER0_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b000>;
676 def : RWSysReg<"PMEVTYPER1_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b001>;
677 def : RWSysReg<"PMEVTYPER2_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b010>;
678 def : RWSysReg<"PMEVTYPER3_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b011>;
679 def : RWSysReg<"PMEVTYPER4_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b100>;
680 def : RWSysReg<"PMEVTYPER5_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b101>;
681 def : RWSysReg<"PMEVTYPER6_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b110>;
682 def : RWSysReg<"PMEVTYPER7_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b111>;
683 def : RWSysReg<"PMEVTYPER8_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b000>;
684 def : RWSysReg<"PMEVTYPER9_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b001>;
685 def : RWSysReg<"PMEVTYPER10_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b010>;
686 def : RWSysReg<"PMEVTYPER11_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b011>;
687 def : RWSysReg<"PMEVTYPER12_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b100>;
688 def : RWSysReg<"PMEVTYPER13_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b101>;
689 def : RWSysReg<"PMEVTYPER14_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b110>;
690 def : RWSysReg<"PMEVTYPER15_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b111>;
691 def : RWSysReg<"PMEVTYPER16_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b000>;
692 def : RWSysReg<"PMEVTYPER17_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b001>;
693 def : RWSysReg<"PMEVTYPER18_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b010>;
694 def : RWSysReg<"PMEVTYPER19_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b011>;
695 def : RWSysReg<"PMEVTYPER20_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b100>;
696 def : RWSysReg<"PMEVTYPER21_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b101>;
697 def : RWSysReg<"PMEVTYPER22_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b110>;
698 def : RWSysReg<"PMEVTYPER23_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b111>;
699 def : RWSysReg<"PMEVTYPER24_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b000>;
700 def : RWSysReg<"PMEVTYPER25_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b001>;
701 def : RWSysReg<"PMEVTYPER26_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b010>;
702 def : RWSysReg<"PMEVTYPER27_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b011>;
703 def : RWSysReg<"PMEVTYPER28_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b100>;
704 def : RWSysReg<"PMEVTYPER29_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b101>;
705 def : RWSysReg<"PMEVTYPER30_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b110>;
706
707 // Trace registers
708 // Op0 Op1 CRn CRm Op2
709 def : RWSysReg<"TRCPRGCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b000>;
710 def : RWSysReg<"TRCPROCSELR", 0b10, 0b001, 0b0000, 0b0010, 0b000>;
711 def : RWSysReg<"TRCCONFIGR", 0b10, 0b001, 0b0000, 0b0100, 0b000>;
712 def : RWSysReg<"TRCAUXCTLR", 0b10, 0b001, 0b0000, 0b0110, 0b000>;
713 def : RWSysReg<"TRCEVENTCTL0R", 0b10, 0b001, 0b0000, 0b1000, 0b000>;
714 def : RWSysReg<"TRCEVENTCTL1R", 0b10, 0b001, 0b0000, 0b1001, 0b000>;
715 def : RWSysReg<"TRCSTALLCTLR", 0b10, 0b001, 0b0000, 0b1011, 0b000>;
716 def : RWSysReg<"TRCTSCTLR", 0b10, 0b001, 0b0000, 0b1100, 0b000>;
717 def : RWSysReg<"TRCSYNCPR", 0b10, 0b001, 0b0000, 0b1101, 0b000>;
718 def : RWSysReg<"TRCCCCTLR", 0b10, 0b001, 0b0000, 0b1110, 0b000>;
719 def : RWSysReg<"TRCBBCTLR", 0b10, 0b001, 0b0000, 0b1111, 0b000>;
720 def : RWSysReg<"TRCTRACEIDR", 0b10, 0b001, 0b0000, 0b0000, 0b001>;
721 def : RWSysReg<"TRCQCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b001>;
722 def : RWSysReg<"TRCVICTLR", 0b10, 0b001, 0b0000, 0b0000, 0b010>;
723 def : RWSysReg<"TRCVIIECTLR", 0b10, 0b001, 0b0000, 0b0001, 0b010>;
724 def : RWSysReg<"TRCVISSCTLR", 0b10, 0b001, 0b0000, 0b0010, 0b010>;
725 def : RWSysReg<"TRCVIPCSSCTLR", 0b10, 0b001, 0b0000, 0b0011, 0b010>;
726 def : RWSysReg<"TRCVDCTLR", 0b10, 0b001, 0b0000, 0b1000, 0b010>;
727 def : RWSysReg<"TRCVDSACCTLR", 0b10, 0b001, 0b0000, 0b1001, 0b010>;
728 def : RWSysReg<"TRCVDARCCTLR", 0b10, 0b001, 0b0000, 0b1010, 0b010>;
729 def : RWSysReg<"TRCSEQEVR0", 0b10, 0b001, 0b0000, 0b0000, 0b100>;
730 def : RWSysReg<"TRCSEQEVR1", 0b10, 0b001, 0b0000, 0b0001, 0b100>;
731 def : RWSysReg<"TRCSEQEVR2", 0b10, 0b001, 0b0000, 0b0010, 0b100>;
732 def : RWSysReg<"TRCSEQRSTEVR", 0b10, 0b001, 0b0000, 0b0110, 0b100>;
733 def : RWSysReg<"TRCSEQSTR", 0b10, 0b001, 0b0000, 0b0111, 0b100>;
734 def : RWSysReg<"TRCEXTINSELR", 0b10, 0b001, 0b0000, 0b1000, 0b100>;
735 def : RWSysReg<"TRCCNTRLDVR0", 0b10, 0b001, 0b0000, 0b0000, 0b101>;
736 def : RWSysReg<"TRCCNTRLDVR1", 0b10, 0b001, 0b0000, 0b0001, 0b101>;
737 def : RWSysReg<"TRCCNTRLDVR2", 0b10, 0b001, 0b0000, 0b0010, 0b101>;
738 def : RWSysReg<"TRCCNTRLDVR3", 0b10, 0b001, 0b0000, 0b0011, 0b101>;
739 def : RWSysReg<"TRCCNTCTLR0", 0b10, 0b001, 0b0000, 0b0100, 0b101>;
740 def : RWSysReg<"TRCCNTCTLR1", 0b10, 0b001, 0b0000, 0b0101, 0b101>;
741 def : RWSysReg<"TRCCNTCTLR2", 0b10, 0b001, 0b0000, 0b0110, 0b101>;
742 def : RWSysReg<"TRCCNTCTLR3", 0b10, 0b001, 0b0000, 0b0111, 0b101>;
743 def : RWSysReg<"TRCCNTVR0", 0b10, 0b001, 0b0000, 0b1000, 0b101>;
744 def : RWSysReg<"TRCCNTVR1", 0b10, 0b001, 0b0000, 0b1001, 0b101>;
745 def : RWSysReg<"TRCCNTVR2", 0b10, 0b001, 0b0000, 0b1010, 0b101>;
746 def : RWSysReg<"TRCCNTVR3", 0b10, 0b001, 0b0000, 0b1011, 0b101>;
747 def : RWSysReg<"TRCIMSPEC0", 0b10, 0b001, 0b0000, 0b0000, 0b111>;
748 def : RWSysReg<"TRCIMSPEC1", 0b10, 0b001, 0b0000, 0b0001, 0b111>;
749 def : RWSysReg<"TRCIMSPEC2", 0b10, 0b001, 0b0000, 0b0010, 0b111>;
750 def : RWSysReg<"TRCIMSPEC3", 0b10, 0b001, 0b0000, 0b0011, 0b111>;
751 def : RWSysReg<"TRCIMSPEC4", 0b10, 0b001, 0b0000, 0b0100, 0b111>;
752 def : RWSysReg<"TRCIMSPEC5", 0b10, 0b001, 0b0000, 0b0101, 0b111>;
753 def : RWSysReg<"TRCIMSPEC6", 0b10, 0b001, 0b0000, 0b0110, 0b111>;
754 def : RWSysReg<"TRCIMSPEC7", 0b10, 0b001, 0b0000, 0b0111, 0b111>;
755 def : RWSysReg<"TRCRSCTLR2", 0b10, 0b001, 0b0001, 0b0010, 0b000>;
756 def : RWSysReg<"TRCRSCTLR3", 0b10, 0b001, 0b0001, 0b0011, 0b000>;
757 def : RWSysReg<"TRCRSCTLR4", 0b10, 0b001, 0b0001, 0b0100, 0b000>;
758 def : RWSysReg<"TRCRSCTLR5", 0b10, 0b001, 0b0001, 0b0101, 0b000>;
759 def : RWSysReg<"TRCRSCTLR6", 0b10, 0b001, 0b0001, 0b0110, 0b000>;
760 def : RWSysReg<"TRCRSCTLR7", 0b10, 0b001, 0b0001, 0b0111, 0b000>;
761 def : RWSysReg<"TRCRSCTLR8", 0b10, 0b001, 0b0001, 0b1000, 0b000>;
762 def : RWSysReg<"TRCRSCTLR9", 0b10, 0b001, 0b0001, 0b1001, 0b000>;
763 def : RWSysReg<"TRCRSCTLR10", 0b10, 0b001, 0b0001, 0b1010, 0b000>;
764 def : RWSysReg<"TRCRSCTLR11", 0b10, 0b001, 0b0001, 0b1011, 0b000>;
765 def : RWSysReg<"TRCRSCTLR12", 0b10, 0b001, 0b0001, 0b1100, 0b000>;
766 def : RWSysReg<"TRCRSCTLR13", 0b10, 0b001, 0b0001, 0b1101, 0b000>;
767 def : RWSysReg<"TRCRSCTLR14", 0b10, 0b001, 0b0001, 0b1110, 0b000>;
768 def : RWSysReg<"TRCRSCTLR15", 0b10, 0b001, 0b0001, 0b1111, 0b000>;
769 def : RWSysReg<"TRCRSCTLR16", 0b10, 0b001, 0b0001, 0b0000, 0b001>;
770 def : RWSysReg<"TRCRSCTLR17", 0b10, 0b001, 0b0001, 0b0001, 0b001>;
771 def : RWSysReg<"TRCRSCTLR18", 0b10, 0b001, 0b0001, 0b0010, 0b001>;
772 def : RWSysReg<"TRCRSCTLR19", 0b10, 0b001, 0b0001, 0b0011, 0b001>;
773 def : RWSysReg<"TRCRSCTLR20", 0b10, 0b001, 0b0001, 0b0100, 0b001>;
774 def : RWSysReg<"TRCRSCTLR21", 0b10, 0b001, 0b0001, 0b0101, 0b001>;
775 def : RWSysReg<"TRCRSCTLR22", 0b10, 0b001, 0b0001, 0b0110, 0b001>;
776 def : RWSysReg<"TRCRSCTLR23", 0b10, 0b001, 0b0001, 0b0111, 0b001>;
777 def : RWSysReg<"TRCRSCTLR24", 0b10, 0b001, 0b0001, 0b1000, 0b001>;
778 def : RWSysReg<"TRCRSCTLR25", 0b10, 0b001, 0b0001, 0b1001, 0b001>;
779 def : RWSysReg<"TRCRSCTLR26", 0b10, 0b001, 0b0001, 0b1010, 0b001>;
780 def : RWSysReg<"TRCRSCTLR27", 0b10, 0b001, 0b0001, 0b1011, 0b001>;
781 def : RWSysReg<"TRCRSCTLR28", 0b10, 0b001, 0b0001, 0b1100, 0b001>;
782 def : RWSysReg<"TRCRSCTLR29", 0b10, 0b001, 0b0001, 0b1101, 0b001>;
783 def : RWSysReg<"TRCRSCTLR30", 0b10, 0b001, 0b0001, 0b1110, 0b001>;
784 def : RWSysReg<"TRCRSCTLR31", 0b10, 0b001, 0b0001, 0b1111, 0b001>;
785 def : RWSysReg<"TRCSSCCR0", 0b10, 0b001, 0b0001, 0b0000, 0b010>;
786 def : RWSysReg<"TRCSSCCR1", 0b10, 0b001, 0b0001, 0b0001, 0b010>;
787 def : RWSysReg<"TRCSSCCR2", 0b10, 0b001, 0b0001, 0b0010, 0b010>;
788 def : RWSysReg<"TRCSSCCR3", 0b10, 0b001, 0b0001, 0b0011, 0b010>;
789 def : RWSysReg<"TRCSSCCR4", 0b10, 0b001, 0b0001, 0b0100, 0b010>;
790 def : RWSysReg<"TRCSSCCR5", 0b10, 0b001, 0b0001, 0b0101, 0b010>;
791 def : RWSysReg<"TRCSSCCR6", 0b10, 0b001, 0b0001, 0b0110, 0b010>;
792 def : RWSysReg<"TRCSSCCR7", 0b10, 0b001, 0b0001, 0b0111, 0b010>;
793 def : RWSysReg<"TRCSSCSR0", 0b10, 0b001, 0b0001, 0b1000, 0b010>;
794 def : RWSysReg<"TRCSSCSR1", 0b10, 0b001, 0b0001, 0b1001, 0b010>;
795 def : RWSysReg<"TRCSSCSR2", 0b10, 0b001, 0b0001, 0b1010, 0b010>;
796 def : RWSysReg<"TRCSSCSR3", 0b10, 0b001, 0b0001, 0b1011, 0b010>;
797 def : RWSysReg<"TRCSSCSR4", 0b10, 0b001, 0b0001, 0b1100, 0b010>;
798 def : RWSysReg<"TRCSSCSR5", 0b10, 0b001, 0b0001, 0b1101, 0b010>;
799 def : RWSysReg<"TRCSSCSR6", 0b10, 0b001, 0b0001, 0b1110, 0b010>;
800 def : RWSysReg<"TRCSSCSR7", 0b10, 0b001, 0b0001, 0b1111, 0b010>;
801 def : RWSysReg<"TRCSSPCICR0", 0b10, 0b001, 0b0001, 0b0000, 0b011>;
802 def : RWSysReg<"TRCSSPCICR1", 0b10, 0b001, 0b0001, 0b0001, 0b011>;
803 def : RWSysReg<"TRCSSPCICR2", 0b10, 0b001, 0b0001, 0b0010, 0b011>;
804 def : RWSysReg<"TRCSSPCICR3", 0b10, 0b001, 0b0001, 0b0011, 0b011>;
805 def : RWSysReg<"TRCSSPCICR4", 0b10, 0b001, 0b0001, 0b0100, 0b011>;
806 def : RWSysReg<"TRCSSPCICR5", 0b10, 0b001, 0b0001, 0b0101, 0b011>;
807 def : RWSysReg<"TRCSSPCICR6", 0b10, 0b001, 0b0001, 0b0110, 0b011>;
808 def : RWSysReg<"TRCSSPCICR7", 0b10, 0b001, 0b0001, 0b0111, 0b011>;
809 def : RWSysReg<"TRCPDCR", 0b10, 0b001, 0b0001, 0b0100, 0b100>;
810 def : RWSysReg<"TRCACVR0", 0b10, 0b001, 0b0010, 0b0000, 0b000>;
811 def : RWSysReg<"TRCACVR1", 0b10, 0b001, 0b0010, 0b0010, 0b000>;
812 def : RWSysReg<"TRCACVR2", 0b10, 0b001, 0b0010, 0b0100, 0b000>;
813 def : RWSysReg<"TRCACVR3", 0b10, 0b001, 0b0010, 0b0110, 0b000>;
814 def : RWSysReg<"TRCACVR4", 0b10, 0b001, 0b0010, 0b1000, 0b000>;
815 def : RWSysReg<"TRCACVR5", 0b10, 0b001, 0b0010, 0b1010, 0b000>;
816 def : RWSysReg<"TRCACVR6", 0b10, 0b001, 0b0010, 0b1100, 0b000>;
817 def : RWSysReg<"TRCACVR7", 0b10, 0b001, 0b0010, 0b1110, 0b000>;
818 def : RWSysReg<"TRCACVR8", 0b10, 0b001, 0b0010, 0b0000, 0b001>;
819 def : RWSysReg<"TRCACVR9", 0b10, 0b001, 0b0010, 0b0010, 0b001>;
820 def : RWSysReg<"TRCACVR10", 0b10, 0b001, 0b0010, 0b0100, 0b001>;
821 def : RWSysReg<"TRCACVR11", 0b10, 0b001, 0b0010, 0b0110, 0b001>;
822 def : RWSysReg<"TRCACVR12", 0b10, 0b001, 0b0010, 0b1000, 0b001>;
823 def : RWSysReg<"TRCACVR13", 0b10, 0b001, 0b0010, 0b1010, 0b001>;
824 def : RWSysReg<"TRCACVR14", 0b10, 0b001, 0b0010, 0b1100, 0b001>;
825 def : RWSysReg<"TRCACVR15", 0b10, 0b001, 0b0010, 0b1110, 0b001>;
826 def : RWSysReg<"TRCACATR0", 0b10, 0b001, 0b0010, 0b0000, 0b010>;
827 def : RWSysReg<"TRCACATR1", 0b10, 0b001, 0b0010, 0b0010, 0b010>;
828 def : RWSysReg<"TRCACATR2", 0b10, 0b001, 0b0010, 0b0100, 0b010>;
829 def : RWSysReg<"TRCACATR3", 0b10, 0b001, 0b0010, 0b0110, 0b010>;
830 def : RWSysReg<"TRCACATR4", 0b10, 0b001, 0b0010, 0b1000, 0b010>;
831 def : RWSysReg<"TRCACATR5", 0b10, 0b001, 0b0010, 0b1010, 0b010>;
832 def : RWSysReg<"TRCACATR6", 0b10, 0b001, 0b0010, 0b1100, 0b010>;
833 def : RWSysReg<"TRCACATR7", 0b10, 0b001, 0b0010, 0b1110, 0b010>;
834 def : RWSysReg<"TRCACATR8", 0b10, 0b001, 0b0010, 0b0000, 0b011>;
835 def : RWSysReg<"TRCACATR9", 0b10, 0b001, 0b0010, 0b0010, 0b011>;
836 def : RWSysReg<"TRCACATR10", 0b10, 0b001, 0b0010, 0b0100, 0b011>;
837 def : RWSysReg<"TRCACATR11", 0b10, 0b001, 0b0010, 0b0110, 0b011>;
838 def : RWSysReg<"TRCACATR12", 0b10, 0b001, 0b0010, 0b1000, 0b011>;
839 def : RWSysReg<"TRCACATR13", 0b10, 0b001, 0b0010, 0b1010, 0b011>;
840 def : RWSysReg<"TRCACATR14", 0b10, 0b001, 0b0010, 0b1100, 0b011>;
841 def : RWSysReg<"TRCACATR15", 0b10, 0b001, 0b0010, 0b1110, 0b011>;
842 def : RWSysReg<"TRCDVCVR0", 0b10, 0b001, 0b0010, 0b0000, 0b100>;
843 def : RWSysReg<"TRCDVCVR1", 0b10, 0b001, 0b0010, 0b0100, 0b100>;
844 def : RWSysReg<"TRCDVCVR2", 0b10, 0b001, 0b0010, 0b1000, 0b100>;
845 def : RWSysReg<"TRCDVCVR3", 0b10, 0b001, 0b0010, 0b1100, 0b100>;
846 def : RWSysReg<"TRCDVCVR4", 0b10, 0b001, 0b0010, 0b0000, 0b101>;
847 def : RWSysReg<"TRCDVCVR5", 0b10, 0b001, 0b0010, 0b0100, 0b101>;
848 def : RWSysReg<"TRCDVCVR6", 0b10, 0b001, 0b0010, 0b1000, 0b101>;
849 def : RWSysReg<"TRCDVCVR7", 0b10, 0b001, 0b0010, 0b1100, 0b101>;
850 def : RWSysReg<"TRCDVCMR0", 0b10, 0b001, 0b0010, 0b0000, 0b110>;
851 def : RWSysReg<"TRCDVCMR1", 0b10, 0b001, 0b0010, 0b0100, 0b110>;
852 def : RWSysReg<"TRCDVCMR2", 0b10, 0b001, 0b0010, 0b1000, 0b110>;
853 def : RWSysReg<"TRCDVCMR3", 0b10, 0b001, 0b0010, 0b1100, 0b110>;
854 def : RWSysReg<"TRCDVCMR4", 0b10, 0b001, 0b0010, 0b0000, 0b111>;
855 def : RWSysReg<"TRCDVCMR5", 0b10, 0b001, 0b0010, 0b0100, 0b111>;
856 def : RWSysReg<"TRCDVCMR6", 0b10, 0b001, 0b0010, 0b1000, 0b111>;
857 def : RWSysReg<"TRCDVCMR7", 0b10, 0b001, 0b0010, 0b1100, 0b111>;
858 def : RWSysReg<"TRCCIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b000>;
859 def : RWSysReg<"TRCCIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b000>;
860 def : RWSysReg<"TRCCIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b000>;
861 def : RWSysReg<"TRCCIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b000>;
862 def : RWSysReg<"TRCCIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b000>;
863 def : RWSysReg<"TRCCIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b000>;
864 def : RWSysReg<"TRCCIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b000>;
865 def : RWSysReg<"TRCCIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b000>;
866 def : RWSysReg<"TRCVMIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b001>;
867 def : RWSysReg<"TRCVMIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b001>;
868 def : RWSysReg<"TRCVMIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b001>;
869 def : RWSysReg<"TRCVMIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b001>;
870 def : RWSysReg<"TRCVMIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b001>;
871 def : RWSysReg<"TRCVMIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b001>;
872 def : RWSysReg<"TRCVMIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b001>;
873 def : RWSysReg<"TRCVMIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b001>;
874 def : RWSysReg<"TRCCIDCCTLR0", 0b10, 0b001, 0b0011, 0b0000, 0b010>;
875 def : RWSysReg<"TRCCIDCCTLR1", 0b10, 0b001, 0b0011, 0b0001, 0b010>;
876 def : RWSysReg<"TRCVMIDCCTLR0", 0b10, 0b001, 0b0011, 0b0010, 0b010>;
877 def : RWSysReg<"TRCVMIDCCTLR1", 0b10, 0b001, 0b0011, 0b0011, 0b010>;
878 def : RWSysReg<"TRCITCTRL", 0b10, 0b001, 0b0111, 0b0000, 0b100>;
879 def : RWSysReg<"TRCCLAIMSET", 0b10, 0b001, 0b0111, 0b1000, 0b110>;
880 def : RWSysReg<"TRCCLAIMCLR", 0b10, 0b001, 0b0111, 0b1001, 0b110>;
881
882 // GICv3 registers
883 // Op0 Op1 CRn CRm Op2
884 def : RWSysReg<"ICC_BPR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b011>;
885 def : RWSysReg<"ICC_BPR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b011>;
886 def : RWSysReg<"ICC_PMR_EL1", 0b11, 0b000, 0b0100, 0b0110, 0b000>;
887 def : RWSysReg<"ICC_CTLR_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b100>;
888 def : RWSysReg<"ICC_CTLR_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b100>;
889 def : RWSysReg<"ICC_SRE_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b101>;
890 def : RWSysReg<"ICC_SRE_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b101>;
891 def : RWSysReg<"ICC_SRE_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b101>;
892 def : RWSysReg<"ICC_IGRPEN0_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b110>;
893 def : RWSysReg<"ICC_IGRPEN1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b111>;
894 def : RWSysReg<"ICC_IGRPEN1_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b111>;
895 def : RWSysReg<"ICC_SEIEN_EL1", 0b11, 0b000, 0b1100, 0b1101, 0b000>;
896 def : RWSysReg<"ICC_AP0R0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b100>;
897 def : RWSysReg<"ICC_AP0R1_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b101>;
898 def : RWSysReg<"ICC_AP0R2_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b110>;
899 def : RWSysReg<"ICC_AP0R3_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b111>;
900 def : RWSysReg<"ICC_AP1R0_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b000>;
901 def : RWSysReg<"ICC_AP1R1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b001>;
902 def : RWSysReg<"ICC_AP1R2_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b010>;
903 def : RWSysReg<"ICC_AP1R3_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b011>;
904 def : RWSysReg<"ICH_AP0R0_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b000>;
905 def : RWSysReg<"ICH_AP0R1_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b001>;
906 def : RWSysReg<"ICH_AP0R2_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b010>;
907 def : RWSysReg<"ICH_AP0R3_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b011>;
908 def : RWSysReg<"ICH_AP1R0_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b000>;
909 def : RWSysReg<"ICH_AP1R1_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b001>;
910 def : RWSysReg<"ICH_AP1R2_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b010>;
911 def : RWSysReg<"ICH_AP1R3_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b011>;
912 def : RWSysReg<"ICH_HCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b000>;
913 def : RWSysReg<"ICH_MISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b010>;
914 def : RWSysReg<"ICH_VMCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b111>;
915 def : RWSysReg<"ICH_VSEIR_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b100>;
916 def : RWSysReg<"ICH_LR0_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b000>;
917 def : RWSysReg<"ICH_LR1_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b001>;
918 def : RWSysReg<"ICH_LR2_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b010>;
919 def : RWSysReg<"ICH_LR3_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b011>;
920 def : RWSysReg<"ICH_LR4_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b100>;
921 def : RWSysReg<"ICH_LR5_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b101>;
922 def : RWSysReg<"ICH_LR6_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b110>;
923 def : RWSysReg<"ICH_LR7_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b111>;
924 def : RWSysReg<"ICH_LR8_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b000>;
925 def : RWSysReg<"ICH_LR9_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b001>;
926 def : RWSysReg<"ICH_LR10_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b010>;
927 def : RWSysReg<"ICH_LR11_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b011>;
928 def : RWSysReg<"ICH_LR12_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b100>;
929 def : RWSysReg<"ICH_LR13_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b101>;
930 def : RWSysReg<"ICH_LR14_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b110>;
931 def : RWSysReg<"ICH_LR15_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b111>;
932
933 // v8.1a "Privileged Access Never" extension-specific system registers
934 let Requires = [{ {AArch64::HasV8_1aOps} }] in
935 def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>;
936
937 // v8.1a "Limited Ordering Regions" extension-specific system registers
938 // Op0 Op1 CRn CRm Op2
939 let Requires = [{ {AArch64::HasV8_1aOps} }] in {
940 def : RWSysReg<"LORSA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b000>;
941 def : RWSysReg<"LOREA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b001>;
942 def : RWSysReg<"LORN_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b010>;
943 def : RWSysReg<"LORC_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b011>;
944 }
945
946 // v8.1a "Virtualization hos extensions" system registers
947 // Op0 Op1 CRn CRm Op2
948 let Requires = [{ {AArch64::HasV8_1aOps} }] in {
949 def : RWSysReg<"TTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b001>;
950 def : RWSysReg<"CONTEXTIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b001>;
951 def : RWSysReg<"CNTHV_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b000>;
952 def : RWSysReg<"CNTHV_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b010>;
953 def : RWSysReg<"CNTHV_CTL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b001>;
954 def : RWSysReg<"SCTLR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b000>;
955 def : RWSysReg<"CPACR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b010>;
956 def : RWSysReg<"TTBR0_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b000>;
957 def : RWSysReg<"TTBR1_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b001>;
958 def : RWSysReg<"TCR_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b010>;
959 def : RWSysReg<"AFSR0_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b000>;
960 def : RWSysReg<"AFSR1_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b001>;
961 def : RWSysReg<"ESR_EL12", 0b11, 0b101, 0b0101, 0b0010, 0b000>;
962 def : RWSysReg<"FAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b000>;
963 def : RWSysReg<"MAIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b000>;
964 def : RWSysReg<"AMAIR_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b000>;
965 def : RWSysReg<"VBAR_EL12", 0b11, 0b101, 0b1100, 0b0000, 0b000>;
966 def : RWSysReg<"CONTEXTIDR_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b001>;
967 def : RWSysReg<"CNTKCTL_EL12", 0b11, 0b101, 0b1110, 0b0001, 0b000>;
968 def : RWSysReg<"CNTP_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b000>;
969 def : RWSysReg<"CNTP_CTL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b001>;
970 def : RWSysReg<"CNTP_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b010>;
971 def : RWSysReg<"CNTV_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b000>;
972 def : RWSysReg<"CNTV_CTL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b001>;
973 def : RWSysReg<"CNTV_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b010>;
974 def : RWSysReg<"SPSR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b000>;
975 def : RWSysReg<"ELR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b001>;
976 }
977 // v8.2a registers
978 // Op0 Op1 CRn CRm Op2
979 let Requires = [{ {AArch64::HasV8_2aOps} }] in
980 def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>;
981
982 // v8.2a "Statistical Profiling extension" registers
983 // Op0 Op1 CRn CRm Op2
984 let Requires = [{ {AArch64::FeatureSPE} }] in {
985 def : RWSysReg<"PMBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b000>;
986 def : RWSysReg<"PMBPTR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b001>;
987 def : RWSysReg<"PMBSR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b011>;
988 def : RWSysReg<"PMBIDR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b111>;
989 def : RWSysReg<"PMSCR_EL2", 0b11, 0b100, 0b1001, 0b1001, 0b000>;
990 def : RWSysReg<"PMSCR_EL12", 0b11, 0b101, 0b1001, 0b1001, 0b000>;
991 def : RWSysReg<"PMSCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b000>;
992 def : RWSysReg<"PMSICR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b010>;
993 def : RWSysReg<"PMSIRR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b011>;
994 def : RWSysReg<"PMSFCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b100>;
995 def : RWSysReg<"PMSEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b101>;
996 def : RWSysReg<"PMSLATFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b110>;
997 def : RWSysReg<"PMSIDR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b111>;
998 }
999
1000 // v8.2a "RAS extension" registers
1001 // Op0 Op1 CRn CRm Op2
1002 let Requires = [{ {AArch64::FeatureRAS} }] in {
1003 def : RWSysReg<"ERRSELR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b001>;
1004 def : RWSysReg<"ERXCTLR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b001>;
1005 def : RWSysReg<"ERXSTATUS_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b010>;
1006 def : RWSysReg<"ERXADDR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b011>;
1007 def : RWSysReg<"ERXMISC0_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b000>;
1008 def : RWSysReg<"ERXMISC1_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b001>;
1009 def : RWSysReg<"DISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b001>;
1010 def : RWSysReg<"VDISR_EL2", 0b11, 0b100, 0b1100, 0b0001, 0b001>;
1011 def : RWSysReg<"VSESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b011>;
1012 }
1013
1014 // Cyclone specific system registers
1015 // Op0 Op1 CRn CRm Op2
1016 let Requires = [{ {AArch64::ProcCyclone} }] in
1017 def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>;
20722072 return MatchOperand_ParseFail;
20732073 }
20742074
2075 bool Valid;
2076 auto Mapper = AArch64PRFM::PRFMMapper();
2077 StringRef Name =
2078 Mapper.toString(MCE->getValue(), getSTI().getFeatureBits(), Valid);
2079 Operands.push_back(AArch64Operand::CreatePrefetch(prfop, Name,
2080 S, getContext()));
2075 auto PRFM = AArch64PRFM::lookupPRFMByEncoding(MCE->getValue());
2076 Operands.push_back(AArch64Operand::CreatePrefetch(
2077 prfop, PRFM ? PRFM->Name : "", S, getContext()));
20812078 return MatchOperand_Success;
20822079 }
20832080
20862083 return MatchOperand_ParseFail;
20872084 }
20882085
2089 bool Valid;
2090 auto Mapper = AArch64PRFM::PRFMMapper();
2091 unsigned prfop =
2092 Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid);
2093 if (!Valid) {
2086 auto PRFM = AArch64PRFM::lookupPRFMByName(Tok.getString());
2087 if (!PRFM) {
20942088 TokError("pre-fetch hint expected");
20952089 return MatchOperand_ParseFail;
20962090 }
20972091
20982092 Parser.Lex(); // Eat identifier token.
2099 Operands.push_back(AArch64Operand::CreatePrefetch(prfop, Tok.getString(),
2100 S, getContext()));
2093 Operands.push_back(AArch64Operand::CreatePrefetch(
2094 PRFM->Encoding, Tok.getString(), S, getContext()));
21012095 return MatchOperand_Success;
21022096 }
21032097
21122106 return MatchOperand_ParseFail;
21132107 }
21142108
2115 bool Valid;
2116 auto Mapper = AArch64PSBHint::PSBHintMapper();
2117 unsigned psbhint =
2118 Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid);
2119 if (!Valid) {
2109 auto PSB = AArch64PSBHint::lookupPSBByName(Tok.getString());
2110 if (!PSB) {
21202111 TokError("invalid operand for instruction");
21212112 return MatchOperand_ParseFail;
21222113 }
21232114
21242115 Parser.Lex(); // Eat identifier token.
2125 Operands.push_back(AArch64Operand::CreatePSBHint(psbhint, Tok.getString(),
2126 S, getContext()));
2116 Operands.push_back(AArch64Operand::CreatePSBHint(
2117 PSB->Encoding, Tok.getString(), S, getContext()));
21272118 return MatchOperand_Success;
21282119 }
21292120
27472738 Error(ExprLoc, "barrier operand out of range");
27482739 return MatchOperand_ParseFail;
27492740 }
2750 bool Valid;
2751 auto Mapper = AArch64DB::DBarrierMapper();
2752 StringRef Name =
2753 Mapper.toString(MCE->getValue(), getSTI().getFeatureBits(), Valid);
2754 Operands.push_back( AArch64Operand::CreateBarrier(MCE->getValue(), Name,
2755 ExprLoc, getContext()));
2741 auto DB = AArch64DB::lookupDBByEncoding(MCE->getValue());
2742 Operands.push_back(AArch64Operand::CreateBarrier(
2743 MCE->getValue(), DB ? DB->Name : "", ExprLoc, getContext()));
27562744 return MatchOperand_Success;
27572745 }
27582746
27612749 return MatchOperand_ParseFail;
27622750 }
27632751
2764 bool Valid;
2765 auto Mapper = AArch64DB::DBarrierMapper();
2766 unsigned Opt =
2767 Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid);
2768 if (!Valid) {
2752 auto DB = AArch64DB::lookupDBByName(Tok.getString());
2753 if (!DB) {
27692754 TokError("invalid barrier option name");
27702755 return MatchOperand_ParseFail;
27712756 }
27722757
27732758 // The only valid named option for ISB is 'sy'
2774 if (Mnemonic == "isb" && Opt != AArch64DB::SY) {
2759 if (Mnemonic == "isb" && DB->Encoding != AArch64DB::sy) {
27752760 TokError("'sy' or #imm operand expected");
27762761 return MatchOperand_ParseFail;
27772762 }
27782763
2779 Operands.push_back( AArch64Operand::CreateBarrier(Opt, Tok.getString(),
2780 getLoc(), getContext()));
2764 Operands.push_back(AArch64Operand::CreateBarrier(
2765 DB->Encoding, Tok.getString(), getLoc(), getContext()));
27812766 Parser.Lex(); // Consume the option
27822767
27832768 return MatchOperand_Success;
27912776 if (Tok.isNot(AsmToken::Identifier))
27922777 return MatchOperand_NoMatch;
27932778
2794 bool IsKnown;
2795 auto MRSMapper = AArch64SysReg::MRSMapper();
2796 uint32_t MRSReg = MRSMapper.fromString(Tok.getString(),
2797 getSTI().getFeatureBits(), IsKnown);
2798 assert(IsKnown == (MRSReg != -1U) &&
2799 "register should be -1 if and only if it's unknown");
2800
2801 auto MSRMapper = AArch64SysReg::MSRMapper();
2802 uint32_t MSRReg = MSRMapper.fromString(Tok.getString(),
2803 getSTI().getFeatureBits(), IsKnown);
2804 assert(IsKnown == (MSRReg != -1U) &&
2805 "register should be -1 if and only if it's unknown");
2806
2807 auto PStateMapper = AArch64PState::PStateMapper();
2808 uint32_t PStateField =
2809 PStateMapper.fromString(Tok.getString(),
2810 getSTI().getFeatureBits(), IsKnown);
2811 assert(IsKnown == (PStateField != -1U) &&
2812 "register should be -1 if and only if it's unknown");
2813
2814 Operands.push_back(AArch64Operand::CreateSysReg(
2815 Tok.getString(), getLoc(), MRSReg, MSRReg, PStateField, getContext()));
2779 int MRSReg, MSRReg;
2780 auto SysReg = AArch64SysReg::lookupSysRegByName(Tok.getString());
2781 if (SysReg && SysReg->haveFeatures(getSTI().getFeatureBits())) {
2782 MRSReg = SysReg->Readable ? SysReg->Encoding : -1;
2783 MSRReg = SysReg->Writeable ? SysReg->Encoding : -1;
2784 } else
2785 MRSReg = MSRReg = AArch64SysReg::parseGenericRegister(Tok.getString());
2786
2787 auto PState = AArch64PState::lookupPStateByName(Tok.getString());
2788 unsigned PStateImm = -1;
2789 if (PState && PState->haveFeatures(getSTI().getFeatureBits()))
2790 PStateImm = PState->Encoding;
2791
2792 Operands.push_back(
2793 AArch64Operand::CreateSysReg(Tok.getString(), getLoc(), MRSReg, MSRReg,
2794 PStateImm, getContext()));
28162795 Parser.Lex(); // Eat identifier
28172796
28182797 return MatchOperand_Success;
1111 tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
1212 tablegen(LLVM AArch64GenSubtargetInfo.inc -gen-subtarget)
1313 tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
14 tablegen(LLVM AArch64GenSystemOperands.inc -gen-searchable-tables)
15
1416 add_public_tablegen_target(AArch64CommonTableGen)
1517
1618 # List of all GlobalISel files.
15221522 Inst.addOperand(MCOperand::createImm(pstate_field));
15231523 Inst.addOperand(MCOperand::createImm(crm));
15241524
1525 bool ValidNamed;
1526 const AArch64Disassembler *Dis =
1525 const AArch64Disassembler *Dis =
15271526 static_cast(Decoder);
1528 (void)AArch64PState::PStateMapper().toString(pstate_field,
1529 Dis->getSubtargetInfo().getFeatureBits(), ValidNamed);
1530
1531 return ValidNamed ? Success : Fail;
1527 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1528 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1529 return Success;
1530 return Fail;
15321531 }
15331532
15341533 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
11901190 const MCSubtargetInfo &STI,
11911191 raw_ostream &O) {
11921192 unsigned prfop = MI->getOperand(OpNum).getImm();
1193 bool Valid;
1194 StringRef Name =
1195 AArch64PRFM::PRFMMapper().toString(prfop, STI.getFeatureBits(), Valid);
1196 if (Valid)
1197 O << Name;
1193 auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop);
1194 if (PRFM)
1195 O << PRFM->Name;
11981196 else
11991197 O << '#' << formatImm(prfop);
12001198 }
12031201 const MCSubtargetInfo &STI,
12041202 raw_ostream &O) {
12051203 unsigned psbhintop = MI->getOperand(OpNum).getImm();
1206 bool Valid;
1207 StringRef Name =
1208 AArch64PSBHint::PSBHintMapper().toString(psbhintop, STI.getFeatureBits(), Valid);
1209 if (Valid)
1210 O << Name;
1204 auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
1205 if (PSB)
1206 O << PSB->Name;
12111207 else
12121208 O << '#' << formatImm(psbhintop);
12131209 }
14031399 unsigned Val = MI->getOperand(OpNo).getImm();
14041400 unsigned Opcode = MI->getOpcode();
14051401
1406 bool Valid;
14071402 StringRef Name;
1408 if (Opcode == AArch64::ISB)
1409 Name = AArch64ISB::ISBMapper().toString(Val, STI.getFeatureBits(),
1410 Valid);
1411 else
1412 Name = AArch64DB::DBarrierMapper().toString(Val, STI.getFeatureBits(),
1413 Valid);
1414 if (Valid)
1403 if (Opcode == AArch64::ISB) {
1404 auto ISB = AArch64ISB::lookupISBByEncoding(Val);
1405 Name = ISB ? ISB->Name : "";
1406 } else {
1407 auto DB = AArch64DB::lookupDBByEncoding(Val);
1408 Name = DB ? DB->Name : "";
1409 }
1410 if (!Name.empty())
14151411 O << Name;
14161412 else
14171413 O << "#" << Val;
14221418 raw_ostream &O) {
14231419 unsigned Val = MI->getOperand(OpNo).getImm();
14241420
1425 auto Mapper = AArch64SysReg::MRSMapper();
1426 std::string Name = Mapper.toString(Val, STI.getFeatureBits());
1427
1428 O << StringRef(Name).upper();
1421 // Horrible hack for the one register that has identical encodings but
1422 // different names in MSR and MRS. Because of this, one of MRS and MSR is
1423 // going to get the wrong entry
1424 if (Val == AArch64SysReg::DBGDTRRX_EL0) {
1425 O << "DBGDTRRX_EL0";
1426 return;
1427 }
1428
1429 const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
1430 if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits()))
1431 O << Reg->Name;
1432 else
1433 O << AArch64SysReg::genericRegisterString(Val);
14291434 }
14301435
14311436 void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
14331438 raw_ostream &O) {
14341439 unsigned Val = MI->getOperand(OpNo).getImm();
14351440
1436 auto Mapper = AArch64SysReg::MSRMapper();
1437 std::string Name = Mapper.toString(Val, STI.getFeatureBits());
1438
1439 O << StringRef(Name).upper();
1441 // Horrible hack for the one register that has identical encodings but
1442 // different names in MSR and MRS. Because of this, one of MRS and MSR is
1443 // going to get the wrong entry
1444 if (Val == AArch64SysReg::DBGDTRTX_EL0) {
1445 O << "DBGDTRTX_EL0";
1446 return;
1447 }
1448
1449 const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
1450 if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits()))
1451 O << Reg->Name;
1452 else
1453 O << AArch64SysReg::genericRegisterString(Val);
14401454 }
14411455
14421456 void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
14441458 raw_ostream &O) {
14451459 unsigned Val = MI->getOperand(OpNo).getImm();
14461460
1447 bool Valid;
1448 StringRef Name =
1449 AArch64PState::PStateMapper().toString(Val, STI.getFeatureBits(), Valid);
1450 if (Valid)
1451 O << Name.upper();
1461 auto PState = AArch64PState::lookupPStateByEncoding(Val);
1462 if (PState && PState->haveFeatures(STI.getFeatureBits()))
1463 O << PState->Name;
14521464 else
14531465 O << "#" << formatImm(Val);
14541466 }
1010 //
1111 //===----------------------------------------------------------------------===//
1212 #include "AArch64BaseInfo.h"
13 #include "llvm/ADT/ArrayRef.h"
1314 #include "llvm/ADT/SmallVector.h"
1415 #include "llvm/ADT/StringExtras.h"
1516 #include "llvm/Support/Regex.h"
1617
1718 using namespace llvm;
1819
19 StringRef AArch64NamedImmMapper::toString(uint32_t Value,
20 const FeatureBitset& FeatureBits, bool &Valid) const {
21 for (unsigned i = 0; i < NumMappings; ++i) {
22 if (Mappings[i].isValueEqual(Value, FeatureBits)) {
23 Valid = true;
24 return Mappings[i].Name;
25 }
20 namespace llvm {
21 namespace AArch64AT {
22 #define GET_AT_IMPL
23 #include "AArch64GenSystemOperands.inc"
2624 }
27
28 Valid = false;
29 return StringRef();
30 }
31
32 uint32_t AArch64NamedImmMapper::fromString(StringRef Name,
33 const FeatureBitset& FeatureBits, bool &Valid) const {
34 std::string LowerCaseName = Name.lower();
35 for (unsigned i = 0; i < NumMappings; ++i) {
36 if (Mappings[i].isNameEqual(LowerCaseName, FeatureBits)) {
37 Valid = true;
38 return Mappings[i].Value;
39 }
40 }
41
42 Valid = false;
43 return -1;
44 }
45
46 bool AArch64NamedImmMapper::validImm(uint32_t Value) const {
47 return Value < TooBigImm;
48 }
49
50 const AArch64NamedImmMapper::Mapping AArch64AT::ATMapper::ATMappings[] = {
51 {"s1e1r", S1E1R, {}},
52 {"s1e2r", S1E2R, {}},
53 {"s1e3r", S1E3R, {}},
54 {"s1e1w", S1E1W, {}},
55 {"s1e2w", S1E2W, {}},
56 {"s1e3w", S1E3W, {}},
57 {"s1e0r", S1E0R, {}},
58 {"s1e0w", S1E0W, {}},
59 {"s12e1r", S12E1R, {}},
60 {"s12e1w", S12E1W, {}},
61 {"s12e0r", S12E0R, {}},
62 {"s12e0w", S12E0W, {}},
63 };
64
65 AArch64AT::ATMapper::ATMapper()
66 : AArch64NamedImmMapper(ATMappings, 0) {}
67
68 const AArch64NamedImmMapper::Mapping AArch64DB::DBarrierMapper::DBarrierMappings[] = {
69 {"oshld", OSHLD, {}},
70 {"oshst", OSHST, {}},
71 {"osh", OSH, {}},
72 {"nshld", NSHLD, {}},
73 {"nshst", NSHST, {}},
74 {"nsh", NSH, {}},
75 {"ishld", ISHLD, {}},
76 {"ishst", ISHST, {}},
77 {"ish", ISH, {}},
78 {"ld", LD, {}},
79 {"st", ST, {}},
80 {"sy", SY, {}}
81 };
82
83 AArch64DB::DBarrierMapper::DBarrierMapper()
84 : AArch64NamedImmMapper(DBarrierMappings, 16u) {}
85
86 const AArch64NamedImmMapper::Mapping AArch64DC::DCMapper::DCMappings[] = {
87 {"zva", ZVA, {}},
88 {"ivac", IVAC, {}},
89 {"isw", ISW, {}},
90 {"cvac", CVAC, {}},
91 {"csw", CSW, {}},
92 {"cvau", CVAU, {}},
93 {"civac", CIVAC, {}},
94 {"cisw", CISW, {}}
95 };
96
97 AArch64DC::DCMapper::DCMapper()
98 : AArch64NamedImmMapper(DCMappings, 0) {}
99
100 const AArch64NamedImmMapper::Mapping AArch64IC::ICMapper::ICMappings[] = {
101 {"ialluis", IALLUIS, {}},
102 {"iallu", IALLU, {}},
103 {"ivau", IVAU, {}}
104 };
105
106 AArch64IC::ICMapper::ICMapper()
107 : AArch64NamedImmMapper(ICMappings, 0) {}
108
109 const AArch64NamedImmMapper::Mapping AArch64ISB::ISBMapper::ISBMappings[] = {
110 {"sy", SY, {}},
111 };
112
113 AArch64ISB::ISBMapper::ISBMapper()
114 : AArch64NamedImmMapper(ISBMappings, 16) {}
115
116 const AArch64NamedImmMapper::Mapping AArch64PRFM::PRFMMapper::PRFMMappings[] = {
117 {"pldl1keep", PLDL1KEEP, {}},
118 {"pldl1strm", PLDL1STRM, {}},
119 {"pldl2keep", PLDL2KEEP, {}},
120 {"pldl2strm", PLDL2STRM, {}},
121 {"pldl3keep", PLDL3KEEP, {}},
122 {"pldl3strm", PLDL3STRM, {}},
123 {"plil1keep", PLIL1KEEP, {}},
124 {"plil1strm", PLIL1STRM, {}},
125 {"plil2keep", PLIL2KEEP, {}},
126 {"plil2strm", PLIL2STRM, {}},
127 {"plil3keep", PLIL3KEEP, {}},
128 {"plil3strm", PLIL3STRM, {}},
129 {"pstl1keep", PSTL1KEEP, {}},
130 {"pstl1strm", PSTL1STRM, {}},
131 {"pstl2keep", PSTL2KEEP, {}},
132 {"pstl2strm", PSTL2STRM, {}},
133 {"pstl3keep", PSTL3KEEP, {}},
134 {"pstl3strm", PSTL3STRM, {}}
135 };
136
137 AArch64PRFM::PRFMMapper::PRFMMapper()
138 : AArch64NamedImmMapper(PRFMMappings, 32) {}
139
140 const AArch64NamedImmMapper::Mapping AArch64PState::PStateMapper::PStateMappings[] = {
141 {"spsel", SPSel, {}},
142 {"daifset", DAIFSet, {}},
143 {"daifclr", DAIFClr, {}},
144
145 // v8.1a "Privileged Access Never" extension-specific PStates
146 {"pan", PAN, {AArch64::HasV8_1aOps}},
147
148 // v8.2a
149 {"uao", UAO, {AArch64::HasV8_2aOps}},
150 };
151
152 AArch64PState::PStateMapper::PStateMapper()
153 : AArch64NamedImmMapper(PStateMappings, 0) {}
154
155 const AArch64NamedImmMapper::Mapping AArch64PSBHint::PSBHintMapper::PSBHintMappings[] = {
156 // v8.2a "Statistical Profiling" extension-specific PSB operand
157 {"csync", CSync, {AArch64::FeatureSPE}},
158 };
159
160 AArch64PSBHint::PSBHintMapper::PSBHintMapper()
161 : AArch64NamedImmMapper(PSBHintMappings, 0) {}
162
163 const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
164 {"mdccsr_el0", MDCCSR_EL0, {}},
165 {"dbgdtrrx_el0", DBGDTRRX_EL0, {}},
166 {"mdrar_el1", MDRAR_EL1, {}},
167 {"oslsr_el1", OSLSR_EL1, {}},
168 {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1, {}},
169 {"pmceid0_el0", PMCEID0_EL0, {}},
170 {"pmceid1_el0", PMCEID1_EL0, {}},
171 {"midr_el1", MIDR_EL1, {}},
172 {"ccsidr_el1", CCSIDR_EL1, {}},
173 {"clidr_el1", CLIDR_EL1, {}},
174 {"ctr_el0", CTR_EL0, {}},
175 {"mpidr_el1", MPIDR_EL1, {}},
176 {"revidr_el1", REVIDR_EL1, {}},
177 {"aidr_el1", AIDR_EL1, {}},
178 {"dczid_el0", DCZID_EL0, {}},
179 {"id_pfr0_el1", ID_PFR0_EL1, {}},
180 {"id_pfr1_el1", ID_PFR1_EL1, {}},
181 {"id_dfr0_el1", ID_DFR0_EL1, {}},
182 {"id_afr0_el1", ID_AFR0_EL1, {}},
183 {"id_mmfr0_el1", ID_MMFR0_EL1, {}},
184 {"id_mmfr1_el1", ID_MMFR1_EL1, {}},
185 {"id_mmfr2_el1", ID_MMFR2_EL1, {}},
186 {"id_mmfr3_el1", ID_MMFR3_EL1, {}},
187 {"id_mmfr4_el1", ID_MMFR4_EL1, {}},
188 {"id_isar0_el1", ID_ISAR0_EL1, {}},
189 {"id_isar1_el1", ID_ISAR1_EL1, {}},
190 {"id_isar2_el1", ID_ISAR2_EL1, {}},
191 {"id_isar3_el1", ID_ISAR3_EL1, {}},
192 {"id_isar4_el1", ID_ISAR4_EL1, {}},
193 {"id_isar5_el1", ID_ISAR5_EL1, {}},
194 {"id_aa64pfr0_el1", ID_A64PFR0_EL1, {}},
195 {"id_aa64pfr1_el1", ID_A64PFR1_EL1, {}},
196 {"id_aa64dfr0_el1", ID_A64DFR0_EL1, {}},
197 {"id_aa64dfr1_el1", ID_A64DFR1_EL1, {}},
198 {"id_aa64afr0_el1", ID_A64AFR0_EL1, {}},
199 {"id_aa64afr1_el1", ID_A64AFR1_EL1, {}},
200 {"id_aa64isar0_el1", ID_A64ISAR0_EL1, {}},
201 {"id_aa64isar1_el1", ID_A64ISAR1_EL1, {}},
202 {"id_aa64mmfr0_el1", ID_A64MMFR0_EL1, {}},
203 {"id_aa64mmfr1_el1", ID_A64MMFR1_EL1, {}},
204 {"id_aa64mmfr2_el1", ID_A64MMFR2_EL1, {AArch64::HasV8_2aOps}},
205 {"mvfr0_el1", MVFR0_EL1, {}},
206 {"mvfr1_el1", MVFR1_EL1, {}},
207 {"mvfr2_el1", MVFR2_EL1, {}},
208 {"rvbar_el1", RVBAR_EL1, {}},
209 {"rvbar_el2", RVBAR_EL2, {}},
210 {"rvbar_el3", RVBAR_EL3, {}},
211 {"isr_el1", ISR_EL1, {}},
212 {"cntpct_el0", CNTPCT_EL0, {}},
213 {"cntvct_el0", CNTVCT_EL0, {}},
214
215 // Trace registers
216 {"trcstatr", TRCSTATR, {}},
217 {"trcidr8", TRCIDR8, {}},
218 {"trcidr9", TRCIDR9, {}},
219 {"trcidr10", TRCIDR10, {}},
220 {"trcidr11", TRCIDR11, {}},
221 {"trcidr12", TRCIDR12, {}},
222 {"trcidr13", TRCIDR13, {}},
223 {"trcidr0", TRCIDR0, {}},
224 {"trcidr1", TRCIDR1, {}},
225 {"trcidr2", TRCIDR2, {}},
226 {"trcidr3", TRCIDR3, {}},
227 {"trcidr4", TRCIDR4, {}},
228 {"trcidr5", TRCIDR5, {}},
229 {"trcidr6", TRCIDR6, {}},
230 {"trcidr7", TRCIDR7, {}},
231 {"trcoslsr", TRCOSLSR, {}},
232 {"trcpdsr", TRCPDSR, {}},
233 {"trcdevaff0", TRCDEVAFF0, {}},
234 {"trcdevaff1", TRCDEVAFF1, {}},
235 {"trclsr", TRCLSR, {}},
236 {"trcauthstatus", TRCAUTHSTATUS, {}},
237 {"trcdevarch", TRCDEVARCH, {}},
238 {"trcdevid", TRCDEVID, {}},
239 {"trcdevtype", TRCDEVTYPE, {}},
240 {"trcpidr4", TRCPIDR4, {}},
241 {"trcpidr5", TRCPIDR5, {}},
242 {"trcpidr6", TRCPIDR6, {}},
243 {"trcpidr7", TRCPIDR7, {}},
244 {"trcpidr0", TRCPIDR0, {}},
245 {"trcpidr1", TRCPIDR1, {}},
246 {"trcpidr2", TRCPIDR2, {}},
247 {"trcpidr3", TRCPIDR3, {}},
248 {"trccidr0", TRCCIDR0, {}},
249 {"trccidr1", TRCCIDR1, {}},
250 {"trccidr2", TRCCIDR2, {}},
251 {"trccidr3", TRCCIDR3, {}},
252
253 // GICv3 registers
254 {"icc_iar1_el1", ICC_IAR1_EL1, {}},
255 {"icc_iar0_el1", ICC_IAR0_EL1, {}},
256 {"icc_hppir1_el1", ICC_HPPIR1_EL1, {}},
257 {"icc_hppir0_el1", ICC_HPPIR0_EL1, {}},
258 {"icc_rpr_el1", ICC_RPR_EL1, {}},
259 {"ich_vtr_el2", ICH_VTR_EL2, {}},
260 {"ich_eisr_el2", ICH_EISR_EL2, {}},
261 {"ich_elsr_el2", ICH_ELSR_EL2, {}},
262
263 // v8.1a "Limited Ordering Regions" extension-specific system registers
264 {"lorid_el1", LORID_EL1, {AArch64::HasV8_1aOps}},
265
266 // v8.2a "Reliability, Availability and Serviceability" extensions registers
267 {"erridr_el1", ERRIDR_EL1, {AArch64::FeatureRAS}},
268 {"erxfr_el1", ERXFR_EL1, {AArch64::FeatureRAS}}
269 };
270
271 AArch64SysReg::MRSMapper::MRSMapper() {
272 InstMappings = &MRSMappings[0];
273 NumInstMappings = llvm::array_lengthof(MRSMappings);
274 }
275
276 const AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRMappings[] = {
277 {"dbgdtrtx_el0", DBGDTRTX_EL0, {}},
278 {"oslar_el1", OSLAR_EL1, {}},
279 {"pmswinc_el0", PMSWINC_EL0, {}},
280
281 // Trace registers
282 {"trcoslar", TRCOSLAR, {}},
283 {"trclar", TRCLAR, {}},
284
285 // GICv3 registers
286 {"icc_eoir1_el1", ICC_EOIR1_EL1, {}},
287 {"icc_eoir0_el1", ICC_EOIR0_EL1, {}},
288 {"icc_dir_el1", ICC_DIR_EL1, {}},
289 {"icc_sgi1r_el1", ICC_SGI1R_EL1, {}},
290 {"icc_asgi1r_el1", ICC_ASGI1R_EL1, {}},
291 {"icc_sgi0r_el1", ICC_SGI0R_EL1, {}},
292 };
293
294 AArch64SysReg::MSRMapper::MSRMapper() {
295 InstMappings = &MSRMappings[0];
296 NumInstMappings = llvm::array_lengthof(MSRMappings);
29725 }
29826
29927
300 const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = {
301 {"osdtrrx_el1", OSDTRRX_EL1, {}},
302 {"osdtrtx_el1", OSDTRTX_EL1, {}},
303 {"teecr32_el1", TEECR32_EL1, {}},
304 {"mdccint_el1", MDCCINT_EL1, {}},
305 {"mdscr_el1", MDSCR_EL1, {}},
306 {"dbgdtr_el0", DBGDTR_EL0, {}},
307 {"oseccr_el1", OSECCR_EL1, {}},
308 {"dbgvcr32_el2", DBGVCR32_EL2, {}},
309 {"dbgbvr0_el1", DBGBVR0_EL1, {}},
310 {"dbgbvr1_el1", DBGBVR1_EL1, {}},
311 {"dbgbvr2_el1", DBGBVR2_EL1, {}},
312 {"dbgbvr3_el1", DBGBVR3_EL1, {}},
313 {"dbgbvr4_el1", DBGBVR4_EL1, {}},
314 {"dbgbvr5_el1", DBGBVR5_EL1, {}},
315 {"dbgbvr6_el1", DBGBVR6_EL1, {}},
316 {"dbgbvr7_el1", DBGBVR7_EL1, {}},
317 {"dbgbvr8_el1", DBGBVR8_EL1, {}},
318 {"dbgbvr9_el1", DBGBVR9_EL1, {}},
319 {"dbgbvr10_el1", DBGBVR10_EL1, {}},
320 {"dbgbvr11_el1", DBGBVR11_EL1, {}},
321 {"dbgbvr12_el1", DBGBVR12_EL1, {}},
322 {"dbgbvr13_el1", DBGBVR13_EL1, {}},
323 {"dbgbvr14_el1", DBGBVR14_EL1, {}},
324 {"dbgbvr15_el1", DBGBVR15_EL1, {}},
325 {"dbgbcr0_el1", DBGBCR0_EL1, {}},
326 {"dbgbcr1_el1", DBGBCR1_EL1, {}},
327 {"dbgbcr2_el1", DBGBCR2_EL1, {}},
328 {"dbgbcr3_el1", DBGBCR3_EL1, {}},
329 {"dbgbcr4_el1", DBGBCR4_EL1, {}},
330 {"dbgbcr5_el1", DBGBCR5_EL1, {}},
331 {"dbgbcr6_el1", DBGBCR6_EL1, {}},
332 {"dbgbcr7_el1", DBGBCR7_EL1, {}},
333 {"dbgbcr8_el1", DBGBCR8_EL1, {}},
334 {"dbgbcr9_el1", DBGBCR9_EL1, {}},
335 {"dbgbcr10_el1", DBGBCR10_EL1, {}},
336 {"dbgbcr11_el1", DBGBCR11_EL1, {}},
337 {"dbgbcr12_el1", DBGBCR12_EL1, {}},
338 {"dbgbcr13_el1", DBGBCR13_EL1, {}},
339 {"dbgbcr14_el1", DBGBCR14_EL1, {}},
340 {"dbgbcr15_el1", DBGBCR15_EL1, {}},
341 {"dbgwvr0_el1", DBGWVR0_EL1, {}},
342 {"dbgwvr1_el1", DBGWVR1_EL1, {}},
343 {"dbgwvr2_el1", DBGWVR2_EL1, {}},
344 {"dbgwvr3_el1", DBGWVR3_EL1, {}},
345 {"dbgwvr4_el1", DBGWVR4_EL1, {}},
346 {"dbgwvr5_el1", DBGWVR5_EL1, {}},
347 {"dbgwvr6_el1", DBGWVR6_EL1, {}},
348 {"dbgwvr7_el1", DBGWVR7_EL1, {}},
349 {"dbgwvr8_el1", DBGWVR8_EL1, {}},
350 {"dbgwvr9_el1", DBGWVR9_EL1, {}},
351 {"dbgwvr10_el1", DBGWVR10_EL1, {}},
352 {"dbgwvr11_el1", DBGWVR11_EL1, {}},
353 {"dbgwvr12_el1", DBGWVR12_EL1, {}},
354 {"dbgwvr13_el1", DBGWVR13_EL1, {}},
355 {"dbgwvr14_el1", DBGWVR14_EL1, {}},
356 {"dbgwvr15_el1", DBGWVR15_EL1, {}},
357 {"dbgwcr0_el1", DBGWCR0_EL1, {}},
358 {"dbgwcr1_el1", DBGWCR1_EL1, {}},
359 {"dbgwcr2_el1", DBGWCR2_EL1, {}},
360 {"dbgwcr3_el1", DBGWCR3_EL1, {}},
361 {"dbgwcr4_el1", DBGWCR4_EL1, {}},
362 {"dbgwcr5_el1", DBGWCR5_EL1, {}},
363 {"dbgwcr6_el1", DBGWCR6_EL1, {}},
364 {"dbgwcr7_el1", DBGWCR7_EL1, {}},
365 {"dbgwcr8_el1", DBGWCR8_EL1, {}},
366 {"dbgwcr9_el1", DBGWCR9_EL1, {}},
367 {"dbgwcr10_el1", DBGWCR10_EL1, {}},
368 {"dbgwcr11_el1", DBGWCR11_EL1, {}},
369 {"dbgwcr12_el1", DBGWCR12_EL1, {}},
370 {"dbgwcr13_el1", DBGWCR13_EL1, {}},
371 {"dbgwcr14_el1", DBGWCR14_EL1, {}},
372 {"dbgwcr15_el1", DBGWCR15_EL1, {}},
373 {"teehbr32_el1", TEEHBR32_EL1, {}},
374 {"osdlr_el1", OSDLR_EL1, {}},
375 {"dbgprcr_el1", DBGPRCR_EL1, {}},
376 {"dbgclaimset_el1", DBGCLAIMSET_EL1, {}},
377 {"dbgclaimclr_el1", DBGCLAIMCLR_EL1, {}},
378 {"csselr_el1", CSSELR_EL1, {}},
379 {"vpidr_el2", VPIDR_EL2, {}},
380 {"vmpidr_el2", VMPIDR_EL2, {}},
381 {"sctlr_el1", SCTLR_EL1, {}},
382 {"sctlr_el2", SCTLR_EL2, {}},
383 {"sctlr_el3", SCTLR_EL3, {}},
384 {"actlr_el1", ACTLR_EL1, {}},
385 {"actlr_el2", ACTLR_EL2, {}},
386 {"actlr_el3", ACTLR_EL3, {}},
387 {"cpacr_el1", CPACR_EL1, {}},
388 {"hcr_el2", HCR_EL2, {}},
389 {"scr_el3", SCR_EL3, {}},
390 {"mdcr_el2", MDCR_EL2, {}},
391 {"sder32_el3", SDER32_EL3, {}},
392 {"cptr_el2", CPTR_EL2, {}},
393 {"cptr_el3", CPTR_EL3, {}},
394 {"hstr_el2", HSTR_EL2, {}},
395 {"hacr_el2", HACR_EL2, {}},
396 {"mdcr_el3", MDCR_EL3, {}},
397 {"ttbr0_el1", TTBR0_EL1, {}},
398 {"ttbr0_el2", TTBR0_EL2, {}},
399 {"ttbr0_el3", TTBR0_EL3, {}},
400 {"ttbr1_el1", TTBR1_EL1, {}},
401 {"tcr_el1", TCR_EL1, {}},
402 {"tcr_el2", TCR_EL2, {}},
403 {"tcr_el3", TCR_EL3, {}},
404 {"vttbr_el2", VTTBR_EL2, {}},
405 {"vtcr_el2", VTCR_EL2, {}},
406 {"dacr32_el2", DACR32_EL2, {}},
407 {"spsr_el1", SPSR_EL1, {}},
408 {"spsr_el2", SPSR_EL2, {}},
409 {"spsr_el3", SPSR_EL3, {}},
410 {"elr_el1", ELR_EL1, {}},
411 {"elr_el2", ELR_EL2, {}},
412 {"elr_el3", ELR_EL3, {}},
413 {"sp_el0", SP_EL0, {}},
414 {"sp_el1", SP_EL1, {}},
415 {"sp_el2", SP_EL2, {}},
416 {"spsel", SPSel, {}},
417 {"nzcv", NZCV, {}},
418 {"daif", DAIF, {}},
419 {"currentel", CurrentEL, {}},
420 {"spsr_irq", SPSR_irq, {}},
421 {"spsr_abt", SPSR_abt, {}},
422 {"spsr_und", SPSR_und, {}},
423 {"spsr_fiq", SPSR_fiq, {}},
424 {"fpcr", FPCR, {}},
425 {"fpsr", FPSR, {}},
426 {"dspsr_el0", DSPSR_EL0, {}},
427 {"dlr_el0", DLR_EL0, {}},
428 {"ifsr32_el2", IFSR32_EL2, {}},
429 {"afsr0_el1", AFSR0_EL1, {}},
430 {"afsr0_el2", AFSR0_EL2, {}},
431 {"afsr0_el3", AFSR0_EL3, {}},
432 {"afsr1_el1", AFSR1_EL1, {}},
433 {"afsr1_el2", AFSR1_EL2, {}},
434 {"afsr1_el3", AFSR1_EL3, {}},
435 {"esr_el1", ESR_EL1, {}},
436 {"esr_el2", ESR_EL2, {}},
437 {"esr_el3", ESR_EL3, {}},
438 {"fpexc32_el2", FPEXC32_EL2, {}},
439 {"far_el1", FAR_EL1, {}},
440 {"far_el2", FAR_EL2, {}},
441 {"far_el3", FAR_EL3, {}},
442 {"hpfar_el2", HPFAR_EL2, {}},
443 {"par_el1", PAR_EL1, {}},
444 {"pmcr_el0", PMCR_EL0, {}},
445 {"pmcntenset_el0", PMCNTENSET_EL0, {}},
446 {"pmcntenclr_el0", PMCNTENCLR_EL0, {}},
447 {"pmovsclr_el0", PMOVSCLR_EL0, {}},
448 {"pmselr_el0", PMSELR_EL0, {}},
449 {"pmccntr_el0", PMCCNTR_EL0, {}},
450 {"pmxevtyper_el0", PMXEVTYPER_EL0, {}},
451 {"pmxevcntr_el0", PMXEVCNTR_EL0, {}},
452 {"pmuserenr_el0", PMUSERENR_EL0, {}},
453 {"pmintenset_el1", PMINTENSET_EL1, {}},
454 {"pmintenclr_el1", PMINTENCLR_EL1, {}},
455 {"pmovsset_el0", PMOVSSET_EL0, {}},
456 {"mair_el1", MAIR_EL1, {}},
457 {"mair_el2", MAIR_EL2, {}},
458 {"mair_el3", MAIR_EL3, {}},
459 {"amair_el1", AMAIR_EL1, {}},
460 {"amair_el2", AMAIR_EL2, {}},
461 {"amair_el3", AMAIR_EL3, {}},
462 {"vbar_el1", VBAR_EL1, {}},
463 {"vbar_el2", VBAR_EL2, {}},
464 {"vbar_el3", VBAR_EL3, {}},
465 {"rmr_el1", RMR_EL1, {}},
466 {"rmr_el2", RMR_EL2, {}},
467 {"rmr_el3", RMR_EL3, {}},
468 {"contextidr_el1", CONTEXTIDR_EL1, {}},
469 {"tpidr_el0", TPIDR_EL0, {}},
470 {"tpidr_el2", TPIDR_EL2, {}},
471 {"tpidr_el3", TPIDR_EL3, {}},
472 {"tpidrro_el0", TPIDRRO_EL0, {}},
473 {"tpidr_el1", TPIDR_EL1, {}},
474 {"cntfrq_el0", CNTFRQ_EL0, {}},
475 {"cntvoff_el2", CNTVOFF_EL2, {}},
476 {"cntkctl_el1", CNTKCTL_EL1, {}},
477 {"cnthctl_el2", CNTHCTL_EL2, {}},
478 {"cntp_tval_el0", CNTP_TVAL_EL0, {}},
479 {"cnthp_tval_el2", CNTHP_TVAL_EL2, {}},
480 {"cntps_tval_el1", CNTPS_TVAL_EL1, {}},
481 {"cntp_ctl_el0", CNTP_CTL_EL0, {}},
482 {"cnthp_ctl_el2", CNTHP_CTL_EL2, {}},
483 {"cntps_ctl_el1", CNTPS_CTL_EL1, {}},
484 {"cntp_cval_el0", CNTP_CVAL_EL0, {}},
485 {"cnthp_cval_el2", CNTHP_CVAL_EL2, {}},
486 {"cntps_cval_el1", CNTPS_CVAL_EL1, {}},
487 {"cntv_tval_el0", CNTV_TVAL_EL0, {}},
488 {"cntv_ctl_el0", CNTV_CTL_EL0, {}},
489 {"cntv_cval_el0", CNTV_CVAL_EL0, {}},
490 {"pmevcntr0_el0", PMEVCNTR0_EL0, {}},
491 {"pmevcntr1_el0", PMEVCNTR1_EL0, {}},
492 {"pmevcntr2_el0", PMEVCNTR2_EL0, {}},
493 {"pmevcntr3_el0", PMEVCNTR3_EL0, {}},
494 {"pmevcntr4_el0", PMEVCNTR4_EL0, {}},
495 {"pmevcntr5_el0", PMEVCNTR5_EL0, {}},
496 {"pmevcntr6_el0", PMEVCNTR6_EL0, {}},
497 {"pmevcntr7_el0", PMEVCNTR7_EL0, {}},
498 {"pmevcntr8_el0", PMEVCNTR8_EL0, {}},
499 {"pmevcntr9_el0", PMEVCNTR9_EL0, {}},
500 {"pmevcntr10_el0", PMEVCNTR10_EL0, {}},
501 {"pmevcntr11_el0", PMEVCNTR11_EL0, {}},
502 {"pmevcntr12_el0", PMEVCNTR12_EL0, {}},
503 {"pmevcntr13_el0", PMEVCNTR13_EL0, {}},
504 {"pmevcntr14_el0", PMEVCNTR14_EL0, {}},
505 {"pmevcntr15_el0", PMEVCNTR15_EL0, {}},
506 {"pmevcntr16_el0", PMEVCNTR16_EL0, {}},
507 {"pmevcntr17_el0", PMEVCNTR17_EL0, {}},
508 {"pmevcntr18_el0", PMEVCNTR18_EL0, {}},
509 {"pmevcntr19_el0", PMEVCNTR19_EL0, {}},
510 {"pmevcntr20_el0", PMEVCNTR20_EL0, {}},
511 {"pmevcntr21_el0", PMEVCNTR21_EL0, {}},
512 {"pmevcntr22_el0", PMEVCNTR22_EL0, {}},
513 {"pmevcntr23_el0", PMEVCNTR23_EL0, {}},
514 {"pmevcntr24_el0", PMEVCNTR24_EL0, {}},
515 {"pmevcntr25_el0", PMEVCNTR25_EL0, {}},
516 {"pmevcntr26_el0", PMEVCNTR26_EL0, {}},
517 {"pmevcntr27_el0", PMEVCNTR27_EL0, {}},
518 {"pmevcntr28_el0", PMEVCNTR28_EL0, {}},
519 {"pmevcntr29_el0", PMEVCNTR29_EL0, {}},
520 {"pmevcntr30_el0", PMEVCNTR30_EL0, {}},
521 {"pmccfiltr_el0", PMCCFILTR_EL0, {}},
522 {"pmevtyper0_el0", PMEVTYPER0_EL0, {}},
523 {"pmevtyper1_el0", PMEVTYPER1_EL0, {}},
524 {"pmevtyper2_el0", PMEVTYPER2_EL0, {}},
525 {"pmevtyper3_el0", PMEVTYPER3_EL0, {}},
526 {"pmevtyper4_el0", PMEVTYPER4_EL0, {}},
527 {"pmevtyper5_el0", PMEVTYPER5_EL0, {}},
528 {"pmevtyper6_el0", PMEVTYPER6_EL0, {}},
529 {"pmevtyper7_el0", PMEVTYPER7_EL0, {}},
530 {"pmevtyper8_el0", PMEVTYPER8_EL0, {}},
531 {"pmevtyper9_el0", PMEVTYPER9_EL0, {}},
532 {"pmevtyper10_el0", PMEVTYPER10_EL0, {}},
533 {"pmevtyper11_el0", PMEVTYPER11_EL0, {}},
534 {"pmevtyper12_el0", PMEVTYPER12_EL0, {}},
535 {"pmevtyper13_el0", PMEVTYPER13_EL0, {}},
536 {"pmevtyper14_el0", PMEVTYPER14_EL0, {}},
537 {"pmevtyper15_el0", PMEVTYPER15_EL0, {}},
538 {"pmevtyper16_el0", PMEVTYPER16_EL0, {}},
539 {"pmevtyper17_el0", PMEVTYPER17_EL0, {}},
540 {"pmevtyper18_el0", PMEVTYPER18_EL0, {}},
541 {"pmevtyper19_el0", PMEVTYPER19_EL0, {}},
542 {"pmevtyper20_el0", PMEVTYPER20_EL0, {}},
543 {"pmevtyper21_el0", PMEVTYPER21_EL0, {}},
544 {"pmevtyper22_el0", PMEVTYPER22_EL0, {}},
545 {"pmevtyper23_el0", PMEVTYPER23_EL0, {}},
546 {"pmevtyper24_el0", PMEVTYPER24_EL0, {}},
547 {"pmevtyper25_el0", PMEVTYPER25_EL0, {}},
548 {"pmevtyper26_el0", PMEVTYPER26_EL0, {}},
549 {"pmevtyper27_el0", PMEVTYPER27_EL0, {}},
550 {"pmevtyper28_el0", PMEVTYPER28_EL0, {}},
551 {"pmevtyper29_el0", PMEVTYPER29_EL0, {}},
552 {"pmevtyper30_el0", PMEVTYPER30_EL0, {}},
28 namespace llvm {
29 namespace AArch64DB {
30 #define GET_DB_IMPL
31 #include "AArch64GenSystemOperands.inc"
32 }
33 }
55334
554 // Trace registers
555 {"trcprgctlr", TRCPRGCTLR, {}},
556 {"trcprocselr", TRCPROCSELR, {}},
557 {"trcconfigr", TRCCONFIGR, {}},
558 {"trcauxctlr", TRCAUXCTLR, {}},
559 {"trceventctl0r", TRCEVENTCTL0R, {}},
560 {"trceventctl1r", TRCEVENTCTL1R, {}},
561 {"trcstallctlr", TRCSTALLCTLR, {}},
562 {"trctsctlr", TRCTSCTLR, {}},
563 {"trcsyncpr", TRCSYNCPR, {}},
564 {"trcccctlr", TRCCCCTLR, {}},
565 {"trcbbctlr", TRCBBCTLR, {}},
566 {"trctraceidr", TRCTRACEIDR, {}},
567 {"trcqctlr", TRCQCTLR, {}},
568 {"trcvictlr", TRCVICTLR, {}},
569 {"trcviiectlr", TRCVIIECTLR, {}},
570 {"trcvissctlr", TRCVISSCTLR, {}},
571 {"trcvipcssctlr", TRCVIPCSSCTLR, {}},
572 {"trcvdctlr", TRCVDCTLR, {}},
573 {"trcvdsacctlr", TRCVDSACCTLR, {}},
574 {"trcvdarcctlr", TRCVDARCCTLR, {}},
575 {"trcseqevr0", TRCSEQEVR0, {}},
576 {"trcseqevr1", TRCSEQEVR1, {}},
577 {"trcseqevr2", TRCSEQEVR2, {}},
578 {"trcseqrstevr", TRCSEQRSTEVR, {}},
579 {"trcseqstr", TRCSEQSTR, {}},
580 {"trcextinselr", TRCEXTINSELR, {}},
581 {"trccntrldvr0", TRCCNTRLDVR0, {}},
582 {"trccntrldvr1", TRCCNTRLDVR1, {}},
583 {"trccntrldvr2", TRCCNTRLDVR2, {}},
584 {"trccntrldvr3", TRCCNTRLDVR3, {}},
585 {"trccntctlr0", TRCCNTCTLR0, {}},
586 {"trccntctlr1", TRCCNTCTLR1, {}},
587 {"trccntctlr2", TRCCNTCTLR2, {}},
588 {"trccntctlr3", TRCCNTCTLR3, {}},
589 {"trccntvr0", TRCCNTVR0, {}},
590 {"trccntvr1", TRCCNTVR1, {}},
591 {"trccntvr2", TRCCNTVR2, {}},
592 {"trccntvr3", TRCCNTVR3, {}},
593 {"trcimspec0", TRCIMSPEC0, {}},
594 {"trcimspec1", TRCIMSPEC1, {}},
595 {"trcimspec2", TRCIMSPEC2, {}},
596 {"trcimspec3", TRCIMSPEC3, {}},
597 {"trcimspec4", TRCIMSPEC4, {}},
598 {"trcimspec5", TRCIMSPEC5, {}},
599 {"trcimspec6", TRCIMSPEC6, {}},
600 {"trcimspec7", TRCIMSPEC7, {}},
601 {"trcrsctlr2", TRCRSCTLR2, {}},
602 {"trcrsctlr3", TRCRSCTLR3, {}},
603 {"trcrsctlr4", TRCRSCTLR4, {}},
604 {"trcrsctlr5", TRCRSCTLR5, {}},
605 {"trcrsctlr6", TRCRSCTLR6, {}},
606 {"trcrsctlr7", TRCRSCTLR7, {}},
607 {"trcrsctlr8", TRCRSCTLR8, {}},
608 {"trcrsctlr9", TRCRSCTLR9, {}},
609 {"trcrsctlr10", TRCRSCTLR10, {}},
610 {"trcrsctlr11", TRCRSCTLR11, {}},
611 {"trcrsctlr12", TRCRSCTLR12, {}},
612 {"trcrsctlr13", TRCRSCTLR13, {}},
613 {"trcrsctlr14", TRCRSCTLR14, {}},
614 {"trcrsctlr15", TRCRSCTLR15, {}},
615 {"trcrsctlr16", TRCRSCTLR16, {}},
616 {"trcrsctlr17", TRCRSCTLR17, {}},
617 {"trcrsctlr18", TRCRSCTLR18, {}},
618 {"trcrsctlr19", TRCRSCTLR19, {}},
619 {"trcrsctlr20", TRCRSCTLR20, {}},
620 {"trcrsctlr21", TRCRSCTLR21, {}},
621 {"trcrsctlr22", TRCRSCTLR22, {}},
622 {"trcrsctlr23", TRCRSCTLR23, {}},
623 {"trcrsctlr24", TRCRSCTLR24, {}},
624 {"trcrsctlr25", TRCRSCTLR25, {}},
625 {"trcrsctlr26", TRCRSCTLR26, {}},
626 {"trcrsctlr27", TRCRSCTLR27, {}},
627 {"trcrsctlr28", TRCRSCTLR28, {}},
628 {"trcrsctlr29", TRCRSCTLR29, {}},
629 {"trcrsctlr30", TRCRSCTLR30, {}},
630 {"trcrsctlr31", TRCRSCTLR31, {}},
631 {"trcssccr0", TRCSSCCR0, {}},
632 {"trcssccr1", TRCSSCCR1, {}},
633 {"trcssccr2", TRCSSCCR2, {}},
634 {"trcssccr3", TRCSSCCR3, {}},
635 {"trcssccr4", TRCSSCCR4, {}},
636 {"trcssccr5", TRCSSCCR5, {}},
637 {"trcssccr6", TRCSSCCR6, {}},
638 {"trcssccr7", TRCSSCCR7, {}},
639 {"trcsscsr0", TRCSSCSR0, {}},
640 {"trcsscsr1", TRCSSCSR1, {}},
641 {"trcsscsr2", TRCSSCSR2, {}},
642 {"trcsscsr3", TRCSSCSR3, {}},
643 {"trcsscsr4", TRCSSCSR4, {}},
644 {"trcsscsr5", TRCSSCSR5, {}},
645 {"trcsscsr6", TRCSSCSR6, {}},
646 {"trcsscsr7", TRCSSCSR7, {}},
647 {"trcsspcicr0", TRCSSPCICR0, {}},
648 {"trcsspcicr1", TRCSSPCICR1, {}},
649 {"trcsspcicr2", TRCSSPCICR2, {}},
650 {"trcsspcicr3", TRCSSPCICR3, {}},
651 {"trcsspcicr4", TRCSSPCICR4, {}},
652 {"trcsspcicr5", TRCSSPCICR5, {}},
653 {"trcsspcicr6", TRCSSPCICR6, {}},
654 {"trcsspcicr7", TRCSSPCICR7, {}},
655 {"trcpdcr", TRCPDCR, {}},
656 {"trcacvr0", TRCACVR0, {}},
657 {"trcacvr1", TRCACVR1, {}},
658 {"trcacvr2", TRCACVR2, {}},
659 {"trcacvr3", TRCACVR3, {}},
660 {"trcacvr4", TRCACVR4, {}},
661 {"trcacvr5", TRCACVR5, {}},
662 {"trcacvr6", TRCACVR6, {}},
663 {"trcacvr7", TRCACVR7, {}},
664 {"trcacvr8", TRCACVR8, {}},
665 {"trcacvr9", TRCACVR9, {}},
666 {"trcacvr10", TRCACVR10, {}},
667 {"trcacvr11", TRCACVR11, {}},
668 {"trcacvr12", TRCACVR12, {}},
669 {"trcacvr13", TRCACVR13, {}},
670 {"trcacvr14", TRCACVR14, {}},
671 {"trcacvr15", TRCACVR15, {}},
672 {"trcacatr0", TRCACATR0, {}},
673 {"trcacatr1", TRCACATR1, {}},
674 {"trcacatr2", TRCACATR2, {}},
675 {"trcacatr3", TRCACATR3, {}},
676 {"trcacatr4", TRCACATR4, {}},
677 {"trcacatr5", TRCACATR5, {}},
678 {"trcacatr6", TRCACATR6, {}},
679 {"trcacatr7", TRCACATR7, {}},
680 {"trcacatr8", TRCACATR8, {}},
681 {"trcacatr9", TRCACATR9, {}},
682 {"trcacatr10", TRCACATR10, {}},
683 {"trcacatr11", TRCACATR11, {}},
684 {"trcacatr12", TRCACATR12, {}},
685 {"trcacatr13", TRCACATR13, {}},
686 {"trcacatr14", TRCACATR14, {}},
687 {"trcacatr15", TRCACATR15, {}},
688 {"trcdvcvr0", TRCDVCVR0, {}},
689 {"trcdvcvr1", TRCDVCVR1, {}},
690 {"trcdvcvr2", TRCDVCVR2, {}},
691 {"trcdvcvr3", TRCDVCVR3, {}},
692 {"trcdvcvr4", TRCDVCVR4, {}},
693 {"trcdvcvr5", TRCDVCVR5, {}},
694 {"trcdvcvr6", TRCDVCVR6, {}},
695 {"trcdvcvr7", TRCDVCVR7, {}},
696 {"trcdvcmr0", TRCDVCMR0, {}},
697 {"trcdvcmr1", TRCDVCMR1, {}},
698 {"trcdvcmr2", TRCDVCMR2, {}},
699 {"trcdvcmr3", TRCDVCMR3, {}},
700 {"trcdvcmr4", TRCDVCMR4, {}},
701 {"trcdvcmr5", TRCDVCMR5, {}},
702 {"trcdvcmr6", TRCDVCMR6, {}},
703 {"trcdvcmr7", TRCDVCMR7, {}},
704 {"trccidcvr0", TRCCIDCVR0, {}},
705 {"trccidcvr1", TRCCIDCVR1, {}},
706 {"trccidcvr2", TRCCIDCVR2, {}},
707 {"trccidcvr3", TRCCIDCVR3, {}},
708 {"trccidcvr4", TRCCIDCVR4, {}},
709 {"trccidcvr5", TRCCIDCVR5, {}},
710 {"trccidcvr6", TRCCIDCVR6, {}},
711 {"trccidcvr7", TRCCIDCVR7, {}},
712 {"trcvmidcvr0", TRCVMIDCVR0, {}},
713 {"trcvmidcvr1", TRCVMIDCVR1, {}},
714 {"trcvmidcvr2", TRCVMIDCVR2, {}},
715 {"trcvmidcvr3", TRCVMIDCVR3, {}},
716 {"trcvmidcvr4", TRCVMIDCVR4, {}},
717 {"trcvmidcvr5", TRCVMIDCVR5, {}},
718 {"trcvmidcvr6", TRCVMIDCVR6, {}},
719 {"trcvmidcvr7", TRCVMIDCVR7, {}},
720 {"trccidcctlr0", TRCCIDCCTLR0, {}},
721 {"trccidcctlr1", TRCCIDCCTLR1, {}},
722 {"trcvmidcctlr0", TRCVMIDCCTLR0, {}},
723 {"trcvmidcctlr1", TRCVMIDCCTLR1, {}},
724 {"trcitctrl", TRCITCTRL, {}},
725 {"trcclaimset", TRCCLAIMSET, {}},
726 {"trcclaimclr", TRCCLAIMCLR, {}},
35 namespace llvm {
36 namespace AArch64DC {
37 #define GET_DC_IMPL
38 #include "AArch64GenSystemOperands.inc"
39 }
40 }
72741
728 // GICv3 registers
729 {"icc_bpr1_el1", ICC_BPR1_EL1, {}},
730 {"icc_bpr0_el1", ICC_BPR0_EL1, {}},
731 {"icc_pmr_el1", ICC_PMR_EL1, {}},
732 {"icc_ctlr_el1", ICC_CTLR_EL1, {}},
733 {"icc_ctlr_el3", ICC_CTLR_EL3, {}},
734 {"icc_sre_el1", ICC_SRE_EL1, {}},
735 {"icc_sre_el2", ICC_SRE_EL2, {}},
736 {"icc_sre_el3", ICC_SRE_EL3, {}},
737 {"icc_igrpen0_el1", ICC_IGRPEN0_EL1, {}},
738 {"icc_igrpen1_el1", ICC_IGRPEN1_EL1, {}},
739 {"icc_igrpen1_el3", ICC_IGRPEN1_EL3, {}},
740 {"icc_seien_el1", ICC_SEIEN_EL1, {}},
741 {"icc_ap0r0_el1", ICC_AP0R0_EL1, {}},
742 {"icc_ap0r1_el1", ICC_AP0R1_EL1, {}},
743 {"icc_ap0r2_el1", ICC_AP0R2_EL1, {}},
744 {"icc_ap0r3_el1", ICC_AP0R3_EL1, {}},
745 {"icc_ap1r0_el1", ICC_AP1R0_EL1, {}},
746 {"icc_ap1r1_el1", ICC_AP1R1_EL1, {}},
747 {"icc_ap1r2_el1", ICC_AP1R2_EL1, {}},
748 {"icc_ap1r3_el1", ICC_AP1R3_EL1, {}},
749 {"ich_ap0r0_el2", ICH_AP0R0_EL2, {}},
750 {"ich_ap0r1_el2", ICH_AP0R1_EL2, {}},
751 {"ich_ap0r2_el2", ICH_AP0R2_EL2, {}},
752 {"ich_ap0r3_el2", ICH_AP0R3_EL2, {}},
753 {"ich_ap1r0_el2", ICH_AP1R0_EL2, {}},
754 {"ich_ap1r1_el2", ICH_AP1R1_EL2, {}},
755 {"ich_ap1r2_el2", ICH_AP1R2_EL2, {}},
756 {"ich_ap1r3_el2", ICH_AP1R3_EL2, {}},
757 {"ich_hcr_el2", ICH_HCR_EL2, {}},
758 {"ich_misr_el2", ICH_MISR_EL2, {}},
759 {"ich_vmcr_el2", ICH_VMCR_EL2, {}},
760 {"ich_vseir_el2", ICH_VSEIR_EL2, {}},
761 {"ich_lr0_el2", ICH_LR0_EL2, {}},
762 {"ich_lr1_el2", ICH_LR1_EL2, {}},
763 {"ich_lr2_el2", ICH_LR2_EL2, {}},
764 {"ich_lr3_el2", ICH_LR3_EL2, {}},
765 {"ich_lr4_el2", ICH_LR4_EL2, {}},
766 {"ich_lr5_el2", ICH_LR5_EL2, {}},
767 {"ich_lr6_el2", ICH_LR6_EL2, {}},
768 {"ich_lr7_el2", ICH_LR7_EL2, {}},
769 {"ich_lr8_el2", ICH_LR8_EL2, {}},
770 {"ich_lr9_el2", ICH_LR9_EL2, {}},
771 {"ich_lr10_el2", ICH_LR10_EL2, {}},
772 {"ich_lr11_el2", ICH_LR11_EL2, {}},
773 {"ich_lr12_el2", ICH_LR12_EL2, {}},
774 {"ich_lr13_el2", ICH_LR13_EL2, {}},
775 {"ich_lr14_el2", ICH_LR14_EL2, {}},
776 {"ich_lr15_el2", ICH_LR15_EL2, {}},
42 namespace llvm {
43 namespace AArch64IC {
44 #define GET_IC_IMPL
45 #include "AArch64GenSystemOperands.inc"
46 }
47 }
77748
778 // Cyclone registers
779 {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3, {AArch64::ProcCyclone}},
49 namespace llvm {
50 namespace AArch64ISB {
51 #define GET_ISB_IMPL
52 #include "AArch64GenSystemOperands.inc"
53 }
54 }
55 namespace llvm {
56 namespace AArch64PRFM {
57 #define GET_PRFM_IMPL
58 #include "AArch64GenSystemOperands.inc"
59 }
60 }
78061
781 // v8.1a "Privileged Access Never" extension-specific system registers
782 {"pan", PAN, {AArch64::HasV8_1aOps}},
62 namespace llvm {
63 namespace AArch64PState {
64 #define GET_PSTATE_IMPL
65 #include "AArch64GenSystemOperands.inc"
66 }
67 }
78368
784 // v8.1a "Limited Ordering Regions" extension-specific system registers
785 {"lorsa_el1", LORSA_EL1, {AArch64::HasV8_1aOps}},
786 {"lorea_el1", LOREA_EL1, {AArch64::HasV8_1aOps}},
787 {"lorn_el1", LORN_EL1, {AArch64::HasV8_1aOps}},
788 {"lorc_el1", LORC_EL1, {AArch64::HasV8_1aOps}},
69 namespace llvm {
70 namespace AArch64PSBHint {
71 #define GET_PSB_IMPL
72 #include "AArch64GenSystemOperands.inc"
73 }
74 }
78975
790 // v8.1a "Virtualization host extensions" system registers
791 {"ttbr1_el2", TTBR1_EL2, {AArch64::HasV8_1aOps}},
792 {"contextidr_el2", CONTEXTIDR_EL2, {AArch64::HasV8_1aOps}},
793 {"cnthv_tval_el2", CNTHV_TVAL_EL2, {AArch64::HasV8_1aOps}},
794 {"cnthv_cval_el2", CNTHV_CVAL_EL2, {AArch64::HasV8_1aOps}},
795 {"cnthv_ctl_el2", CNTHV_CTL_EL2, {AArch64::HasV8_1aOps}},
796 {"sctlr_el12", SCTLR_EL12, {AArch64::HasV8_1aOps}},
797 {"cpacr_el12", CPACR_EL12, {AArch64::HasV8_1aOps}},
798 {"ttbr0_el12", TTBR0_EL12, {AArch64::HasV8_1aOps}},
799 {"ttbr1_el12", TTBR1_EL12, {AArch64::HasV8_1aOps}},
800 {"tcr_el12", TCR_EL12, {AArch64::HasV8_1aOps}},
801 {"afsr0_el12", AFSR0_EL12, {AArch64::HasV8_1aOps}},
802 {"afsr1_el12", AFSR1_EL12, {AArch64::HasV8_1aOps}},
803 {"esr_el12", ESR_EL12, {AArch64::HasV8_1aOps}},
804 {"far_el12", FAR_EL12, {AArch64::HasV8_1aOps}},
805 {"mair_el12", MAIR_EL12, {AArch64::HasV8_1aOps}},
806 {"amair_el12", AMAIR_EL12, {AArch64::HasV8_1aOps}},
807 {"vbar_el12", VBAR_EL12, {AArch64::HasV8_1aOps}},
808 {"contextidr_el12", CONTEXTIDR_EL12, {AArch64::HasV8_1aOps}},
809 {"cntkctl_el12", CNTKCTL_EL12, {AArch64::HasV8_1aOps}},
810 {"cntp_tval_el02", CNTP_TVAL_EL02, {AArch64::HasV8_1aOps}},
811 {"cntp_ctl_el02", CNTP_CTL_EL02, {AArch64::HasV8_1aOps}},
812 {"cntp_cval_el02", CNTP_CVAL_EL02, {AArch64::HasV8_1aOps}},
813 {"cntv_tval_el02", CNTV_TVAL_EL02, {AArch64::HasV8_1aOps}},
814 {"cntv_ctl_el02", CNTV_CTL_EL02, {AArch64::HasV8_1aOps}},
815 {"cntv_cval_el02", CNTV_CVAL_EL02, {AArch64::HasV8_1aOps}},
816 {"spsr_el12", SPSR_EL12, {AArch64::HasV8_1aOps}},
817 {"elr_el12", ELR_EL12, {AArch64::HasV8_1aOps}},
76 namespace llvm {
77 namespace AArch64SysReg {
78 #define GET_SYSREG_IMPL
79 #include "AArch64GenSystemOperands.inc"
80 }
81 }
81882
819 // v8.2a registers
820 {"uao", UAO, {AArch64::HasV8_2aOps}},
821
822 // v8.2a "Reliability, Availability and Serviceability" extensions registers
823 {"errselr_el1", ERRSELR_EL1, {AArch64::FeatureRAS}},
824 {"erxctlr_el1", ERXCTLR_EL1, {AArch64::FeatureRAS}},
825 {"erxstatus_el1", ERXSTATUS_EL1, {AArch64::FeatureRAS}},
826 {"erxaddr_el1", ERXADDR_EL1, {AArch64::FeatureRAS}},
827 {"erxmisc0_el1", ERXMISC0_EL1, {AArch64::FeatureRAS}},
828 {"erxmisc1_el1", ERXMISC1_EL1, {AArch64::FeatureRAS}},
829 {"disr_el1", DISR_EL1, {AArch64::FeatureRAS}},
830 {"vdisr_el2", VDISR_EL2, {AArch64::FeatureRAS}},
831 {"vsesr_el2", VSESR_EL2, {AArch64::FeatureRAS}},
832
833 // v8.2a "Statistical Profiling extension" registers
834 {"pmblimitr_el1", PMBLIMITR_EL1, {AArch64::FeatureSPE}},
835 {"pmbptr_el1", PMBPTR_EL1, {AArch64::FeatureSPE}},
836 {"pmbsr_el1", PMBSR_EL1, {AArch64::FeatureSPE}},
837 {"pmbidr_el1", PMBIDR_EL1, {AArch64::FeatureSPE}},
838 {"pmscr_el2", PMSCR_EL2, {AArch64::FeatureSPE}},
839 {"pmscr_el12", PMSCR_EL12, {AArch64::FeatureSPE}},
840 {"pmscr_el1", PMSCR_EL1, {AArch64::FeatureSPE}},
841 {"pmsicr_el1", PMSICR_EL1, {AArch64::FeatureSPE}},
842 {"pmsirr_el1", PMSIRR_EL1, {AArch64::FeatureSPE}},
843 {"pmsfcr_el1", PMSFCR_EL1, {AArch64::FeatureSPE}},
844 {"pmsevfr_el1", PMSEVFR_EL1, {AArch64::FeatureSPE}},
845 {"pmslatfr_el1", PMSLATFR_EL1, {AArch64::FeatureSPE}},
846 {"pmsidr_el1", PMSIDR_EL1, {AArch64::FeatureSPE}},
847 };
848
849 uint32_t
850 AArch64SysReg::SysRegMapper::fromString(StringRef Name,
851 const FeatureBitset& FeatureBits, bool &Valid) const {
852 std::string NameLower = Name.lower();
853
854 // First search the registers shared by all
855 for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) {
856 if (SysRegMappings[i].isNameEqual(NameLower, FeatureBits)) {
857 Valid = true;
858 return SysRegMappings[i].Value;
859 }
860 }
861
862 // Now try the instruction-specific registers (either read-only or
863 // write-only).
864 for (unsigned i = 0; i < NumInstMappings; ++i) {
865 if (InstMappings[i].isNameEqual(NameLower, FeatureBits)) {
866 Valid = true;
867 return InstMappings[i].Value;
868 }
869 }
870
83 uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) {
87184 // Try to parse an S____ register name
872 Regex GenericRegPattern("^s([0-3])_([0-7])_c([0-9]|1[0-5])_c([0-9]|1[0-5])_([0-7])$");
85 Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$");
87386
87487 SmallVector Ops;
875 if (!GenericRegPattern.match(NameLower, &Ops)) {
876 Valid = false;
88 if (!GenericRegPattern.match(Name.upper(), &Ops))
87789 return -1;
878 }
87990
88091 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
88192 uint32_t Bits;
88697 Ops[5].getAsInteger(10, Op2);
88798 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
88899
889 Valid = true;
890100 return Bits;
891101 }
892102
893 std::string
894 AArch64SysReg::SysRegMapper::toString(uint32_t Bits,
895 const FeatureBitset& FeatureBits) const {
896 // First search the registers shared by all
897 for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) {
898 if (SysRegMappings[i].isValueEqual(Bits, FeatureBits)) {
899 return SysRegMappings[i].Name;
900 }
901 }
902
903 // Now try the instruction-specific registers (either read-only or
904 // write-only).
905 for (unsigned i = 0; i < NumInstMappings; ++i) {
906 if (InstMappings[i].isValueEqual(Bits, FeatureBits)) {
907 return InstMappings[i].Name;
908 }
909 }
910
103 std::string AArch64SysReg::genericRegisterString(uint32_t Bits) {
911104 assert(Bits < 0x10000);
912105 uint32_t Op0 = (Bits >> 14) & 0x3;
913106 uint32_t Op1 = (Bits >> 11) & 0x7;
915108 uint32_t CRm = (Bits >> 3) & 0xf;
916109 uint32_t Op2 = Bits & 0x7;
917110
918 return "s" + utostr(Op0)+ "_" + utostr(Op1) + "_c" + utostr(CRn)
919 + "_c" + utostr(CRm) + "_" + utostr(Op2);
111 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
112 utostr(CRm) + "_" + utostr(Op2);
920113 }
921114
922 const AArch64NamedImmMapper::Mapping AArch64TLBI::TLBIMapper::TLBIMappings[] = {
923 {"ipas2e1is", IPAS2E1IS, {}},
924 {"ipas2le1is", IPAS2LE1IS, {}},
925 {"vmalle1is", VMALLE1IS, {}},
926 {"alle2is", ALLE2IS, {}},
927 {"alle3is", ALLE3IS, {}},
928 {"vae1is", VAE1IS, {}},
929 {"vae2is", VAE2IS, {}},
930 {"vae3is", VAE3IS, {}},
931 {"aside1is", ASIDE1IS, {}},
932 {"vaae1is", VAAE1IS, {}},
933 {"alle1is", ALLE1IS, {}},
934 {"vale1is", VALE1IS, {}},
935 {"vale2is", VALE2IS, {}},
936 {"vale3is", VALE3IS, {}},
937 {"vmalls12e1is", VMALLS12E1IS, {}},
938 {"vaale1is", VAALE1IS, {}},
939 {"ipas2e1", IPAS2E1, {}},
940 {"ipas2le1", IPAS2LE1, {}},
941 {"vmalle1", VMALLE1, {}},
942 {"alle2", ALLE2, {}},
943 {"alle3", ALLE3, {}},
944 {"vae1", VAE1, {}},
945 {"vae2", VAE2, {}},
946 {"vae3", VAE3, {}},
947 {"aside1", ASIDE1, {}},
948 {"vaae1", VAAE1, {}},
949 {"alle1", ALLE1, {}},
950 {"vale1", VALE1, {}},
951 {"vale2", VALE2, {}},
952 {"vale3", VALE3, {}},
953 {"vmalls12e1", VMALLS12E1, {}},
954 {"vaale1", VAALE1, {}}
955 };
956
957 AArch64TLBI::TLBIMapper::TLBIMapper()
958 : AArch64NamedImmMapper(TLBIMappings, 0) {}
115 namespace llvm {
116 namespace AArch64TLBI {
117 #define GET_TLBI_IMPL
118 #include "AArch64GenSystemOperands.inc"
119 }
120 }
265265 }
266266 } // end namespace AArch64CC
267267
268 /// Instances of this class can perform bidirectional mapping from random
269 /// identifier strings to operand encodings. For example "MSR" takes a named
270 /// system-register which must be encoded somehow and decoded for printing. This
271 /// central location means that the information for those transformations is not
272 /// duplicated and remains in sync.
273 ///
274 /// FIXME: currently the algorithm is a completely unoptimised linear
275 /// search. Obviously this could be improved, but we would probably want to work
276 /// out just how often these instructions are emitted before working on it. It
277 /// might even be optimal to just reorder the tables for the common instructions
278 /// rather than changing the algorithm.
279 struct AArch64NamedImmMapper {
280 struct Mapping {
281 const char *Name;
282 uint32_t Value;
283 // Set of features this mapping is available for
284 // Zero value of FeatureBitSet means the mapping is always available
285 FeatureBitset FeatureBitSet;
286
287 bool isNameEqual(const std::string &Other,
288 const FeatureBitset &FeatureBits) const {
289 if (FeatureBitSet.any() &&
290 (FeatureBitSet & FeatureBits).none())
291 return false;
292 return Name == Other;
268 namespace AArch64AT{
269 struct AT {
270 const char *Name;
271 uint16_t Encoding;
272 };
273
274 #define GET_AT_DECL
275 #include "AArch64GenSystemOperands.inc"
276
277 }
278 namespace AArch64DB {
279 struct DB {
280 const char *Name;
281 uint16_t Encoding;
282 };
283
284 #define GET_DB_DECL
285 #include "AArch64GenSystemOperands.inc"
286 }
287
288 namespace AArch64DC {
289 struct DC {
290 const char *Name;
291 uint16_t Encoding;
292 };
293
294 #define GET_DC_DECL
295 #include "AArch64GenSystemOperands.inc"
296 }
297
298 namespace AArch64IC {
299 struct IC {
300 const char *Name;
301 uint16_t Encoding;
302 bool NeedsReg;
303 };
304 #define GET_IC_DECL
305 #include "AArch64GenSystemOperands.inc"
306 }
307
308 namespace AArch64ISB {
309 struct ISB {
310 const char *Name;
311 uint16_t Encoding;
312 };
313 #define GET_ISB_DECL
314 #include "AArch64GenSystemOperands.inc"
315 }
316
317 namespace AArch64PRFM {
318 struct PRFM {
319 const char *Name;
320 uint16_t Encoding;
321 };
322 #define GET_PRFM_DECL
323 #include "AArch64GenSystemOperands.inc"
324 }
325
326 namespace AArch64PState {
327 struct PState {
328 const char *Name;
329 uint16_t Encoding;
330 FeatureBitset FeaturesRequired;
331
332 bool haveFeatures(FeatureBitset ActiveFeatures) const {
333 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
293334 }
294
295 bool isValueEqual(uint32_t Other,
296 const FeatureBitset& FeatureBits) const {
297 if (FeatureBitSet.any() &&
298 (FeatureBitSet & FeatureBits).none())
299 return false;
300 return Value == Other;
301 }
302 };
303
304 template
305 AArch64NamedImmMapper(const Mapping (&Mappings)[N], uint32_t TooBigImm)
306 : Mappings(&Mappings[0]), NumMappings(N), TooBigImm(TooBigImm) {}
307
308 // Maps value to string, depending on availability for FeatureBits given
309 StringRef toString(uint32_t Value, const FeatureBitset& FeatureBits,
310 bool &Valid) const;
311 // Maps string to value, depending on availability for FeatureBits given
312 uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits,
313 bool &Valid) const;
314
315 /// Many of the instructions allow an alternative assembly form consisting of
316 /// a simple immediate. Currently the only valid forms are ranges [0, N) where
317 /// N being 0 indicates no immediate syntax-form is allowed.
318 bool validImm(uint32_t Value) const;
319 protected:
320 const Mapping *Mappings;
321 size_t NumMappings;
322 uint32_t TooBigImm;
323 };
324
325 namespace AArch64AT {
326 enum ATValues {
327 Invalid = -1, // Op0 Op1 CRn CRm Op2
328 S1E1R = 0x43c0, // 01 000 0111 1000 000
329 S1E2R = 0x63c0, // 01 100 0111 1000 000
330 S1E3R = 0x73c0, // 01 110 0111 1000 000
331 S1E1W = 0x43c1, // 01 000 0111 1000 001
332 S1E2W = 0x63c1, // 01 100 0111 1000 001
333 S1E3W = 0x73c1, // 01 110 0111 1000 001
334 S1E0R = 0x43c2, // 01 000 0111 1000 010
335 S1E0W = 0x43c3, // 01 000 0111 1000 011
336 S12E1R = 0x63c4, // 01 100 0111 1000 100
337 S12E1W = 0x63c5, // 01 100 0111 1000 101
338 S12E0R = 0x63c6, // 01 100 0111 1000 110
339 S12E0W = 0x63c7, // 01 100 0111 1000 111
340 S1E1RP = 0x43c8, // 01 000 0111 1001 000
341 S1E1WP = 0x43c9 // 01 000 0111 1001 001
342 };
343
344 struct ATMapper : AArch64NamedImmMapper {
345 const static Mapping ATMappings[];
346
347 ATMapper();
348 };
349
350 }
351 namespace AArch64DB {
352 enum DBValues {
353 Invalid = -1,
354 OSHLD = 0x1,
355 OSHST = 0x2,
356 OSH = 0x3,
357 NSHLD = 0x5,
358 NSHST = 0x6,
359 NSH = 0x7,
360 ISHLD = 0x9,
361 ISHST = 0xa,
362 ISH = 0xb,
363 LD = 0xd,
364 ST = 0xe,
365 SY = 0xf
366 };
367
368 struct DBarrierMapper : AArch64NamedImmMapper {
369 const static Mapping DBarrierMappings[];
370
371 DBarrierMapper();
372 };
373 }
374
375 namespace AArch64DC {
376 enum DCValues {
377 Invalid = -1, // Op1 CRn CRm Op2
378 ZVA = 0x5ba1, // 01 011 0111 0100 001
379 IVAC = 0x43b1, // 01 000 0111 0110 001
380 ISW = 0x43b2, // 01 000 0111 0110 010
381 CVAC = 0x5bd1, // 01 011 0111 1010 001
382 CSW = 0x43d2, // 01 000 0111 1010 010
383 CVAU = 0x5bd9, // 01 011 0111 1011 001
384 CIVAC = 0x5bf1, // 01 011 0111 1110 001
385 CISW = 0x43f2 // 01 000 0111 1110 010
386 };
387
388 struct DCMapper : AArch64NamedImmMapper {
389 const static Mapping DCMappings[];
390
391 DCMapper();
392 };
393
394 }
395
396 namespace AArch64IC {
397 enum ICValues {
398 Invalid = -1, // Op1 CRn CRm Op2
399 IALLUIS = 0x0388, // 000 0111 0001 000
400 IALLU = 0x03a8, // 000 0111 0101 000
401 IVAU = 0x1ba9 // 011 0111 0101 001
402 };
403
404
405 struct ICMapper : AArch64NamedImmMapper {
406 const static Mapping ICMappings[];
407
408 ICMapper();
409 };
410
411 static inline bool NeedsRegister(ICValues Val) {
412 return Val == IVAU;
413 }
414 }
415
416 namespace AArch64ISB {
417 enum ISBValues {
418 Invalid = -1,
419 SY = 0xf
420 };
421 struct ISBMapper : AArch64NamedImmMapper {
422 const static Mapping ISBMappings[];
423
424 ISBMapper();
425 };
426 }
427
428 namespace AArch64PRFM {
429 enum PRFMValues {
430 Invalid = -1,
431 PLDL1KEEP = 0x00,
432 PLDL1STRM = 0x01,
433 PLDL2KEEP = 0x02,
434 PLDL2STRM = 0x03,
435 PLDL3KEEP = 0x04,
436 PLDL3STRM = 0x05,
437 PLIL1KEEP = 0x08,
438 PLIL1STRM = 0x09,
439 PLIL2KEEP = 0x0a,
440 PLIL2STRM = 0x0b,
441 PLIL3KEEP = 0x0c,
442 PLIL3STRM = 0x0d,
443 PSTL1KEEP = 0x10,
444 PSTL1STRM = 0x11,
445 PSTL2KEEP = 0x12,
446 PSTL2STRM = 0x13,
447 PSTL3KEEP = 0x14,
448 PSTL3STRM = 0x15
449 };
450
451 struct PRFMMapper : AArch64NamedImmMapper {
452 const static Mapping PRFMMappings[];
453
454 PRFMMapper();
455 };
456 }
457
458 namespace AArch64PState {
459 enum PStateValues {
460 Invalid = -1,
461 SPSel = 0x05,
462 DAIFSet = 0x1e,
463 DAIFClr = 0x1f,
464
465 // v8.1a "Privileged Access Never" extension-specific PStates
466 PAN = 0x04,
467
468 // v8.2a "User Access Override" extension-specific PStates
469 UAO = 0x03
470 };
471
472 struct PStateMapper : AArch64NamedImmMapper {
473 const static Mapping PStateMappings[];
474
475 PStateMapper();
476 };
477
335 };
336 #define GET_PSTATE_DECL
337 #include "AArch64GenSystemOperands.inc"
478338 }
479339
480340 namespace AArch64PSBHint {
481 enum PSBHintValues {
482 Invalid = -1,
483 // v8.2a "Statistical Profiling" extension-specific PSB operands
484 CSync = 0x11, // psb csync = hint #0x11
485 };
486
487 struct PSBHintMapper : AArch64NamedImmMapper {
488 const static Mapping PSBHintMappings[];
489
490 PSBHintMapper();
491 };
492
341 struct PSB {
342 const char *Name;
343 uint16_t Encoding;
344 };
345 #define GET_PSB_DECL
346 #include "AArch64GenSystemOperands.inc"
493347 }
494348
495349 namespace AArch64SE {
573427 }
574428
575429 namespace AArch64SysReg {
576 enum SysRegROValues {
577 MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
578 DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
579 MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
580 OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
581 DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
582 PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
583 PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
584 MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
585 CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
586 CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
587 CTR_EL0 = 0xd801, // 11 011 0000 0000 001
588 MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
589 REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
590 AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
591 DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
592 ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
593 ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
594 ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
595 ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
596 ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
597 ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
598 ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
599 ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
600 ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
601 ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
602 ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
603 ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
604 ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
605 ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
606 ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
607 ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
608 ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
609 ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
610 ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
611 ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
612 ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
613 ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
614 ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
615 ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
616 ID_A64MMFR2_EL1 = 0xc03a, // 11 000 0000 0111 010
617 MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
618 MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
619 MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
620 RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
621 RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
622 RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
623 ISR_EL1 = 0xc608, // 11 000 1100 0001 000
624 CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
625 CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
626 ID_MMFR4_EL1 = 0xc016, // 11 000 0000 0010 110
627
628 // Trace registers
629 TRCSTATR = 0x8818, // 10 001 0000 0011 000
630 TRCIDR8 = 0x8806, // 10 001 0000 0000 110
631 TRCIDR9 = 0x880e, // 10 001 0000 0001 110
632 TRCIDR10 = 0x8816, // 10 001 0000 0010 110
633 TRCIDR11 = 0x881e, // 10 001 0000 0011 110
634 TRCIDR12 = 0x8826, // 10 001 0000 0100 110
635 TRCIDR13 = 0x882e, // 10 001 0000 0101 110
636 TRCIDR0 = 0x8847, // 10 001 0000 1000 111
637 TRCIDR1 = 0x884f, // 10 001 0000 1001 111
638 TRCIDR2 = 0x8857, // 10 001 0000 1010 111
639 TRCIDR3 = 0x885f, // 10 001 0000 1011 111
640 TRCIDR4 = 0x8867, // 10 001 0000 1100 111
641 TRCIDR5 = 0x886f, // 10 001 0000 1101 111
642 TRCIDR6 = 0x8877, // 10 001 0000 1110 111
643 TRCIDR7 = 0x887f, // 10 001 0000 1111 111
644 TRCOSLSR = 0x888c, // 10 001 0001 0001 100
645 TRCPDSR = 0x88ac, // 10 001 0001 0101 100
646 TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
647 TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
648 TRCLSR = 0x8bee, // 10 001 0111 1101 110
649 TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
650 TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
651 TRCDEVID = 0x8b97, // 10 001 0111 0010 111
652 TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
653 TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
654 TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
655 TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
656 TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
657 TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
658 TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
659 TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
660 TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
661 TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
662 TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
663 TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
664 TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
665
666 // GICv3 registers
667 ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
668 ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
669 ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
670 ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
671 ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
672 ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
673 ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
674 ICH_ELSR_EL2 = 0xe65d, // 11 100 1100 1011 101
675
676 // RAS extension registers
677 ERRIDR_EL1 = 0xc298, // 11 000 0101 0011 000
678 ERXFR_EL1 = 0xc2a0 // 11 000 0101 0100 000
679 };
680
681 enum SysRegWOValues {
682 DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
683 OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
684 PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
685
686 // Trace Registers
687 TRCOSLAR = 0x8884, // 10 001 0001 0000 100
688 TRCLAR = 0x8be6, // 10 001 0111 1100 110
689
690 // GICv3 registers
691 ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
692 ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
693 ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
694 ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
695 ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
696 ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111
697 };
698
699 enum SysRegValues {
700 Invalid = -1, // Op0 Op1 CRn CRm Op2
701 OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010
702 OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010
703 TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000
704 MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000
705 MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010
706 DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000
707 OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010
708 DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000
709 DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100
710 DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100
711 DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100
712 DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100
713 DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100
714 DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100
715 DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100
716 DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100
717 DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100
718 DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100
719 DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100
720 DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100
721 DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100
722 DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100
723 DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100
724 DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100
725 DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101
726 DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101
727 DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101
728 DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101
729 DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101
730 DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101
731 DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101
732 DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101
733 DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101
734 DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101
735 DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101
736 DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101
737 DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101
738 DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101
739 DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101
740 DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101
741 DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110
742 DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110
743 DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110
744 DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110
745 DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110
746 DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110
747 DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110
748 DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110
749 DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110
750 DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110
751 DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110
752 DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110
753 DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110
754 DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110
755 DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110
756 DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110
757 DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111
758 DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111
759 DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111
760 DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111
761 DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111
762 DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111
763 DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111
764 DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111
765 DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111
766 DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111
767 DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111
768 DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111
769 DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111
770 DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111
771 DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111
772 DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111
773 TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000
774 OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100
775 DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100
776 DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110
777 DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110
778 CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000
779 VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000
780 VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101
781 CPACR_EL1 = 0xc082, // 11 000 0001 0000 010
782 SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000
783 SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000
784 SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000
785 ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001
786 ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001
787 ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001
788 HCR_EL2 = 0xe088, // 11 100 0001 0001 000
789 SCR_EL3 = 0xf088, // 11 110 0001 0001 000
790 MDCR_EL2 = 0xe089, // 11 100 0001 0001 001
791 SDER32_EL3 = 0xf089, // 11 110 0001 0001 001
792 CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010
793 CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010
794 HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011
795 HACR_EL2 = 0xe08f, // 11 100 0001 0001 111
796 MDCR_EL3 = 0xf099, // 11 110 0001 0011 001
797 TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000
798 TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000
799 TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000
800 TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001
801 TCR_EL1 = 0xc102, // 11 000 0010 0000 010
802 TCR_EL2 = 0xe102, // 11 100 0010 0000 010
803 TCR_EL3 = 0xf102, // 11 110 0010 0000 010
804 VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000
805 VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010
806 DACR32_EL2 = 0xe180, // 11 100 0011 0000 000
807 SPSR_EL1 = 0xc200, // 11 000 0100 0000 000
808 SPSR_EL2 = 0xe200, // 11 100 0100 0000 000
809 SPSR_EL3 = 0xf200, // 11 110 0100 0000 000
810 ELR_EL1 = 0xc201, // 11 000 0100 0000 001
811 ELR_EL2 = 0xe201, // 11 100 0100 0000 001
812 ELR_EL3 = 0xf201, // 11 110 0100 0000 001
813 SP_EL0 = 0xc208, // 11 000 0100 0001 000
814 SP_EL1 = 0xe208, // 11 100 0100 0001 000
815 SP_EL2 = 0xf208, // 11 110 0100 0001 000
816 SPSel = 0xc210, // 11 000 0100 0010 000
817 NZCV = 0xda10, // 11 011 0100 0010 000
818 DAIF = 0xda11, // 11 011 0100 0010 001
819 CurrentEL = 0xc212, // 11 000 0100 0010 010
820 SPSR_irq = 0xe218, // 11 100 0100 0011 000
821 SPSR_abt = 0xe219, // 11 100 0100 0011 001
822 SPSR_und = 0xe21a, // 11 100 0100 0011 010
823 SPSR_fiq = 0xe21b, // 11 100 0100 0011 011
824 FPCR = 0xda20, // 11 011 0100 0100 000
825 FPSR = 0xda21, // 11 011 0100 0100 001
826 DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000
827 DLR_EL0 = 0xda29, // 11 011 0100 0101 001
828 IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001
829 AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000
830 AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000
831 AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000
832 AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001
833 AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001
834 AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001
835 ESR_EL1 = 0xc290, // 11 000 0101 0010 000
836 ESR_EL2 = 0xe290, // 11 100 0101 0010 000
837 ESR_EL3 = 0xf290, // 11 110 0101 0010 000
838 FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000
839 FAR_EL1 = 0xc300, // 11 000 0110 0000 000
840 FAR_EL2 = 0xe300, // 11 100 0110 0000 000
841 FAR_EL3 = 0xf300, // 11 110 0110 0000 000
842 HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100
843 PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000
844 PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000
845 PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001
846 PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010
847 PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011
848 PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101
849 PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000
850 PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001
851 PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010
852 PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000
853 PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001
854 PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010
855 PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011
856 MAIR_EL1 = 0xc510, // 11 000 1010 0010 000
857 MAIR_EL2 = 0xe510, // 11 100 1010 0010 000
858 MAIR_EL3 = 0xf510, // 11 110 1010 0010 000
859 AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000
860 AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000
861 AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000
862 VBAR_EL1 = 0xc600, // 11 000 1100 0000 000
863 VBAR_EL2 = 0xe600, // 11 100 1100 0000 000
864 VBAR_EL3 = 0xf600, // 11 110 1100 0000 000
865 RMR_EL1 = 0xc602, // 11 000 1100 0000 010
866 RMR_EL2 = 0xe602, // 11 100 1100 0000 010
867 RMR_EL3 = 0xf602, // 11 110 1100 0000 010
868 CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001
869 TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010
870 TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010
871 TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010
872 TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011
873 TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100
874 CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000
875 CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011
876 CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000
877 CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000
878 CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000
879 CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000
880 CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000
881 CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001
882 CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001
883 CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001
884 CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010
885 CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010
886 CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010
887 CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000
888 CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001
889 CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010
890 PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000
891 PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001
892 PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010
893 PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011
894 PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100
895 PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101
896 PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110
897 PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111
898 PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000
899 PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001
900 PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010
901 PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011
902 PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100
903 PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101
904 PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110
905 PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111
906 PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000
907 PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001
908 PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010
909 PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011
910 PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100
911 PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101
912 PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110
913 PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111
914 PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000
915 PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001
916 PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010
917 PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011
918 PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100
919 PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101
920 PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110
921 PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111
922 PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000
923 PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001
924 PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010
925 PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011
926 PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100
927 PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101
928 PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110
929 PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111
930 PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000
931 PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001
932 PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010
933 PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011
934 PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100
935 PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101
936 PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110
937 PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111
938 PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000
939 PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001
940 PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010
941 PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011
942 PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100
943 PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101
944 PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110
945 PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111
946 PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000
947 PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001
948 PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010
949 PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011
950 PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100
951 PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101
952 PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110
953
954 // Trace registers
955 TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000
956 TRCPROCSELR = 0x8810, // 10 001 0000 0010 000
957 TRCCONFIGR = 0x8820, // 10 001 0000 0100 000
958 TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000
959 TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000
960 TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000
961 TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000
962 TRCTSCTLR = 0x8860, // 10 001 0000 1100 000
963 TRCSYNCPR = 0x8868, // 10 001 0000 1101 000
964 TRCCCCTLR = 0x8870, // 10 001 0000 1110 000
965 TRCBBCTLR = 0x8878, // 10 001 0000 1111 000
966 TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001
967 TRCQCTLR = 0x8809, // 10 001 0000 0001 001
968 TRCVICTLR = 0x8802, // 10 001 0000 0000 010
969 TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010
970 TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010
971 TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010
972 TRCVDCTLR = 0x8842, // 10 001 0000 1000 010
973 TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010
974 TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010
975 TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100
976 TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100
977 TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100
978 TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100
979 TRCSEQSTR = 0x883c, // 10 001 0000 0111 100
980 TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100
981 TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101
982 TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101
983 TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101
984 TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101
985 TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101
986 TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101
987 TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101
988 TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101
989 TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101
990 TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101
991 TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101
992 TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101
993 TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111
994 TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111
995 TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111
996 TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111
997 TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111
998 TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111
999 TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111
1000 TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111
1001 TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000
1002 TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000
1003 TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000
1004 TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000
1005 TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000
1006 TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000
1007 TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000
1008 TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000
1009 TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000
1010 TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000
1011 TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000
1012 TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000
1013 TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000
1014 TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000
1015 TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001
1016 TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001
1017 TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001
1018 TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001
1019 TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001
1020 TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001
1021 TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001
1022 TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001
1023 TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001
1024 TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001
1025 TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001
1026 TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001
1027 TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001
1028 TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001
1029 TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001
1030 TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001
1031 TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010
1032 TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010
1033 TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010
1034 TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010
1035 TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010
1036 TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010
1037 TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010
1038 TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010
1039 TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010
1040 TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010
1041 TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010
1042 TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010
1043 TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010
1044 TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010
1045 TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010
1046 TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010
1047 TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011
1048 TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011
1049 TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011
1050 TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011
1051 TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011
1052 TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011
1053 TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011
1054 TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011
1055 TRCPDCR = 0x88a4, // 10 001 0001 0100 100
1056 TRCACVR0 = 0x8900, // 10 001 0010 0000 000
1057 TRCACVR1 = 0x8910, // 10 001 0010 0010 000
1058 TRCACVR2 = 0x8920, // 10 001 0010 0100 000
1059 TRCACVR3 = 0x8930, // 10 001 0010 0110 000
1060 TRCACVR4 = 0x8940, // 10 001 0010 1000 000
1061 TRCACVR5 = 0x8950, // 10 001 0010 1010 000
1062 TRCACVR6 = 0x8960, // 10 001 0010 1100 000
1063 TRCACVR7 = 0x8970, // 10 001 0010 1110 000
1064 TRCACVR8 = 0x8901, // 10 001 0010 0000 001
1065 TRCACVR9 = 0x8911, // 10 001 0010 0010 001
1066 TRCACVR10 = 0x8921, // 10 001 0010 0100 001
1067 TRCACVR11 = 0x8931, // 10 001 0010 0110 001
1068 TRCACVR12 = 0x8941, // 10 001 0010 1000 001
1069 TRCACVR13 = 0x8951, // 10 001 0010 1010 001
1070 TRCACVR14 = 0x8961, // 10 001 0010 1100 001
1071 TRCACVR15 = 0x8971, // 10 001 0010 1110 001
1072 TRCACATR0 = 0x8902, // 10 001 0010 0000 010
1073 TRCACATR1 = 0x8912, // 10 001 0010 0010 010
1074 TRCACATR2 = 0x8922, // 10 001 0010 0100 010
1075 TRCACATR3 = 0x8932, // 10 001 0010 0110 010
1076 TRCACATR4 = 0x8942, // 10 001 0010 1000 010
1077 TRCACATR5 = 0x8952, // 10 001 0010 1010 010
1078 TRCACATR6 = 0x8962, // 10 001 0010 1100 010
1079 TRCACATR7 = 0x8972, // 10 001 0010 1110 010
1080 TRCACATR8 = 0x8903, // 10 001 0010 0000 011
1081 TRCACATR9 = 0x8913, // 10 001 0010 0010 011
1082 TRCACATR10 = 0x8923, // 10 001 0010 0100 011
1083 TRCACATR11 = 0x8933, // 10 001 0010 0110 011
1084 TRCACATR12 = 0x8943, // 10 001 0010 1000 011
1085 TRCACATR13 = 0x8953, // 10 001 0010 1010 011
1086 TRCACATR14 = 0x8963, // 10 001 0010 1100 011
1087 TRCACATR15 = 0x8973, // 10 001 0010 1110 011
1088 TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100
1089 TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100
1090 TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100
1091 TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100
1092 TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101
1093 TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101
1094 TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101
1095 TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101
1096 TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110
1097 TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110
1098 TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110
1099 TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110
1100 TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111
1101 TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111
1102 TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111
1103 TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111
1104 TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000
1105 TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000
1106 TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000
1107 TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000
1108 TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000
1109 TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000
1110 TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000
1111 TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000
1112 TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001
1113 TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001
1114 TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001
1115 TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001
1116 TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001
1117 TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001
1118 TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001
1119 TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001
1120 TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010
1121 TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010
1122 TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010
1123 TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010
1124 TRCITCTRL = 0x8b84, // 10 001 0111 0000 100
1125 TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110
1126 TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110
1127
1128 // GICv3 registers
1129 ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011
1130 ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011
1131 ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000
1132 ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100
1133 ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100
1134 ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101
1135 ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101
1136 ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101
1137 ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110
1138 ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111
1139 ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111
1140 ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000
1141 ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100
1142 ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101
1143 ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110
1144 ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111
1145 ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000
1146 ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001
1147 ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010
1148 ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011
1149 ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000
1150 ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001
1151 ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010
1152 ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011
1153 ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000
1154 ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001
1155 ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010
1156 ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011
1157 ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000
1158 ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010
1159 ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111
1160 ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100
1161 ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000
1162 ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001
1163 ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010
1164 ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011
1165 ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100
1166 ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101
1167 ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110
1168 ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111
1169 ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000
1170 ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001
1171 ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010
1172 ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011
1173 ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100
1174 ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101
1175 ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110
1176 ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111
1177
1178 // v8.1a "Privileged Access Never" extension-specific system registers
1179 PAN = 0xc213, // 11 000 0100 0010 011
1180
1181 // v8.1a "Limited Ordering Regions" extension-specific system registers
1182 LORSA_EL1 = 0xc520, // 11 000 1010 0100 000
1183 LOREA_EL1 = 0xc521, // 11 000 1010 0100 001
1184 LORN_EL1 = 0xc522, // 11 000 1010 0100 010
1185 LORC_EL1 = 0xc523, // 11 000 1010 0100 011
1186 LORID_EL1 = 0xc527, // 11 000 1010 0100 111
1187
1188 // v8.1a "Virtualization host extensions" system registers
1189 TTBR1_EL2 = 0xe101, // 11 100 0010 0000 001
1190 CONTEXTIDR_EL2 = 0xe681, // 11 100 1101 0000 001
1191 CNTHV_TVAL_EL2 = 0xe718, // 11 100 1110 0011 000
1192 CNTHV_CVAL_EL2 = 0xe71a, // 11 100 1110 0011 010
1193 CNTHV_CTL_EL2 = 0xe719, // 11 100 1110 0011 001
1194 SCTLR_EL12 = 0xe880, // 11 101 0001 0000 000
1195 CPACR_EL12 = 0xe882, // 11 101 0001 0000 010
1196 TTBR0_EL12 = 0xe900, // 11 101 0010 0000 000
1197 TTBR1_EL12 = 0xe901, // 11 101 0010 0000 001
1198 TCR_EL12 = 0xe902, // 11 101 0010 0000 010
1199 AFSR0_EL12 = 0xea88, // 11 101 0101 0001 000
1200 AFSR1_EL12 = 0xea89, // 11 101 0101 0001 001
1201 ESR_EL12 = 0xea90, // 11 101 0101 0010 000
1202 FAR_EL12 = 0xeb00, // 11 101 0110 0000 000
1203 MAIR_EL12 = 0xed10, // 11 101 1010 0010 000
1204 AMAIR_EL12 = 0xed18, // 11 101 1010 0011 000
1205 VBAR_EL12 = 0xee00, // 11 101 1100 0000 000
1206 CONTEXTIDR_EL12 = 0xee81, // 11 101 1101 0000 001
1207 CNTKCTL_EL12 = 0xef08, // 11 101 1110 0001 000
1208 CNTP_TVAL_EL02 = 0xef10, // 11 101 1110 0010 000
1209 CNTP_CTL_EL02 = 0xef11, // 11 101 1110 0010 001
1210 CNTP_CVAL_EL02 = 0xef12, // 11 101 1110 0010 010
1211 CNTV_TVAL_EL02 = 0xef18, // 11 101 1110 0011 000
1212 CNTV_CTL_EL02 = 0xef19, // 11 101 1110 0011 001
1213 CNTV_CVAL_EL02 = 0xef1a, // 11 101 1110 0011 010
1214 SPSR_EL12 = 0xea00, // 11 101 0100 0000 000
1215 ELR_EL12 = 0xea01, // 11 101 0100 0000 001
1216
1217 // RAS extension registers
1218 ERRSELR_EL1 = 0xc299, // 11 000 0101 0011 001
1219 ERXCTLR_EL1 = 0xc2a1, // 11 000 0101 0100 001
1220 ERXSTATUS_EL1 = 0xc2a2, // 11 000 0101 0100 010
1221 ERXADDR_EL1 = 0xc2a3, // 11 000 0101 0100 011
1222 ERXMISC0_EL1 = 0xc2a8, // 11 000 0101 0101 000
1223 ERXMISC1_EL1 = 0xc2a9, // 11 000 0101 0101 001
1224 DISR_EL1 = 0xc609, // 11 000 1100 0001 001
1225 VDISR_EL2 = 0xe609, // 11 100 1100 0001 001
1226 VSESR_EL2 = 0xe293, // 11 100 0101 0010 011
1227
1228 // v8.2a registers
1229 UAO = 0xc214, // 11 000 0100 0010 100
1230
1231 // v8.2a "Statistical Profiling extension" registers
1232 PMBLIMITR_EL1 = 0xc4d0, // 11 000 1001 1010 000
1233 PMBPTR_EL1 = 0xc4d1, // 11 000 1001 1010 001
1234 PMBSR_EL1 = 0xc4d3, // 11 000 1001 1010 011
1235 PMBIDR_EL1 = 0xc4d7, // 11 000 1001 1010 111
1236 PMSCR_EL2 = 0xe4c8, // 11 100 1001 1001 000
1237 PMSCR_EL12 = 0xecc8, // 11 101 1001 1001 000
1238 PMSCR_EL1 = 0xc4c8, // 11 000 1001 1001 000
1239 PMSICR_EL1 = 0xc4ca, // 11 000 1001 1001 010
1240 PMSIRR_EL1 = 0xc4cb, // 11 000 1001 1001 011
1241 PMSFCR_EL1 = 0xc4cc, // 11 000 1001 1001 100
1242 PMSEVFR_EL1 = 0xc4cd, // 11 000 1001 1001 101
1243 PMSLATFR_EL1 = 0xc4ce, // 11 000 1001 1001 110
1244 PMSIDR_EL1 = 0xc4cf, // 11 000 1001 1001 111
1245
1246 // Cyclone specific system registers
1247 CPM_IOACC_CTL_EL3 = 0xff90,
1248 };
1249
1250