llvm.org GIT mirror llvm / 696bbc5
Fix gcc -Wsign-compare warning in X86DisassemblerTables.cpp. X86_MAX_OPERANDS is changed to unsigned. Also, add range-based for loops for affected loops. This in turn needed an ArrayRef instead of a pointer-to-array in InternalInstruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207413 91177308-0d34-0410-b5e6-96231b3b80d8 Patrik Hagglund 6 years ago
4 changed file(s) with 15 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
786786 mcInst.setOpcode(X86::XACQUIRE_PREFIX);
787787 }
788788
789 int index;
790
791789 insn.numImmediatesTranslated = 0;
792790
793 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
794 if (insn.operands[index].encoding != ENCODING_NONE) {
795 if (translateOperand(mcInst, insn.operands[index], insn, Dis)) {
791 for (const auto &Op : insn.operands) {
792 if (Op.encoding != ENCODING_NONE) {
793 if (translateOperand(mcInst, Op, insn, Dis)) {
796794 return true;
797795 }
798796 }
16621662 * @return - 0 if all operands could be read; nonzero otherwise.
16631663 */
16641664 static int readOperands(struct InternalInstruction* insn) {
1665 int index;
16661665 int hasVVVV, needVVVV;
16671666 int sawRegImm = 0;
16681667
16731672 hasVVVV = !readVVVV(insn);
16741673 needVVVV = hasVVVV && (insn->vvvv != 0);
16751674
1676 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
1677 switch (x86OperandSets[insn->spec->operands][index].encoding) {
1675 for (const auto &Op : x86OperandSets[insn->spec->operands]) {
1676 switch (Op.encoding) {
16781677 case ENCODING_NONE:
16791678 case ENCODING_SI:
16801679 case ENCODING_DI:
16831682 case ENCODING_RM:
16841683 if (readModRM(insn))
16851684 return -1;
1686 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1685 if (fixupReg(insn, &Op))
16871686 return -1;
16881687 break;
16891688 case ENCODING_CB:
17051704 }
17061705 if (readImmediate(insn, 1))
17071706 return -1;
1708 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM3 &&
1707 if (Op.type == TYPE_IMM3 &&
17091708 insn->immediates[insn->numImmediatesConsumed - 1] > 7)
17101709 return -1;
1711 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM5 &&
1710 if (Op.type == TYPE_IMM5 &&
17121711 insn->immediates[insn->numImmediatesConsumed - 1] > 31)
17131712 return -1;
1714 if (x86OperandSets[insn->spec->operands][index].type == TYPE_XMM128 ||
1715 x86OperandSets[insn->spec->operands][index].type == TYPE_XMM256)
1713 if (Op.type == TYPE_XMM128 ||
1714 Op.type == TYPE_XMM256)
17161715 sawRegImm = 1;
17171716 break;
17181717 case ENCODING_IW:
17611760 needVVVV = 0; /* Mark that we have found a VVVV operand. */
17621761 if (!hasVVVV)
17631762 return -1;
1764 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1763 if (fixupReg(insn, &Op))
17651764 return -1;
17661765 break;
17671766 case ENCODING_WRITEMASK:
18241823 readOperands(insn))
18251824 return -1;
18261825
1827 insn->operands = &x86OperandSets[insn->spec->operands][0];
1826 insn->operands = x86OperandSets[insn->spec->operands];
18281827
18291828 insn->length = insn->readerCursor - insn->startLocation;
18301829
1616 #define X86DISASSEMBLERDECODER_H
1717
1818 #include "X86DisassemblerDecoderCommon.h"
19 #include "llvm/ADT/ArrayRef.h"
1920
2021 namespace llvm {
2122 namespace X86Disassembler {
619620 uint8_t sibScale;
620621 SIBBase sibBase;
621622
622 const OperandSpecifier *operands;
623 ArrayRef operands;
623624 };
624625
625626 /// \brief Decode one instruction and store the decoding results in
480480 };
481481 #undef ENUM_ENTRY
482482
483 static const int X86_MAX_OPERANDS = 5;
483 static const unsigned X86_MAX_OPERANDS = 5;
484484
485485 /// Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode
486486 /// are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,