llvm.org GIT mirror llvm / 695aa80
[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206356 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 6 years ago
14 changed file(s) with 60 addition(s) and 51 deletion(s). Raw diff Collapse all Expand all
175175 return FMF;
176176 }
177177
178 bool ParseOptionalToken(lltok::Kind T, bool &Present, LocTy *Loc = 0) {
178 bool ParseOptionalToken(lltok::Kind T, bool &Present,
179 LocTy *Loc = nullptr) {
179180 if (Lex.getKind() != T) {
180181 Present = false;
181182 } else {
347348 PerFunctionState &PFS);
348349
349350 // Constant Parsing.
350 bool ParseValID(ValID &ID, PerFunctionState *PFS = NULL);
351 bool ParseValID(ValID &ID, PerFunctionState *PFS = nullptr);
351352 bool ParseGlobalValue(Type *Ty, Constant *&V);
352353 bool ParseGlobalTypeAndValue(Constant *&V);
353354 bool ParseGlobalValueVector(SmallVectorImpl &Elts);
169169 void GetPassthruRegs(MachineInstr *MI, std::set& PassthruRegs);
170170
171171 void HandleLastUse(unsigned Reg, unsigned KillIdx, const char *tag,
172 const char *header =NULL, const char *footer =NULL);
172 const char *header = nullptr,
173 const char *footer = nullptr);
173174
174175 void PrescanInstruction(MachineInstr *MI, unsigned Count,
175176 std::set& PassthruRegs);
7676 /// Iterator pointing into the fixed RegUnit interference.
7777 LiveInterval::iterator FixedI;
7878
79 RegUnitInfo(LiveIntervalUnion &LIU) : VirtTag(LIU.getTag()), Fixed(0) {
79 RegUnitInfo(LiveIntervalUnion &LIU)
80 : VirtTag(LIU.getTag()), Fixed(nullptr) {
8081 VirtI.setMap(LIU.getMap());
8182 }
8283 };
9293 void update(unsigned MBBNum);
9394
9495 public:
95 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {}
96 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(nullptr), LIS(nullptr) {}
9697
9798 void clear(MachineFunction *mf, SlotIndexes *indexes, LiveIntervals *lis) {
9899 assert(!hasRefs() && "Cannot clear cache entry with references");
147148 Entry *get(unsigned PhysReg);
148149
149150 public:
150 InterferenceCache() : TRI(0), LIUArray(0), MF(0), PhysRegEntries(NULL),
151 PhysRegEntriesCount(0), RoundRobin(0) {}
151 InterferenceCache()
152 : TRI(nullptr), LIUArray(nullptr), MF(nullptr), PhysRegEntries(nullptr),
153 PhysRegEntriesCount(0), RoundRobin(0) {}
152154
153155 ~InterferenceCache() {
154156 free(PhysRegEntries);
171173 static BlockInterference NoInterference;
172174
173175 void setEntry(Entry *E) {
174 Current = 0;
176 Current = nullptr;
175177 // Update reference counts. Nothing happens when RefCount reaches 0, so
176178 // we don't have to check for E == CacheEntry etc.
177179 if (CacheEntry)
183185
184186 public:
185187 /// Cursor - Create a dangling cursor.
186 Cursor() : CacheEntry(0), Current(0) {}
187 ~Cursor() { setEntry(0); }
188
189 Cursor(const Cursor &O) : CacheEntry(0), Current(0) {
188 Cursor() : CacheEntry(nullptr), Current(nullptr) {}
189 ~Cursor() { setEntry(nullptr); }
190
191 Cursor(const Cursor &O) : CacheEntry(nullptr), Current(nullptr) {
190192 setEntry(O.CacheEntry);
191193 }
192194
199201 void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) {
200202 // Release reference before getting a new one. That guarantees we can
201203 // actually have CacheEntries live cursors.
202 setEntry(0);
204 setEntry(nullptr);
203205 if (PhysReg)
204206 setEntry(Cache.get(PhysReg));
205207 }
9191 VNInfo *Value;
9292
9393 LiveInBlock(LiveRange &LR, MachineDomTreeNode *node, SlotIndex kill)
94 : LR(LR), DomNode(node), Kill(kill), Value(0) {}
94 : LR(LR), DomNode(node), Kill(kill), Value(nullptr) {}
9595 };
9696
9797 /// LiveIn - Work list of blocks where the live-in value has yet to be
124124 void updateLiveIns();
125125
126126 public:
127 LiveRangeCalc() : MF(0), MRI(0), Indexes(0), DomTree(0), Alloc(0) {}
127 LiveRangeCalc() : MF(nullptr), MRI(nullptr), Indexes(nullptr),
128 DomTree(nullptr), Alloc(nullptr) {}
128129
129130 //===--------------------------------------------------------------------===//
130131 // High-level interface.
202203 /// addLiveInBlock().
203204 void setLiveOutValue(MachineBasicBlock *MBB, VNInfo *VNI) {
204205 Seen.set(MBB->getNumber());
205 LiveOut[MBB] = LiveOutPair(VNI, (MachineDomTreeNode *)0);
206 LiveOut[MBB] = LiveOutPair(VNI, nullptr);
206207 }
207208
208209 /// addLiveInBlock - Add a block with an unknown live-in value. This
6464 LiveRegMatrix *Matrix;
6565 RegisterClassInfo RegClassInfo;
6666
67 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
67 RegAllocBase()
68 : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
6869
6970 virtual ~RegAllocBase() {}
7071
6060 public:
6161 CoalescerPair(const TargetRegisterInfo &tri)
6262 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
63 Partial(false), CrossClass(false), Flipped(false), NewRC(0) {}
63 Partial(false), CrossClass(false), Flipped(false), NewRC(nullptr) {}
6464
6565 /// Create a CoalescerPair representing a virtreg-to-physreg copy.
6666 /// No need to call setRegisters().
6767 CoalescerPair(unsigned VirtReg, unsigned PhysReg,
6868 const TargetRegisterInfo &tri)
6969 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
70 Partial(false), CrossClass(false), Flipped(false), NewRC(0) {}
70 Partial(false), CrossClass(false), Flipped(false), NewRC(nullptr) {}
7171
7272 /// setRegisters - set registers to match the copy instruction MI. Return
7373 /// false if MI is not a coalescable copy instruction.
138138 public:
139139 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
140140
141 bool IsValid() const { return Node != NULL; }
141 bool IsValid() const { return Node != nullptr; }
142142
143143 MVT GetValue() const {
144144 assert(IsValid() && "bad iterator");
9595 DebugLoc dl;
9696 unsigned SDNodeOrder;
9797 public:
98 DanglingDebugInfo() : DI(0), dl(DebugLoc()), SDNodeOrder(0) { }
98 DanglingDebugInfo() : DI(nullptr), dl(DebugLoc()), SDNodeOrder(0) { }
9999 DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
100100 DI(di), dl(DL), SDNodeOrder(SDNO) { }
101101 const DbgValueInst* getDI() { return DI; }
134134 MachineBasicBlock* BB;
135135 uint32_t ExtraWeight;
136136
137 Case() : Low(0), High(0), BB(0), ExtraWeight(0) { }
137 Case() : Low(nullptr), High(nullptr), BB(nullptr), ExtraWeight(0) { }
138138 Case(const Constant *low, const Constant *high, MachineBasicBlock *bb,
139139 uint32_t extraweight) : Low(low), High(high), BB(bb),
140140 ExtraWeight(extraweight) { }
395395 /// the same function, use the same failure basic block).
396396 class StackProtectorDescriptor {
397397 public:
398 StackProtectorDescriptor() : ParentMBB(0), SuccessMBB(0), FailureMBB(0),
399 Guard(0) { }
398 StackProtectorDescriptor() : ParentMBB(nullptr), SuccessMBB(nullptr),
399 FailureMBB(nullptr), Guard(nullptr) { }
400400 ~StackProtectorDescriptor() { }
401401
402402 /// Returns true if all fields of the stack protector descriptor are
431431 /// parent mbb after we create the stack protector check (SuccessMBB). This
432432 /// BB is visited only on stack protector check success.
433433 void resetPerBBState() {
434 ParentMBB = 0;
435 SuccessMBB = 0;
434 ParentMBB = nullptr;
435 SuccessMBB = nullptr;
436436 }
437437
438438 /// Reset state that only changes when we switch functions.
445445 /// 2.The guard variable since the guard variable we are checking against is
446446 /// always the same.
447447 void resetPerFunctionState() {
448 FailureMBB = 0;
449 Guard = 0;
448 FailureMBB = nullptr;
449 Guard = nullptr;
450450 }
451451
452452 MachineBasicBlock *getParentMBB() { return ParentMBB; }
481481 /// block will be created.
482482 MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
483483 MachineBasicBlock *ParentMBB,
484 MachineBasicBlock *SuccMBB = 0);
484 MachineBasicBlock *SuccMBB = nullptr);
485485 };
486486
487487 private:
537537
538538 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
539539 CodeGenOpt::Level ol)
540 : CurInst(NULL), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
540 : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
541541 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
542542 HasTailCall(false) {
543543 }
599599
600600 void setValue(const Value *V, SDValue NewN) {
601601 SDValue &N = NodeMap[V];
602 assert(N.getNode() == 0 && "Already set a value for this node!");
602 assert(!N.getNode() && "Already set a value for this node!");
603603 N = NewN;
604604 }
605605
606606 void setUnusedArgValue(const Value *V, SDValue NewN) {
607607 SDValue &N = UnusedArgNodeMap[V];
608 assert(N.getNode() == 0 && "Already set a value for this node!");
608 assert(!N.getNode() && "Already set a value for this node!");
609609 N = NewN;
610610 }
611611
623623 void CopyToExportRegsIfNeeded(const Value *V);
624624 void ExportFromCurrentBlock(const Value *V);
625625 void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
626 MachineBasicBlock *LandingPad = NULL);
626 MachineBasicBlock *LandingPad = nullptr);
627627
628628 std::pair LowerCallOperands(const CallInst &CI,
629629 unsigned ArgIdx,
6464 public:
6565 static char ID; // Pass identification, replacement for typeid.
6666
67 SpillPlacement() : MachineFunctionPass(ID), nodes(0) {}
67 SpillPlacement() : MachineFunctionPass(ID), nodes(nullptr) {}
6868 ~SpillPlacement() { releaseMemory(); }
6969
7070 /// BorderConstraint - A basic block has separate constraints for entry and
416416 /// @param LRMap When not null, this vector will map each live range in Edit
417417 /// back to the indices returned by openIntv.
418418 /// There may be extra indices created by dead code elimination.
419 void finish(SmallVectorImpl *LRMap = 0);
419 void finish(SmallVectorImpl *LRMap = nullptr);
420420
421421 /// dump - print the current interval maping to dbgs().
422422 void dump() const;
147147 /// valid on completely unknown type sets. If Pred is non-null, only MVTs
148148 /// that pass the predicate are added.
149149 bool FillWithPossibleTypes(TreePattern &TP,
150 bool (*Pred)(MVT::SimpleValueType) = 0,
151 const char *PredicateName = 0);
150 bool (*Pred)(MVT::SimpleValueType) = nullptr,
151 const char *PredicateName = nullptr);
152152 };
153153 }
154154
328328 public:
329329 TreePatternNode(Record *Op, const std::vector &Ch,
330330 unsigned NumResults)
331 : Operator(Op), Val(0), TransformFn(0), Children(Ch) {
331 : Operator(Op), Val(nullptr), TransformFn(nullptr), Children(Ch) {
332332 Types.resize(NumResults);
333333 }
334334 TreePatternNode(Init *val, unsigned NumResults) // leaf ctor
335 : Operator(0), Val(val), TransformFn(0) {
335 : Operator(nullptr), Val(val), TransformFn(nullptr) {
336336 Types.resize(NumResults);
337337 }
338338 ~TreePatternNode();
341341 const std::string &getName() const { return Name; }
342342 void setName(StringRef N) { Name.assign(N.begin(), N.end()); }
343343
344 bool isLeaf() const { return Val != 0; }
344 bool isLeaf() const { return Val != nullptr; }
345345
346346 // Type accessors.
347347 unsigned getNumTypes() const { return Types.size(); }
579579 /// patterns as possible. Return true if all types are inferred, false
580580 /// otherwise. Bail out if a type contradiction is found.
581581 bool InferAllTypes(const StringMap >
582 *NamedTypes=0);
582 *NamedTypes=nullptr);
583583
584584 /// error - If this is the first error in the current resolution step,
585585 /// print it and set the error flag. Otherwise, continue silently.
618618 const std::vector &operands,
619619 const std::vector &impresults)
620620 : Pattern(TP), Results(results), Operands(operands),
621 ImpResults(impresults), ResultPattern(0) {}
621 ImpResults(impresults), ResultPattern(nullptr) {}
622622
623623 TreePattern *getPattern() const { return Pattern; }
624624 unsigned getNumResults() const { return Results.size(); }
767767 return PatternFragments.find(R)->second;
768768 }
769769 TreePattern *getPatternFragmentIfRead(Record *R) const {
770 if (!PatternFragments.count(R)) return 0;
770 if (!PatternFragments.count(R)) return nullptr;
771771 return PatternFragments.find(R)->second;
772772 }
773773
7070 // Returns NULL if this and Idx don't compose.
7171 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
7272 CompMap::const_iterator I = Composed.find(Idx);
73 return I == Composed.end() ? 0 : I->second;
73 return I == Composed.end() ? nullptr : I->second;
7474 }
7575
7676 // Add a composite subreg index: this+A = B.
8989 B->Offset = Offset + A->Offset;
9090 B->Size = A->Size;
9191 }
92 return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second;
92 return (Ins.second || Ins.first->second == B) ? nullptr
93 : Ins.first->second;
9394 }
9495
9596 // Update the composite maps of components specified in 'ComposedOf'.
413414 // contain this unit.
414415 unsigned RegClassUnitSetsIdx;
415416
416 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) { Roots[0] = Roots[1] = 0; }
417 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) {
418 Roots[0] = Roots[1] = nullptr;
419 }
417420
418421 ArrayRef getRoots() const {
419422 assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
571574
572575 // Create a native register unit that is associated with one or two root
573576 // registers.
574 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = 0) {
577 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) {
575578 RegUnits.resize(RegUnits.size() + 1);
576579 RegUnits.back().Roots[0] = R0;
577580 RegUnits.back().Roots[1] = R1;
5555 RecVec Aliases;
5656
5757 CodeGenSchedRW()
58 : Index(0), TheDef(0), IsRead(false), IsAlias(false),
58 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
5959 HasVariants(false), IsVariadic(false), IsSequence(false) {}
6060 CodeGenSchedRW(unsigned Idx, Record *Def)
6161 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
7373
7474 CodeGenSchedRW(unsigned Idx, bool Read, const IdxVec &Seq,
7575 const std::string &Name)
76 : Index(Idx), Name(Name), TheDef(0), IsRead(Read), IsAlias(false),
76 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false),
7777 HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) {
7878 assert(Sequence.size() > 1 && "implied sequence needs >1 RWs");
7979 }
141141 // off to join another inferred class.
142142 RecVec InstRWs;
143143
144 CodeGenSchedClass(): Index(0), ItinClassDef(0) {}
144 CodeGenSchedClass(): Index(0), ItinClassDef(nullptr) {}
145145
146146 bool isKeyEqual(Record *IC, const IdxVec &W, const IdxVec &R) {
147147 return ItinClassDef == IC && Writes == W && Reads == R;
206206
207207 Matcher *takeChild(unsigned i) {
208208 Matcher *Res = Children[i];
209 Children[i] = 0;
209 Children[i] = nullptr;
210210 return Res;
211211 }
212212