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[AMDGPU] Choose VMCNT, EXPCNT, LGKMCNT masks and shifts based on the isa version Differential Revision: https://reviews.llvm.org/D24973 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282877 91177308-0d34-0410-b5e6-96231b3b80d8 Konstantin Zhuravlyov 3 years ago
5 changed file(s) with 69 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
4040 #include "llvm/Support/MathExtras.h"
4141
4242 using namespace llvm;
43 using namespace llvm::AMDGPU;
4344
4445 namespace {
4546
20072008 int CntShift;
20082009 int CntMask;
20092010
2011 IsaVersion IV = getIsaVersion(getSTI().getFeatureBits());
20102012 if (CntName == "vmcnt") {
2011 CntMask = 0xf;
2012 CntShift = 0;
2013 CntMask = getVmcntMask(IV);
2014 CntShift = getVmcntShift(IV);
20132015 } else if (CntName == "expcnt") {
2014 CntMask = 0x7;
2015 CntShift = 4;
2016 CntMask = getExpcntMask(IV);
2017 CntShift = getExpcntShift(IV);
20162018 } else if (CntName == "lgkmcnt") {
2017 CntMask = 0xf;
2018 CntShift = 8;
2019 CntMask = getLgkmcntMask(IV);
2020 CntShift = getLgkmcntShift(IV);
20192021 } else {
20202022 return true;
20212023 }
88 //===----------------------------------------------------------------------===//
99
1010 #include "AMDGPUInstPrinter.h"
11 #include "SIDefines.h"
1112 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "SIDefines.h"
1313 #include "Utils/AMDGPUAsmUtils.h"
14 #include "Utils/AMDGPUBaseInfo.h"
1415 #include "llvm/MC/MCExpr.h"
1516 #include "llvm/MC/MCInst.h"
1617 #include "llvm/MC/MCInstrInfo.h"
1718 #include "llvm/MC/MCRegisterInfo.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
1820 #include "llvm/Support/MathExtras.h"
1921 #include "llvm/Support/raw_ostream.h"
2022
2123 #include
2224
2325 using namespace llvm;
26 using namespace llvm::AMDGPU;
2427
2528 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
2629 StringRef Annot, const MCSubtargetInfo &STI) {
863866 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
864867 const MCSubtargetInfo &STI,
865868 raw_ostream &O) {
869 IsaVersion IV = getIsaVersion(STI.getFeatureBits());
870
866871 unsigned SImm16 = MI->getOperand(OpNo).getImm();
867 unsigned Vmcnt = SImm16 & 0xF;
868 unsigned Expcnt = (SImm16 >> 4) & 0x7;
869 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
872 unsigned Vmcnt = (SImm16 >> getVmcntShift(IV)) & getVmcntMask(IV);
873 unsigned Expcnt = (SImm16 >> getExpcntShift(IV)) & getExpcntMask(IV);
874 unsigned Lgkmcnt = (SImm16 >> getLgkmcntShift(IV)) & getLgkmcntMask(IV);
870875
871876 bool NeedSpace = false;
872877
2020 #include "SIDefines.h"
2121 #include "SIInstrInfo.h"
2222 #include "SIMachineFunctionInfo.h"
23 #include "Utils/AMDGPUBaseInfo.h"
2324 #include "llvm/CodeGen/MachineFunction.h"
2425 #include "llvm/CodeGen/MachineFunctionPass.h"
2526 #include "llvm/CodeGen/MachineInstrBuilder.h"
2829 #define DEBUG_TYPE "si-insert-waits"
2930
3031 using namespace llvm;
32 using namespace llvm::AMDGPU;
3133
3234 namespace {
3335
5860 const SIInstrInfo *TII;
5961 const SIRegisterInfo *TRI;
6062 const MachineRegisterInfo *MRI;
63 IsaVersion IV;
6164
6265 /// \brief Constant hardware limits
6366 static const Counters WaitCounts;
409412
410413 // Build the wait instruction
411414 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
412 .addImm((Counts.Named.VM & 0xF) |
413 ((Counts.Named.EXP & 0x7) << 4) |
414 ((Counts.Named.LGKM & 0xF) << 8));
415 .addImm(((Counts.Named.VM & getVmcntMask(IV)) << getVmcntShift(IV)) |
416 ((Counts.Named.EXP & getExpcntMask(IV)) << getExpcntShift(IV)) |
417 ((Counts.Named.LGKM & getLgkmcntMask(IV)) << getLgkmcntShift(IV)));
415418
416419 LastOpcodeType = OTHER;
417420 LastInstWritesM0 = false;
439442 unsigned Imm = I->getOperand(0).getImm();
440443 Counters Counts, WaitOn;
441444
442 Counts.Named.VM = Imm & 0xF;
443 Counts.Named.EXP = (Imm >> 4) & 0x7;
444 Counts.Named.LGKM = (Imm >> 8) & 0xF;
445 Counts.Named.VM = (Imm >> getVmcntShift(IV)) & getVmcntMask(IV);
446 Counts.Named.EXP = (Imm >> getExpcntShift(IV)) & getExpcntMask(IV);
447 Counts.Named.LGKM = (Imm >> getLgkmcntShift(IV)) & getLgkmcntMask(IV);
445448
446449 for (unsigned i = 0; i < 3; ++i) {
447450 if (Counts.Array[i] <= LastIssued.Array[i])
517520 TII = ST->getInstrInfo();
518521 TRI = &TII->getRegisterInfo();
519522 MRI = &MF.getRegInfo();
523 IV = getIsaVersion(ST->getFeatureBits());
520524
521525 WaitedOn = ZeroCounts;
522526 DelayedWaitOn = ZeroCounts;
151151 return Ints;
152152 }
153153
154 unsigned getVmcntMask(IsaVersion Version) {
155 return 0xf;
156 }
157
158 unsigned getVmcntShift(IsaVersion Version) {
159 return 0;
160 }
161
162 unsigned getExpcntMask(IsaVersion Version) {
163 return 0x7;
164 }
165
166 unsigned getExpcntShift(IsaVersion Version) {
167 return 4;
168 }
169
170 unsigned getLgkmcntMask(IsaVersion Version) {
171 return 0xf;
172 }
173
174 unsigned getLgkmcntShift(IsaVersion Version) {
175 return 8;
176 }
177
154178 unsigned getInitialPSInputAddr(const Function &F) {
155179 return getIntegerAttribute(F, "InitialPSInputAddr", 0);
156180 }
6868 std::pair Default,
6969 bool OnlyFirstRequired = false);
7070
71 /// \returns VMCNT bit mask for given isa \p Version.
72 unsigned getVmcntMask(IsaVersion Version);
73
74 /// \returns VMCNT bit shift for given isa \p Version.
75 unsigned getVmcntShift(IsaVersion Version);
76
77 /// \returns EXPCNT bit mask for given isa \p Version.
78 unsigned getExpcntMask(IsaVersion Version);
79
80 /// \returns EXPCNT bit shift for given isa \p Version.
81 unsigned getExpcntShift(IsaVersion Version);
82
83 /// \returns LGKMCNT bit mask for given isa \p Version.
84 unsigned getLgkmcntMask(IsaVersion Version);
85
86 /// \returns LGKMCNT bit shift for given isa \p Version.
87 unsigned getLgkmcntShift(IsaVersion Version);
88
7189 unsigned getInitialPSInputAddr(const Function &F);
7290
7391 bool isShader(CallingConv::ID cc);