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Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the QADD & QSUB instructions. Behave identically to __qadd & __qsub RealView instruction intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109770 91177308-0d34-0410-b5e6-96231b3b80d8 Nate Begeman 10 years ago
3 changed file(s) with 25 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
1717 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
1818 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
1919 Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
20 }
21
22 //===----------------------------------------------------------------------===//
23 // Saturating Arithmentic
24
25 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
26 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
27 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
28 [IntrNoMem, Commutative]>;
29 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
30 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
2031 }
2132
2233 //===----------------------------------------------------------------------===//
17131713
17141714 // ARM Arithmetic Instruction -- for disassembly only
17151715 // GPR:$dst = GPR:$a op GPR:$b
1716 class AAI op27_20, bits<4> op7_4, string opc>
1716 class AAI op27_20, bits<4> op7_4, string opc,
1717 list pattern = [/* For disassembly only; pattern left blank */]>
17171718 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, IIC_iALUr,
1718 opc, "\t$dst, $a, $b",
1719 [/* For disassembly only; pattern left blank */]> {
1719 opc, "\t$dst, $a, $b", pattern> {
17201720 let Inst{27-20} = op27_20;
17211721 let Inst{7-4} = op7_4;
17221722 }
17231723
17241724 // Saturating add/subtract -- for disassembly only
17251725
1726 def QADD : AAI<0b00010000, 0b0101, "qadd">;
1726 def QADD : AAI<0b00010000, 0b0101, "qadd",
1727 [(set GPR:$dst, (int_arm_qadd GPR:$a, GPR:$b))]>;
17271728 def QADD16 : AAI<0b01100010, 0b0001, "qadd16">;
17281729 def QADD8 : AAI<0b01100010, 0b1001, "qadd8">;
17291730 def QASX : AAI<0b01100010, 0b0011, "qasx">;
17301731 def QDADD : AAI<0b00010100, 0b0101, "qdadd">;
17311732 def QDSUB : AAI<0b00010110, 0b0101, "qdsub">;
17321733 def QSAX : AAI<0b01100010, 0b0101, "qsax">;
1733 def QSUB : AAI<0b00010010, 0b0101, "qsub">;
1734 def QSUB : AAI<0b00010010, 0b0101, "qsub",
1735 [(set GPR:$dst, (int_arm_qsub GPR:$a, GPR:$b))]>;
17341736 def QSUB16 : AAI<0b01100010, 0b0111, "qsub16">;
17351737 def QSUB8 : AAI<0b01100010, 0b1111, "qsub8">;
17361738 def UQADD16 : AAI<0b01100110, 0b0001, "uqadd16">;
14401440
14411441 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
14421442 // And Miscellaneous operations -- for disassembly only
1443 class T2I_pam op22_20, bits<4> op7_4, string opc>
1443 class T2I_pam op22_20, bits<4> op7_4, string opc,
1444 list pat = [/* For disassembly only; pattern left blank */]>
14441445 : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, opc,
1445 "\t$dst, $a, $b", [/* For disassembly only; pattern left blank */]> {
1446 "\t$dst, $a, $b", pat> {
14461447 let Inst{31-27} = 0b11111;
14471448 let Inst{26-23} = 0b0101;
14481449 let Inst{22-20} = op22_20;
14521453
14531454 // Saturating add/subtract -- for disassembly only
14541455
1455 def t2QADD : T2I_pam<0b000, 0b1000, "qadd">;
1456 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1457 [(set GPR:$dst, (int_arm_qadd GPR:$a, GPR:$b))]>;
14561458 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
14571459 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
14581460 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
14591461 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
14601462 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
14611463 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1462 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub">;
1464 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1465 [(set GPR:$dst, (int_arm_qsub GPR:$a, GPR:$b))]>;
14631466 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
14641467 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
14651468 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;