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Revert rL362953 and its followup rL362955. These caused a build failure because I managed not to notice they depended on a later unpushed commit in my current stack. Sorry about that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362956 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 4 months ago
35 changed file(s) with 96 addition(s) and 5073 deletion(s). Raw diff Collapse all Expand all
134134 ELF_RELOC(R_ARM_ME_TOO, 0x80)
135135 ELF_RELOC(R_ARM_THM_TLS_DESCSEQ16, 0x81)
136136 ELF_RELOC(R_ARM_THM_TLS_DESCSEQ32, 0x82)
137 ELF_RELOC(R_ARM_THM_BF16, 0x88)
138 ELF_RELOC(R_ARM_THM_BF12, 0x89)
139 ELF_RELOC(R_ARM_THM_BF18, 0x8a)
140137 ELF_RELOC(R_ARM_IRELATIVE, 0xa0)
120120 ARM_ARCH("armv8-m.main", ARMV8MMainline, "8-M.Mainline", "v8m.main",
121121 ARMBuildAttrs::CPUArch::v8_M_Main, FK_FPV5_D16, ARM::AEK_HWDIVTHUMB)
122122 ARM_ARCH("armv8.1-m.main", ARMV8_1MMainline, "8.1-M.Mainline", "v8.1m.main",
123 ARMBuildAttrs::CPUArch::v8_1_M_Main, FK_FP_ARMV8_FULLFP16_SP_D16, ARM::AEK_HWDIVTHUMB | ARM::AEK_RAS | ARM::AEK_LOB)
123 ARMBuildAttrs::CPUArch::v8_1_M_Main, FK_FP_ARMV8_FULLFP16_SP_D16, ARM::AEK_HWDIVTHUMB | ARM::AEK_RAS)
124124 // Non-standard Arch names.
125125 ARM_ARCH("iwmmxt", IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE,
126126 FK_NONE, ARM::AEK_NONE)
163163 ARM_ARCH_EXT_NAME("xscale", ARM::AEK_XSCALE, nullptr, nullptr)
164164 ARM_ARCH_EXT_NAME("fp16fml", ARM::AEK_FP16FML, "+fp16fml", "-fp16fml")
165165 ARM_ARCH_EXT_NAME("sb", ARM::AEK_SB, "+sb", "-sb")
166 ARM_ARCH_EXT_NAME("lob", ARM::AEK_LOB, "+lob", "-lob")
167166 #undef ARM_ARCH_EXT_NAME
168167
169168 #ifndef ARM_HW_DIV_NAME
5050 AEK_SVE2SHA3 = 1 << 22,
5151 AEK_BITPERM = 1 << 23,
5252 AEK_FP_DP = 1 << 24,
53 AEK_LOB = 1 << 25,
5453 // Unsupported extensions.
5554 AEK_OS = 0x8000000,
5655 AEK_IWMMXT = 0x10000000,
403403
404404 def FeatureSB : SubtargetFeature<"sb", "HasSB", "true",
405405 "Enable v8.5a Speculation Barrier" >;
406
407 // Armv8.1-M extensions
408
409 def FeatureLOB : SubtargetFeature<"lob", "HasLOB", "true",
410 "Enable Low Overhead Branch "
411 "extensions">;
412406
413407 //===----------------------------------------------------------------------===//
414408 // ARM architecture class
810804 Feature8MSecExt,
811805 FeatureAcquireRelease,
812806 FeatureMClass,
813 FeatureRAS,
814 FeatureLOB]>;
807 FeatureRAS]>;
815808
816809 // Aliases
817810 def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>;
761761
762762 //===----------------------------------------------------------------------===//
763763
764 static MCSymbol *getBFLabel(StringRef Prefix, unsigned FunctionNumber,
765 unsigned LabelId, MCContext &Ctx) {
766
767 MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
768 + "BF" + Twine(FunctionNumber) + "_" + Twine(LabelId));
769 return Label;
770 }
771
772764 static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
773765 unsigned LabelId, MCContext &Ctx) {
774766
14431435 EmitToStreamer(*OutStreamer, TmpInst);
14441436 return;
14451437 }
1446 case ARM::t2BFi:
1447 case ARM::t2BFic:
1448 case ARM::t2BFLi:
1449 case ARM::t2BFr:
1450 case ARM::t2BFLr: {
1451 // This is a Branch Future instruction.
1452
1453 const MCExpr *BranchLabel = MCSymbolRefExpr::create(
1454 getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1455 MI->getOperand(0).getIndex(), OutContext),
1456 OutContext);
1457
1458 auto MCInst = MCInstBuilder(Opc).addExpr(BranchLabel);
1459 if (MI->getOperand(1).isReg()) {
1460 // For BFr/BFLr
1461 MCInst.addReg(MI->getOperand(1).getReg());
1462 } else {
1463 // For BFi/BFLi/BFic
1464 const MCExpr *BranchTarget;
1465 if (MI->getOperand(1).isMBB())
1466 BranchTarget = MCSymbolRefExpr::create(
1467 MI->getOperand(1).getMBB()->getSymbol(), OutContext);
1468 else if (MI->getOperand(1).isGlobal()) {
1469 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1470 BranchTarget = MCSymbolRefExpr::create(
1471 GetARMGVSymbol(GV, MI->getOperand(1).getTargetFlags()), OutContext);
1472 } else if (MI->getOperand(1).isSymbol()) {
1473 BranchTarget = MCSymbolRefExpr::create(
1474 GetExternalSymbolSymbol(MI->getOperand(1).getSymbolName()),
1475 OutContext);
1476 }
1477
1478 MCInst.addExpr(BranchTarget);
1479 }
1480
1481 if (Opc == ARM::t2BFic) {
1482 const MCExpr *ElseLabel = MCSymbolRefExpr::create(
1483 getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1484 MI->getOperand(2).getIndex(), OutContext),
1485 OutContext);
1486 MCInst.addExpr(ElseLabel);
1487 MCInst.addImm(MI->getOperand(3).getImm());
1488 } else {
1489 MCInst.addImm(MI->getOperand(2).getImm())
1490 .addReg(MI->getOperand(3).getReg());
1491 }
1492
1493 EmitToStreamer(*OutStreamer, MCInst);
1494 return;
1495 }
1496 case ARM::t2BF_LabelPseudo: {
1497 // This is a pseudo op for a label used by a branch future instruction
1498
1499 // Emit the label.
1500 OutStreamer->EmitLabel(getBFLabel(DL.getPrivateGlobalPrefix(),
1501 getFunctionNumber(),
1502 MI->getOperand(0).getIndex(), OutContext));
1503 return;
1504 }
15051438 case ARM::tPICADD: {
15061439 // This is a pseudo op for a label + instruction sequence, which looks like:
15071440 // LPC0:
202202 for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI)
203203 if (Reserved.test(*SI))
204204 markSuperRegs(Reserved, Reg);
205 // For v8.1m architecture
206 markSuperRegs(Reserved, ARM::ZR);
207205
208206 assert(checkAllSuperRegsMarked(Reserved));
209207 return Reserved;
366366 let DecoderMethod = "DecodeRegListOperand";
367367 }
368368
369 // A list of general purpose registers and APSR separated by comma.
370 // Used by CLRM
371 def RegListWithAPSRAsmOperand : AsmOperandClass { let Name = "RegListWithAPSR"; }
372 def reglist_with_apsr : Operand {
373 let EncoderMethod = "getRegisterListOpValue";
374 let ParserMatchClass = RegListWithAPSRAsmOperand;
375 let PrintMethod = "printRegisterList";
376 let DecoderMethod = "DecodeRegListOperand";
377 }
378
379369 def GPRPairOp : RegisterOperand;
380370
381371 def DPRRegListAsmOperand : AsmOperandClass {
398388 let ParserMatchClass = SPRRegListAsmOperand;
399389 let PrintMethod = "printRegisterList";
400390 let DecoderMethod = "DecodeSPRRegListOperand";
401 }
402
403 def FPSRegListWithVPRAsmOperand : AsmOperandClass { let Name =
404 "FPSRegListWithVPR"; }
405 def fp_sreglist_with_vpr : Operand {
406 let EncoderMethod = "getRegisterListOpValue";
407 let ParserMatchClass = FPSRegListWithVPRAsmOperand;
408 let PrintMethod = "printRegisterList";
409 }
410 def FPDRegListWithVPRAsmOperand : AsmOperandClass { let Name =
411 "FPDRegListWithVPR"; }
412 def fp_dreglist_with_vpr : Operand {
413 let EncoderMethod = "getRegisterListOpValue";
414 let ParserMatchClass = FPDRegListWithVPRAsmOperand;
415 let PrintMethod = "printRegisterList";
416391 }
417392
418393 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
149149
150150 // Define Thumb2 specific addressing modes.
151151
152 // t2_addr_offset_none := reg
153 def MemNoOffsetT2AsmOperand
154 : AsmOperandClass { let Name = "MemNoOffsetT2"; }
155 def t2_addr_offset_none : MemOperand {
156 let PrintMethod = "printAddrMode7Operand";
157 let DecoderMethod = "DecodeGPRnopcRegisterClass";
158 let ParserMatchClass = MemNoOffsetT2AsmOperand;
159 let MIOperandInfo = (ops GPRnopc:$base);
160 }
161
162 // t2_nosp_addr_offset_none := reg
163 def MemNoOffsetT2NoSpAsmOperand
164 : AsmOperandClass { let Name = "MemNoOffsetT2NoSp"; }
165 def t2_nosp_addr_offset_none : MemOperand {
166 let PrintMethod = "printAddrMode7Operand";
167 let DecoderMethod = "Decodet2rGPRRegisterClass";
168 let ParserMatchClass = MemNoOffsetT2NoSpAsmOperand;
169 let MIOperandInfo = (ops t2rGPR:$base);
170 }
171
172152 // t2addrmode_imm12 := reg + imm12
173153 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
174154 def t2addrmode_imm12 : MemOperand,
266246 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
267247 def t2am_imm8s4_offset : MemOperand {
268248 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
269 let EncoderMethod = "getT2ScaledImmOpValue<8,2>";
249 let EncoderMethod = "getT2Imm8s4OpValue";
270250 let DecoderMethod = "DecodeT2Imm8S4";
271 }
272
273 // t2addrmode_imm7s4 := reg +/- (imm7 << 2)
274 def MemImm7s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm7s4Offset";}
275 class T2AddrMode_Imm7s4 : MemOperand {
276 let EncoderMethod = "getT2AddrModeImm7s4OpValue";
277 let DecoderMethod = "DecodeT2AddrModeImm7<2,0>";
278 let ParserMatchClass = MemImm7s4OffsetAsmOperand;
279 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
280 }
281
282 def t2addrmode_imm7s4 : T2AddrMode_Imm7s4 {
283 // They are printed the same way as the imm8 version
284 let PrintMethod = "printT2AddrModeImm8s4Operand";
285 }
286
287 def t2addrmode_imm7s4_pre : T2AddrMode_Imm7s4 {
288 // They are printed the same way as the imm8 version
289 let PrintMethod = "printT2AddrModeImm8s4Operand";
290 }
291
292 def t2am_imm7s4_offset_asmoperand : AsmOperandClass { let Name = "Imm7s4"; }
293 def t2am_imm7s4_offset : MemOperand {
294 // They are printed the same way as the imm8 version
295 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
296 let ParserMatchClass = t2am_imm7s4_offset_asmoperand;
297 let EncoderMethod = "getT2ScaledImmOpValue<7,2>";
298 let DecoderMethod = "DecodeT2Imm7S4";
299251 }
300252
301253 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
336288 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
337289 }
338290
339 // Define ARMv8.1-M specific addressing modes.
340
341 // Label operands for BF/BFL/WLS/DLS/LE
342 class BFLabelOp
343 : Operand {
344 let EncoderMethod = !strconcat("getBFTargetOpValue<", isNeg, ", ",
345 fixup, ">");
346 let OperandType = "OPERAND_PCREL";
347 let DecoderMethod = !strconcat("DecodeBFLabelOperand<", signed, ", ",
348 isNeg, ", ", size, ">");
349 }
350 def bflabel_u4 : BFLabelOp<"false", "false", "4", "ARM::fixup_bf_branch">;
351 def bflabel_s12 : BFLabelOp<"true", "false", "12", "ARM::fixup_bfc_target">;
352 def bflabel_s16 : BFLabelOp<"true", "false", "16", "ARM::fixup_bf_target">;
353 def bflabel_s18 : BFLabelOp<"true", "false", "18", "ARM::fixup_bfl_target">;
354 def wlslabel_u11 : BFLabelOp<"false", "false", "11", "ARM::fixup_wls">;
355 def lelabel_u11 : BFLabelOp<"false", "true", "11", "ARM::fixup_le">;
356
357 def bfafter_target : Operand {
358 let EncoderMethod = "getBFAfterTargetOpValue";
359 let OperandType = "OPERAND_PCREL";
360 let DecoderMethod = "DecodeBFAfterTargetOperand";
361 }
362
363 // pred operand excluding AL
364 def pred_noal_asmoperand : AsmOperandClass {
365 let Name = "CondCodeNoAL";
366 let RenderMethod = "addITCondCodeOperands";
367 let PredicateMethod = "isITCondCodeNoAL";
368 let ParserMethod = "parseITCondCode";
369 }
370 def pred_noal : Operand {
371 let PrintMethod = "printMandatoryPredicateOperand";
372 let ParserMatchClass = pred_noal_asmoperand;
373 let DecoderMethod = "DecodePredNoALOperand";
374 }
375
376
377 // CSEL aliases inverted predicate
378 def pred_noal_inv_asmoperand : AsmOperandClass {
379 let Name = "CondCodeNoALInv";
380 let RenderMethod = "addITCondCodeInvOperands";
381 let PredicateMethod = "isITCondCodeNoAL";
382 let ParserMethod = "parseITCondCode";
383 }
384 def pred_noal_inv : Operand {
385 let PrintMethod = "printMandatoryInvertedPredicateOperand";
386 let ParserMatchClass = pred_noal_inv_asmoperand;
387 }
388291 //===----------------------------------------------------------------------===//
389292 // Multiclass helpers...
390293 //
50074910 def : InstAlias<"pli${p} $addr",
50084911 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
50094912 Requires<[IsThumb2,HasV7]>;
5010
5011
5012 //===----------------------------------------------------------------------===//
5013 // ARMv8.1m instructions
5014 //
5015
5016 class V8_1MI
5017 string ops, string cstr, list pattern>
5018 : Thumb2XI
5019 pattern>,
5020 Requires<[HasV8_1MMainline]>;
5021
5022 def t2CLRM : V8_1MI<(outs),
5023 (ins pred:$p, reglist_with_apsr:$regs, variable_ops),
5024 AddrModeNone, NoItinerary, "clrm", "${p}\t$regs", "", []> {
5025 bits<16> regs;
5026
5027 let Inst{31-16} = 0b1110100010011111;
5028 let Inst{15-14} = regs{15-14};
5029 let Inst{13} = 0b0;
5030 let Inst{12-0} = regs{12-0};
5031 }
5032
5033 class t2BF
5034 : V8_1MI<(outs ), iops, AddrModeNone, NoItinerary, asm, ops, "", []> {
5035
5036 let Inst{31-27} = 0b11110;
5037 let Inst{15-14} = 0b11;
5038 let Inst{12} = 0b0;
5039 let Inst{0} = 0b1;
5040
5041 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];
5042 }
5043
5044 def t2BF_LabelPseudo
5045 : t2PseudoInst<(outs ), (ins pclabel:$cp), 0, NoItinerary, []> {
5046 let isTerminator = 1;
5047 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];
5048 }
5049
5050 def t2BFi : t2BF<(ins bflabel_u4:$b_label, bflabel_s16:$label, pred:$p),
5051 !strconcat("bf", "${p}"), "$b_label, $label"> {
5052 bits<4> b_label;
5053 bits<16> label;
5054
5055 let Inst{26-23} = b_label{3-0};
5056 let Inst{22-21} = 0b10;
5057 let Inst{20-16} = label{15-11};
5058 let Inst{13} = 0b1;
5059 let Inst{11} = label{0};
5060 let Inst{10-1} = label{10-1};
5061 }
5062
5063 def t2BFic : t2BF<(ins bflabel_u4:$b_label, bflabel_s12:$label,
5064 bfafter_target:$ba_label, pred_noal:$bcond), "bfcsel",
5065 "$b_label, $label, $ba_label, $bcond"> {
5066 bits<4> bcond;
5067 bits<12> label;
5068 bits<1> ba_label;
5069 bits<4> b_label;
5070
5071 let Inst{26-23} = b_label{3-0};
5072 let Inst{22} = 0b0;
5073 let Inst{21-18} = bcond{3-0};
5074 let Inst{17} = ba_label{0};
5075 let Inst{16} = label{11};
5076 let Inst{13} = 0b1;
5077 let Inst{11} = label{0};
5078 let Inst{10-1} = label{10-1};
5079 }
5080
5081 def t2BFr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p),
5082 !strconcat("bfx", "${p}"), "$b_label, $Rn"> {
5083 bits<4> b_label;
5084 bits<4> Rn;
5085
5086 let Inst{26-23} = b_label{3-0};
5087 let Inst{22-20} = 0b110;
5088 let Inst{19-16} = Rn{3-0};
5089 let Inst{13-1} = 0b1000000000000;
5090 }
5091
5092 def t2BFLi : t2BF<(ins bflabel_u4:$b_label, bflabel_s18:$label, pred:$p),
5093 !strconcat("bfl", "${p}"), "$b_label, $label"> {
5094 bits<4> b_label;
5095 bits<18> label;
5096
5097 let Inst{26-23} = b_label{3-0};
5098 let Inst{22-16} = label{17-11};
5099 let Inst{13} = 0b0;
5100 let Inst{11} = label{0};
5101 let Inst{10-1} = label{10-1};
5102 }
5103
5104 def t2BFLr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p),
5105 !strconcat("bflx", "${p}"), "$b_label, $Rn"> {
5106 bits<4> b_label;
5107 bits<4> Rn;
5108
5109 let Inst{26-23} = b_label{3-0};
5110 let Inst{22-20} = 0b111;
5111 let Inst{19-16} = Rn{3-0};
5112 let Inst{13-1} = 0b1000000000000;
5113 }
5114
5115 class t2LOL
5116 : V8_1MI {
5117 let Inst{31-23} = 0b111100000;
5118 let Inst{15-14} = 0b11;
5119 let Inst{0} = 0b1;
5120 let isBranch = 1;
5121 let isTerminator = 1;
5122 let DecoderMethod = "DecodeLOLoop";
5123 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];
5124 }
5125
5126 def t2WLS : t2LOL<(outs GPRlr:$LR),
5127 (ins rGPR:$Rn, wlslabel_u11:$label),
5128 "wls", "$LR, $Rn, $label"> {
5129 bits<4> Rn;
5130 bits<11> label;
5131 let Inst{22-20} = 0b100;
5132 let Inst{19-16} = Rn{3-0};
5133 let Inst{13-12} = 0b00;
5134 let Inst{11} = label{0};
5135 let Inst{10-1} = label{10-1};
5136 let usesCustomInserter = 1;
5137 }
5138
5139 def t2DLS : t2LOL<(outs GPRlr:$LR), (ins rGPR:$Rn),
5140 "dls", "$LR, $Rn"> {
5141 bits<4> Rn;
5142 let isBranch = 0;
5143 let isTerminator = 0;
5144 let Inst{22-20} = 0b100;
5145 let Inst{19-16} = Rn{3-0};
5146 let Inst{13-1} = 0b1000000000000;
5147 let usesCustomInserter = 1;
5148 }
5149
5150 def t2LEUpdate : t2LOL<(outs GPRlr:$LRout),
5151 (ins GPRlr:$LRin, lelabel_u11:$label),
5152 "le", "$LRin, $label"> {
5153 bits<11> label;
5154 let Inst{22-16} = 0b0001111;
5155 let Inst{13-12} = 0b00;
5156 let Inst{11} = label{0};
5157 let Inst{10-1} = label{10-1};
5158 let usesCustomInserter = 1;
5159 }
5160
5161 def t2LE : t2LOL<(outs ), (ins lelabel_u11:$label), "le", "$label"> {
5162 bits<11> label;
5163 let Inst{22-16} = 0b0101111;
5164 let Inst{13-12} = 0b00;
5165 let Inst{11} = label{0};
5166 let Inst{10-1} = label{10-1};
5167 }
5168
5169 class CS opcode, list pattern=[]>
5170 : V8_1MI<(outs rGPR:$Rd), (ins GPRwithZR:$Rn, GPRwithZR:$Rm, pred_noal:$fcond),
5171 AddrModeNone, NoItinerary, iname, "$Rd, $Rn, $Rm, $fcond", "", pattern> {
5172 bits<4> Rd;
5173 bits<4> Rm;
5174 bits<4> Rn;
5175 bits<4> fcond;
5176
5177 let Inst{31-20} = 0b111010100101;
5178 let Inst{19-16} = Rn{3-0};
5179 let Inst{15-12} = opcode;
5180 let Inst{11-8} = Rd{3-0};
5181 let Inst{7-4} = fcond{3-0};
5182 let Inst{3-0} = Rm{3-0};
5183
5184 let Uses = [CPSR];
5185 }
5186
5187 def t2CSEL : CS<"csel", 0b1000>;
5188 def t2CSINC : CS<"csinc", 0b1001>;
5189 def t2CSINV : CS<"csinv", 0b1010>;
5190 def t2CSNEG : CS<"csneg", 0b1011>;
5191
5192
5193 // CS aliases.
5194 let Predicates = [HasV8_1MMainline] in {
5195 def : InstAlias<"csetm\t$Rd, $fcond",
5196 (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;
5197
5198 def : InstAlias<"cset\t$Rd, $fcond",
5199 (t2CSINC rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;
5200
5201 def : InstAlias<"cinc\t$Rd, $Rn, $fcond",
5202 (t2CSINC rGPR:$Rd, GPRwithZR:$Rn, GPRwithZR:$Rn, pred_noal_inv:$fcond)>;
5203
5204 def : InstAlias<"cinv\t$Rd, $Rn, $fcond",
5205 (t2CSINV rGPR:$Rd, GPRwithZR:$Rn, GPRwithZR:$Rn, pred_noal_inv:$fcond)>;
5206
5207 def : InstAlias<"cneg\t$Rd, $Rn, $fcond",
5208 (t2CSNEG rGPR:$Rd, GPRwithZR:$Rn, GPRwithZR:$Rn, pred_noal_inv:$fcond)>;
5209 }
22982298 let Inst{3-0} = 0b0000;
22992299 }
23002300
2301 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
2302 // to APSR.
2303 let Defs = [CPSR], Uses = [FPSCR_NZCV], Predicates = [HasFPRegs],
2304 Rt = 0b1111 /* apsr_nzcv */ in
2305 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
2306 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
2307
23012308 let DecoderMethod = "DecodeForVMRSandVMSR" in {
2302 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
2303 // to APSR.
2304 let Defs = [CPSR], Uses = [FPSCR_NZCV], Predicates = [HasFPRegs],
2305 Rt = 0b1111 /* apsr_nzcv */ in
2306 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
2307 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
2308
23092309 // Application level FPSCR -> GPR
23102310 let hasSideEffects = 1, Uses = [FPSCR], Predicates = [HasFPRegs] in
23112311 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins),
23302330 "vmrs", "\t$Rt, fpinst", []>;
23312331 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPRnopc:$Rt),
23322332 (ins), "vmrs", "\t$Rt, fpinst2", []>;
2333 let Predicates = [HasV8_1MMainline, HasFPRegs] in {
2334 // System level FPSCR_NZCVQC -> GPR
2335 def VMRS_FPSCR_NZCVQC
2336 : MovFromVFP<0b0010 /* fpscr_nzcvqc */,
2337 (outs GPR:$Rt), (ins cl_FPSCR_NZCV:$fpscr_in),
2338 "vmrs", "\t$Rt, fpscr_nzcvqc", []>;
2339 }
2340 }
2341 let Predicates = [HasV8_1MMainline, Has8MSecExt] in {
2342 // System level FPSCR -> GPR, with context saving for security extensions
2343 def VMRS_FPCXTNS : MovFromVFP<0b1110 /* fpcxtns */, (outs GPR:$Rt), (ins),
2344 "vmrs", "\t$Rt, fpcxtns", []>;
2345 }
2346 let Predicates = [HasV8_1MMainline, Has8MSecExt] in {
2347 // System level FPSCR -> GPR, with context saving for security extensions
2348 def VMRS_FPCXTS : MovFromVFP<0b1111 /* fpcxts */, (outs GPR:$Rt), (ins),
2349 "vmrs", "\t$Rt, fpcxts", []>;
2350 }
2351
2352 let Predicates = [HasV8_1MMainline, HasMVEInt] in {
2353 // System level VPR/P0 -> GPR
2354 let Uses = [VPR] in
2355 def VMRS_VPR : MovFromVFP<0b1100 /* vpr */, (outs GPR:$Rt), (ins),
2356 "vmrs", "\t$Rt, vpr", []>;
2357
2358 def VMRS_P0 : MovFromVFP<0b1101 /* p0 */, (outs GPR:$Rt), (ins VCCR:$cond),
2359 "vmrs", "\t$Rt, p0", []>;
23602333 }
23612334 }
23622335
23792352 let Inst{11-8} = 0b1010;
23802353 let Inst{7} = 0;
23812354 let Inst{4} = 1;
2382 let Predicates = [HasVFP2];
23832355 }
23842356
23852357 let DecoderMethod = "DecodeForVMRSandVMSR" in {
23992371 "vmsr", "\tfpinst, $src", []>;
24002372 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPRnopc:$src),
24012373 "vmsr", "\tfpinst2, $src", []>;
2402 }
2403 let Predicates = [HasV8_1MMainline, Has8MSecExt] in {
2404 // System level GPR -> FPSCR with context saving for security extensions
2405 def VMSR_FPCXTNS : MovToVFP<0b1110 /* fpcxtns */, (outs), (ins GPR:$src),
2406 "vmsr", "\tfpcxtns, $src", []>;
2407 }
2408 let Predicates = [HasV8_1MMainline, Has8MSecExt] in {
2409 // System level GPR -> FPSCR with context saving for security extensions
2410 def VMSR_FPCXTS : MovToVFP<0b1111 /* fpcxts */, (outs), (ins GPR:$src),
2411 "vmsr", "\tfpcxts, $src", []>;
2412 }
2413 let Predicates = [HasV8_1MMainline, HasFPRegs] in {
2414 // System level GPR -> FPSCR_NZCVQC
2415 def VMSR_FPSCR_NZCVQC
2416 : MovToVFP<0b0010 /* fpscr_nzcvqc */,
2417 (outs cl_FPSCR_NZCV:$fpscr_out), (ins GPR:$src),
2418 "vmsr", "\tfpscr_nzcvqc, $src", []>;
2419 }
2420
2421 let Predicates = [HasV8_1MMainline, HasMVEInt] in {
2422 // System level GPR -> VPR/P0
2423 let Defs = [VPR] in
2424 def VMSR_VPR : MovToVFP<0b1100 /* vpr */, (outs), (ins GPR:$src),
2425 "vmsr", "\tvpr, $src", []>;
2426
2427 def VMSR_P0 : MovToVFP<0b1101 /* p0 */, (outs VCCR:$cond), (ins GPR:$src),
2428 "vmsr", "\tp0, $src", []>;
24292374 }
24302375 }
24312376
26032548 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>;
26042549 def : VFP3InstAlias<"fconsts${p} $Sd, $val",
26052550 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;
2606
2607 def VSCCLRMD : VFPXI<(outs), (ins pred:$p, fp_dreglist_with_vpr:$regs, variable_ops),
2608 AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary,
2609 "vscclrm{$p}\t$regs", "", []>, Sched<[]> {
2610 bits<13> regs;
2611 let Inst{31-23} = 0b111011001;
2612 let Inst{22} = regs{12};
2613 let Inst{21-16} = 0b011111;
2614 let Inst{15-12} = regs{11-8};
2615 let Inst{11-8} = 0b1011;
2616 let Inst{7-0} = regs{7-0};
2617
2618 let DecoderMethod = "DecodeVSCCLRM";
2619
2620 list Predicates = [HasV8_1MMainline, Has8MSecExt];
2621 }
2622
2623 def VSCCLRMS : VFPXI<(outs), (ins pred:$p, fp_sreglist_with_vpr:$regs, variable_ops),
2624 AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary,
2625 "vscclrm{$p}\t$regs", "", []>, Sched<[]> {
2626 bits<13> regs;
2627 let Inst{31-23} = 0b111011001;
2628 let Inst{22} = regs{8};
2629 let Inst{21-16} = 0b011111;
2630 let Inst{15-12} = regs{12-9};
2631 let Inst{11-8} = 0b1010;
2632 let Inst{7-0} = regs{7-0};
2633
2634 let DecoderMethod = "DecodeVSCCLRM";
2635
2636 list Predicates = [HasV8_1MMainline, Has8MSecExt];
2637 }
2638
2639 //===----------------------------------------------------------------------===//
2640 // Store VFP System Register to memory.
2641 //
2642
2643 class vfp_vstrldr SysReg, string sysreg,
2644 dag oops, dag iops, IndexMode im, string Dest, string cstr>
2645 : VFPI
2646 !if(opc,"vldr","vstr"), !strconcat("\t", sysreg, ", ", Dest), cstr, []>,
2647 Sched<[]> {
2648 bits<12> addr;
2649 let Inst{27-25} = 0b110;
2650 let Inst{24} = P;
2651 let Inst{23} = addr{7};
2652 let Inst{22} = SysReg{3};
2653 let Inst{21} = W;
2654 let Inst{20} = opc;
2655 let Inst{19-16} = addr{11-8};
2656 let Inst{15-13} = SysReg{2-0};
2657 let Inst{12-7} = 0b011111;
2658 let Inst{6-0} = addr{6-0};
2659 list Predicates = [HasFPRegs, HasV8_1MMainline];
2660 let mayLoad = opc;
2661 let mayStore = !if(opc, 0b0, 0b1);
2662 let hasSideEffects = 1;
2663 }
2664
2665 multiclass vfp_vstrldr_sysreg SysReg, string sysreg,
2666 dag oops=(outs), dag iops=(ins)> {
2667 def _off :
2668 vfp_vstrldr
2669 oops, !con(iops, (ins t2addrmode_imm7s4:$addr)),
2670 IndexModePost, "$addr", "" > {
2671 let DecoderMethod = "DecodeVSTRVLDR_SYSREG";
2672 }
2673
2674 def _pre :
2675 vfp_vstrldr
2676 !con(oops, (outs GPRnopc:$wb)),
2677 !con(iops, (ins t2addrmode_imm7s4_pre:$addr)),
2678 IndexModePre, "$addr!", "$addr.base = $wb"> {
2679 let DecoderMethod = "DecodeVSTRVLDR_SYSREG";
2680 }
2681
2682 def _post :
2683 vfp_vstrldr
2684 !con(oops, (outs GPRnopc:$wb)),
2685 !con(iops, (ins t2_addr_offset_none:$Rn,
2686 t2am_imm7s4_offset:$addr)),
2687 IndexModePost, "$Rn$addr", "$Rn.base = $wb"> {
2688 bits<4> Rn;
2689 let Inst{19-16} = Rn{3-0};
2690 let DecoderMethod = "DecodeVSTRVLDR_SYSREG";
2691 }
2692 }
2693
2694 let Defs = [FPSCR] in {
2695 defm VSTR_FPSCR : vfp_vstrldr_sysreg<0b0,0b0001, "fpscr">;
2696 defm VSTR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b0,0b0010, "fpscr_nzcvqc">;
2697
2698 let Predicates = [HasV8_1MMainline, Has8MSecExt] in {
2699 defm VSTR_FPCXTNS : vfp_vstrldr_sysreg<0b0,0b1110, "fpcxtns">;
2700 defm VSTR_FPCXTS : vfp_vstrldr_sysreg<0b0,0b1111, "fpcxts">;
2701 }
2702 }
2703
2704 let Predicates = [HasV8_1MMainline, HasMVEInt] in {
2705 let Uses = [VPR] in {
2706 defm VSTR_VPR : vfp_vstrldr_sysreg<0b0,0b1100, "vpr">;
2707 }
2708 defm VSTR_P0 : vfp_vstrldr_sysreg<0b0,0b1101, "p0",
2709 (outs), (ins VCCR:$P0)>;
2710 }
2711
2712 let Uses = [FPSCR] in {
2713 defm VLDR_FPSCR : vfp_vstrldr_sysreg<0b1,0b0001, "fpscr">;
2714 defm VLDR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b1,0b0010, "fpscr_nzcvqc">;
2715
2716 let Predicates = [HasV8_1MMainline, Has8MSecExt] in {
2717 defm VLDR_FPCXTNS : vfp_vstrldr_sysreg<0b1,0b1110, "fpcxtns">;
2718 defm VLDR_FPCXTS : vfp_vstrldr_sysreg<0b1,0b1111, "fpcxts">;
2719 }
2720 }
2721
2722 let Predicates = [HasV8_1MMainline, HasMVEInt] in {
2723 let Defs = [VPR] in {
2724 defm VLDR_VPR : vfp_vstrldr_sysreg<0b1,0b1100, "vpr">;
2725 }
2726 defm VLDR_P0 : vfp_vstrldr_sysreg<0b1,0b1101, "p0",
2727 (outs VCCR:$P0), (ins)>;
2728 }
9494 AssemblerPredicate<"FeatureCRC", "crc">;
9595 def HasRAS : Predicate<"Subtarget->hasRAS()">,
9696 AssemblerPredicate<"FeatureRAS", "ras">;
97 def HasLOB : Predicate<"Subtarget->hasLOB()">,
98 AssemblerPredicate<"FeatureLOB", "lob">;
9997 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
10098 AssemblerPredicate<"FeatureFP16","half-float conversions">;
10199 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
196196 def FPEXC : ARMReg<8, "fpexc">;
197197 def FPINST : ARMReg<9, "fpinst">;
198198 def FPINST2 : ARMReg<10, "fpinst2">;
199 // These encodings aren't actual instruction encodings, their encoding depends
200 // on the instruction they are used in and for VPR 32 was chosen such that it
201 // always comes last in spr_reglist_with_vpr.
202 def VPR : ARMReg<32, "vpr">;
203 def FPSCR_NZCVQC
204 : ARMReg<2, "fpscr_nzcvqc">;
205 def P0 : ARMReg<13, "p0">;
206 def FPCXTNS : ARMReg<14, "fpcxtns">;
207 def FPCXTS : ARMReg<15, "fpcxts">;
208
209 def ZR : ARMReg<15, "zr">, DwarfRegNum<[15]>;
210199
211200 // Register classes.
212201 //
255244 let DiagnosticString = "operand must be a register in range [r0, r14] or apsr_nzcv";
256245 }
257246
258 // GPRs without the PC and SP registers but with APSR. Used by CLRM instruction.
259 def GPRwithAPSRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR)> {
260 let isAllocatable = 0;
261 }
262
263 def GPRwithZR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
264 LR, ZR)> {
265
266 let AltOrders = [(add LR, GPRwithZR), (trunc GPRwithZR, 8)];
267 let AltOrderSelect = [{
268 return 1 + MF.getSubtarget().isThumb1Only();
269 }];
270 let DiagnosticString = "operand must be a register in range [r0, r12] or r14 or zr";
271 }
272
273247 // GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the
274248 // implied SP argument list.
275249 // FIXME: It would be better to not use this at all and refactor the
279253 let DiagnosticString = "operand must be a register sp";
280254 }
281255
282 // GPRlr - Only LR is legal. Used by ARMv8.1-M Low Overhead Loop instructions
283 // where LR is the only legal loop counter register.
284 def GPRlr : RegisterClass<"ARM", [i32], 32, (add LR)>;
285
286256 // restricted GPR register class. Many Thumb2 instructions allow the full
287257 // register range for operands, but have undefined behaviours when PC
288258 // or SP (R13 or R15) are used. The ARM ISA refers to these operands
295265 let DiagnosticType = "rGPR";
296266 }
297267
298 // t2rGPR : All Thumb 2 registers with the exception of SP and PC.
299 def t2rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
300 let AltOrders = [(add LR, t2rGPR), (trunc t2rGPR, 8)];
301 let AltOrderSelect = [{
302 return 1 + MF.getSubtarget().isThumb1Only();
303 }];
304 let DiagnosticType = "rGPR";
305 }
306
307268 // Thumb registers are R0-R7 normally. Some instructions can still use
308269 // the general GPR register class above (MOV, e.g.)
309270 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)> {
335296 let CopyCost = -1; // Don't allow copying of status registers.
336297 let isAllocatable = 0;
337298 }
338
339 // MVE Condition code register.
340 def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1], 32, (add VPR)> {
341 // let CopyCost = -1; // Don't allow copying of status registers.
342 }
343
344 // FPSCR, when the flags at the top of it are used as the input or
345 // output to an instruction such as MVE VADC.
346 def cl_FPSCR_NZCV : RegisterClass<"ARM", [i32], 32, (add FPSCR_NZCV)>;
347299
348300 // Scalar single precision floating point register class..
349301 // FIXME: Allocation order changed to s0, s2, ... or s0, s4, ... as a quick hack
395347 let DiagnosticType = "DPR";
396348 }
397349
398 // Scalar single and double precision floating point and VPR register class,
399 // this is only used for parsing, don't use it anywhere else as the size and
400 // types don't match!
401 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
402 let isAllocatable = 0;
403 }
404
405350 // Subset of DPR that are accessible with VFP2 (and so that also have
406351 // 32-bit SPR subregs).
407352 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64,
9393
9494 // FIXME: Remove when all errors have been fixed.
9595 let FullInstRWOverlapCheck = 0;
96
97 let UnsupportedFeatures = [HasV8_1MMainline, HasMVEInt, HasMVEFloat,
98 HasFPRegsV8_1M];
9996 }
10097
10198 //===----------------------------------------------------------------------===//
342342 /// HasRAS - if true, the processor supports RAS extensions
343343 bool HasRAS = false;
344344
345 /// HasLOB - if true, the processor supports the Low Overhead Branch extension
346 bool HasLOB = false;
347
348345 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
349346 /// particularly effective at zeroing a VFP register.
350347 bool HasZeroCycleZeroing = false;
610607 bool hasDotProd() const { return HasDotProd; }
611608 bool hasCRC() const { return HasCRC; }
612609 bool hasRAS() const { return HasRAS; }
613 bool hasLOB() const { return HasLOB; }
614610 bool hasVirtualization() const { return HasVirtualization; }
615611
616612 bool useNEONForSinglePrecisionFP() const {
383383 int tryParseRegister();
384384 bool tryParseRegisterWithWriteBack(OperandVector &);
385385 int tryParseShiftRegister(OperandVector &);
386 bool parseRegisterList(OperandVector &, bool EnforceOrder = true);
386 bool parseRegisterList(OperandVector &);
387387 bool parseMemory(OperandVector &);
388388 bool parseOperand(OperandVector &, StringRef Mnemonic);
389389 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
478478 bool hasV8MMainline() const {
479479 return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
480480 }
481 bool hasV8_1MMainline() const {
482 return getSTI().getFeatureBits()[ARM::HasV8_1MMainlineOps];
483 }
481
484482 bool has8MSecExt() const {
485483 return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
486484 }
661659 k_VectorIndex,
662660 k_Register,
663661 k_RegisterList,
664 k_RegisterListWithAPSR,
665662 k_DPRRegisterList,
666663 k_SPRRegisterList,
667 k_FPSRegisterListWithVPR,
668 k_FPDRegisterListWithVPR,
669664 k_VectorList,
670665 k_VectorListAllLanes,
671666 k_VectorListIndexed,
866861 }
867862
868863 const SmallVectorImpl &getRegList() const {
869 assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||
870 Kind == k_DPRRegisterList || Kind == k_SPRRegisterList ||
871 Kind == k_FPSRegisterListWithVPR ||
872 Kind == k_FPDRegisterListWithVPR) &&
873 "Invalid access!");
864 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
865 Kind == k_SPRRegisterList) && "Invalid access!");
874866 return Registers;
875867 }
876868
10341026 bool isImm8s4() const {
10351027 return isImmediateS4<-1020, 1020>();
10361028 }
1037 bool isImm7s4() const {
1038 return isImmediateS4<-508, 508>();
1039 }
10401029 bool isImm0_1020s4() const {
10411030 return isImmediateS4<0, 1020>();
10421031 }
11781167
11791168 bool isReg() const override { return Kind == k_Register; }
11801169 bool isRegList() const { return Kind == k_RegisterList; }
1181 bool isRegListWithAPSR() const {
1182 return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList;
1183 }
11841170 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
11851171 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1186 bool isFPSRegListWithVPR() const { return Kind == k_FPSRegisterListWithVPR; }
1187 bool isFPDRegListWithVPR() const { return Kind == k_FPDRegisterListWithVPR; }
11881172 bool isToken() const override { return Kind == k_Token; }
11891173 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
11901174 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
12611245 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
12621246 if (!isMem())
12631247 return false;
1264 // No offset of any kind.
1265 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1266 (alignOK || Memory.Alignment == Alignment);
1267 }
1268 bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const {
1269 if (!isMem())
1270 return false;
1271
1272 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1273 Memory.BaseRegNum))
1274 return false;
1275
1276 // No offset of any kind.
1277 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1278 (alignOK || Memory.Alignment == Alignment);
1279 }
1280 bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const {
1281 if (!isMem())
1282 return false;
1283
1284 if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(
1285 Memory.BaseRegNum))
1286 return false;
1287
12881248 // No offset of any kind.
12891249 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
12901250 (alignOK || Memory.Alignment == Alignment);
15601520 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
15611521 Val == std::numeric_limits::min();
15621522 }
1563 bool isMemImm7s4Offset() const {
1564 // If we have an immediate that's not a constant, treat it as a label
1565 // reference needing a fixup. If it is a constant, it's something else
1566 // and we reject it.
1567 if (isImm() && !isa(getImm()))
1568 return true;
1569 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1570 !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1571 Memory.BaseRegNum))
1572 return false;
1573 // Immediate offset a multiple of 4 in range [-508, 508].
1574 if (!Memory.OffsetImm) return true;
1575 int64_t Val = Memory.OffsetImm->getValue();
1576 // Special case, #-0 is INT32_MIN.
1577 return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN;
1578 }
1523
15791524 bool isMemImm0_1020s4Offset() const {
15801525 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
15811526 return false;
20471992 return (Value % Angle == Remainder && Value <= 270);
20481993 }
20491994
2050 bool isITCondCodeNoAL() const {
2051 if (!isITCondCode()) return false;
2052 auto CC = (ARMCC::CondCodes) getCondCode();
2053 return CC != ARMCC::AL;
2054 }
2055
20561995 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
20571996 // Add as immediates when possible. Null MCExpr = 0.
20581997 if (!Expr)
21032042 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
21042043 assert(N == 1 && "Invalid number of operands!");
21052044 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2106 }
2107
2108 void addITCondCodeInvOperands(MCInst &Inst, unsigned N) const {
2109 assert(N == 1 && "Invalid number of operands!");
2110 Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode()))));
21112045 }
21122046
21132047 void addCCOutOperands(MCInst &Inst, unsigned N) const {
21552089 Inst.addOperand(MCOperand::createReg(*I));
21562090 }
21572091
2158 void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const {
2159 assert(N == 1 && "Invalid number of operands!");
2160 const SmallVectorImpl &RegList = getRegList();
2161 for (SmallVectorImpl::const_iterator
2162 I = RegList.begin(), E = RegList.end(); I != E; ++I)
2163 Inst.addOperand(MCOperand::createReg(*I));
2164 }
2165
21662092 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
21672093 addRegListOperands(Inst, N);
21682094 }
21692095
21702096 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2171 addRegListOperands(Inst, N);
2172 }
2173
2174 void addFPSRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2175 addRegListOperands(Inst, N);
2176 }
2177
2178 void addFPDRegListWithVPROperands(MCInst &Inst, unsigned N) const {
21792097 addRegListOperands(Inst, N);
21802098 }
21812099
22662184 Inst.addOperand(MCOperand::createImm(CE->getValue()));
22672185 }
22682186
2269 void addImm7s4Operands(MCInst &Inst, unsigned N) const {
2270 assert(N == 1 && "Invalid number of operands!");
2271 // FIXME: We really want to scale the value here, but the VSTR/VLDR_VSYSR
2272 // instruction don't encode operands that way yet.
2273 const MCConstantExpr *CE = dyn_cast(getImm());
2274 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2275 }
2276
22772187 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
22782188 assert(N == 1 && "Invalid number of operands!");
22792189 // The immediate is scaled by four in the encoding and is stored
24042314 }
24052315
24062316 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2407 assert(N == 1 && "Invalid number of operands!");
2408 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2409 }
2410
2411 void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const {
24122317 assert(N == 1 && "Invalid number of operands!");
24132318 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
24142319 }
26302535 Inst.addOperand(MCOperand::createImm(Val));
26312536 }
26322537
2633 void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const {
2634 assert(N == 2 && "Invalid number of operands!");
2635 // If we have an immediate that's not a constant, treat it as a label
2636 // reference needing a fixup. If it is a constant, it's something else
2637 // and we reject it.
2638 if (isImm()) {
2639 Inst.addOperand(MCOperand::createExpr(getImm()));
2640 Inst.addOperand(MCOperand::createImm(0));
2641 return;
2642 }
2643
2644 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2645 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2646 Inst.addOperand(MCOperand::createImm(Val));
2647 }
2648
26492538 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
26502539 assert(N == 2 && "Invalid number of operands!");
26512540 // The lower two bits are always zero and as such are not encoded.
31553044 assert(Regs.size() > 0 && "RegList contains no registers?");
31563045 KindTy Kind = k_RegisterList;
31573046
3158 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
3159 Regs.front().second)) {
3160 if (Regs.back().second == ARM::VPR)
3161 Kind = k_FPDRegisterListWithVPR;
3162 else
3163 Kind = k_DPRRegisterList;
3164 } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
3165 Regs.front().second)) {
3166 if (Regs.back().second == ARM::VPR)
3167 Kind = k_FPSRegisterListWithVPR;
3168 else
3169 Kind = k_SPRRegisterList;
3170 }
3047 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
3048 Kind = k_DPRRegisterList;
3049 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
3050 contains(Regs.front().second))
3051 Kind = k_SPRRegisterList;
31713052
31723053 // Sort based on the register encoding values.
31733054 array_pod_sort(Regs.begin(), Regs.end());
3174
3175 if (Kind == k_RegisterList && Regs.back().second == ARM::APSR)
3176 Kind = k_RegisterListWithAPSR;
31773055
31783056 auto Op = make_unique(Kind);
31793057 for (SmallVectorImpl>::const_iterator
31803058 I = Regs.begin(), E = Regs.end(); I != E; ++I)
31813059 Op->Registers.push_back(I->second);
3182
31833060 Op->StartLoc = StartLoc;
31843061 Op->EndLoc = EndLoc;
31853062 return Op;
34473324 << ", width: " << Bitfield.Width << ">";
34483325 break;
34493326 case k_RegisterList:
3450 case k_RegisterListWithAPSR:
34513327 case k_DPRRegisterList:
3452 case k_SPRRegisterList:
3453 case k_FPSRegisterListWithVPR:
3454 case k_FPDRegisterListWithVPR: {
3328 case k_SPRRegisterList: {
34553329 OS << "
34563330
34573331 const SmallVectorImpl &RegList = getRegList();
38783752 }
38793753
38803754 /// Parse a register list.
3881 bool ARMAsmParser::parseRegisterList(OperandVector &Operands,
3882 bool EnforceOrder) {
3755 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
38833756 MCAsmParser &Parser = getParser();
38843757 if (Parser.getTok().isNot(AsmToken::LCurly))
38853758 return TokError("Token is not a Left Curly Brace");
39123785 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
39133786 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
39143787 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3915 else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
3916 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
39173788 else
39183789 return Error(RegLoc, "invalid register in register list");
39193790
39673838 Reg = getDRegFromQReg(Reg);
39683839 isQReg = true;
39693840 }
3970 if (!RC->contains(Reg) &&
3971 RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() &&
3972 ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) {
3973 // switch the register classes, as GPRwithAPSRnospRegClassID is a partial
3974 // subset of GPRRegClassId except it contains APSR as well.
3975 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
3976 }
3977 if (Reg == ARM::VPR && (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] ||
3978 RC == &ARMMCRegisterClasses[ARM::DPRRegClassID])) {
3979 RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID];
3980 EReg = MRI->getEncodingValue(Reg);
3981 Registers.push_back(std::pair(EReg, Reg));
3982 continue;
3983 }
39843841 // The register must be in the same register class as the first.
39853842 if (!RC->contains(Reg))
39863843 return Error(RegLoc, "invalid register in register list");
3987 // In most cases, the list must be monotonically increasing. An
3988 // exception is CLRM, which is order-independent anyway, so
3989 // there's no potential for confusion if you write clrm {r2,r1}
3990 // instead of clrm {r1,r2}.
3991 if (EnforceOrder &&
3992 MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3844 // List must be monotonically increasing.
3845 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
39933846 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
39943847 Warning(RegLoc, "register list not in ascending order");
3995 else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
3848 else
39963849 return Error(RegLoc, "register list not in ascending order");
39973850 }
39983851 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
40023855 }
40033856 // VFP register lists must also be contiguous.
40043857 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
4005 RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] &&
40063858 Reg != OldReg + 1)
40073859 return Error(RegLoc, "non-contiguous register range");
40083860 EReg = MRI->getEncodingValue(Reg);
56115463 case AsmToken::LBrac:
56125464 return parseMemory(Operands);
56135465 case AsmToken::LCurly:
5614 return parseRegisterList(Operands, !Mnemonic.startswith("clr"));
5466 return parseRegisterList(Operands);
56155467 case AsmToken::Dollar:
56165468 case AsmToken::Hash:
56175469 // #42 -> immediate.
58005652 Mnemonic == "bxns" || Mnemonic == "blxns" ||
58015653 Mnemonic == "vudot" || Mnemonic == "vsdot" ||
58025654 Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
5803 Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
5804 Mnemonic == "wls" || Mnemonic == "le" || Mnemonic == "dls" ||
5805 Mnemonic == "csel" || Mnemonic == "csinc" ||
5806 Mnemonic == "csinv" || Mnemonic == "csneg" || Mnemonic == "cinc" ||
5807 Mnemonic == "cinv" || Mnemonic == "cneg" || Mnemonic == "cset" ||
5808 Mnemonic == "csetm")
5655 Mnemonic == "vfmal" || Mnemonic == "vfmsl")
58095656 return Mnemonic;
58105657
58115658 // First, split out any predication code. Ignore mnemonics we know aren't
58985745 Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
58995746 Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
59005747 Mnemonic == "sb" || Mnemonic == "ssbb" ||
5901 Mnemonic == "pssbb" ||
5902 Mnemonic == "bfcsel" || Mnemonic == "wls" ||
5903 Mnemonic == "dls" || Mnemonic == "le" || Mnemonic == "csel" ||
5904 Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" ||
5905 Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" ||
5906 Mnemonic == "cset" || Mnemonic == "csetm") {
5748 Mnemonic == "pssbb") {
59075749 // These mnemonics are never predicable
59085750 CanAcceptPredicationCode = false;
59095751 } else if (!isThumb()) {
66356477 } else if (isThumbTwo() && MCID.isPredicable() &&
66366478 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
66376479 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
6638 Inst.getOpcode() != ARM::t2Bcc &&
6639 Inst.getOpcode() != ARM::t2BFic) {
6480 Inst.getOpcode() != ARM::t2Bcc) {
66406481 return Error(Loc, "predicated instructions must be in IT block");
66416482 } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() &&
66426483 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
70326873 return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
70336874 "predicable, but condition "
70346875 "code specified");
7035 break;
7036 }
7037 case ARM::t2WLS: {
7038 int idx = Opcode == ARM::t2WLS ? 3 : 4;
7039 if (!static_cast(*Operands[idx]).isUnsignedOffset<11, 1>())
7040 return Error(Operands[idx]->getStartLoc(),
7041 "loop end is out of range or not a positive multiple of 2");
7042 break;
7043 }
7044 case ARM::t2LEUpdate: {
7045 if (Inst.getOperand(2).isImm() &&
7046 !(Inst.getOperand(2).getImm() < 0 &&
7047 Inst.getOperand(2).getImm() >= -4094 &&
7048 (Inst.getOperand(2).getImm() & 1) == 0))
7049 return Error(Operands[2]->getStartLoc(),
7050 "loop start is out of range or not a negative multiple of 2");
7051 break;
7052 }
7053 case ARM::t2BFi:
7054 case ARM::t2BFr:
7055 case ARM::t2BFLi:
7056 case ARM::t2BFLr: {
7057 if (!static_cast(*Operands[2]).isUnsignedOffset<4, 1>() ||
7058 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
7059 return Error(Operands[2]->getStartLoc(),
7060 "branch location out of range or not a multiple of 2");
7061
7062 if (Opcode == ARM::t2BFi) {
7063 if (!static_cast(*Operands[3]).isSignedOffset<16, 1>())
7064 return Error(Operands[3]->getStartLoc(),
7065 "branch target out of range or not a multiple of 2");
7066 } else if (Opcode == ARM::t2BFLi) {
7067 if (!static_cast(*Operands[3]).isSignedOffset<18, 1>())
7068 return Error(Operands[3]->getStartLoc(),
7069 "branch target out of range or not a multiple of 2");
7070 }
7071 break;
7072 }
7073 case ARM::t2BFic: {
7074 if (!static_cast(*Operands[1]).isUnsignedOffset<4, 1>() ||
7075 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
7076 return Error(Operands[1]->getStartLoc(),
7077 "branch location out of range or not a multiple of 2");
7078
7079 if (!static_cast(*Operands[2]).isSignedOffset<16, 1>())
7080 return Error(Operands[2]->getStartLoc(),
7081 "branch target out of range or not a multiple of 2");
7082
7083 assert(Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() &&
7084 "branch location and else branch target should either both be "
7085 "immediates or both labels");
7086
7087 if (Inst.getOperand(0).isImm() && Inst.getOperand(2).isImm()) {
7088 int Diff = Inst.getOperand(2).getImm() - Inst.getOperand(0).getImm();
7089 if (Diff != 4 && Diff != 2)
7090 return Error(
7091 Operands[3]->getStartLoc(),
7092 "else branch target must be 2 or 4 greater than the branch location");
7093 }
7094 break;
7095 }
7096 case ARM::t2CLRM: {
7097 for (unsigned i = 2; i < Inst.getNumOperands(); i++) {
7098 if (Inst.getOperand(i).isReg() &&
7099 !ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(
7100 Inst.getOperand(i).getReg())) {
7101 return Error(Operands[2]->getStartLoc(),
7102 "invalid register in register list. Valid registers are "
7103 "r0-r12, lr/r14 and APSR.");
7104 }
7105 }
71066876 break;
71076877 }
71086878 case ARM::DSB:
93989168 return Match_RequiresV8;
93999169 }
94009170
9401 switch (Inst.getOpcode()) {
9402 case ARM::VMRS:
9403 case ARM::VMSR:
9404 case ARM::VMRS_FPCXTS:
9405 case ARM::VMRS_FPCXTNS:
9406 case ARM::VMSR_FPCXTS:
9407 case ARM::VMSR_FPCXTNS:
9408 case ARM::VMRS_FPSCR_NZCVQC:
9409 case ARM::VMSR_FPSCR_NZCVQC:
9410 case ARM::FMSTAT:
9411 case ARM::VMRS_VPR:
9412 case ARM::VMRS_P0:
9413 case ARM::VMSR_VPR:
9414 case ARM::VMSR_P0:
9415 // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of
9416 // ARMv8-A.
9417 if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP &&
9418 (isThumb() && !hasV8Ops()))
9419 return Match_InvalidOperand;
9420 break;
9421 default:
9422 break;
9423 }
9171 // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of
9172 // ARMv8-A.
9173 if ((Inst.getOpcode() == ARM::VMRS || Inst.getOpcode() == ARM::VMSR) &&
9174 Inst.getOperand(0).getReg() == ARM::SP && (isThumb() && !hasV8Ops()))
9175 return Match_InvalidOperand;
94249176
94259177 for (unsigned I = 0; I < MCID.NumOperands; ++I)
94269178 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
1088310635 { ARM::AEK_FP16, {Feature_HasV8_2aBit},
1088410636 {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} },
1088510637 { ARM::AEK_RAS, {Feature_HasV8Bit}, {ARM::FeatureRAS} },
10886 { ARM::AEK_LOB, {Feature_HasV8_1MMainlineBit}, {ARM::FeatureLOB} },
1088710638 // FIXME: Unsupported extensions.
1088810639 { ARM::AEK_OS, {}, {} },
1088910640 { ARM::AEK_IWMMXT, {}, {} },
143143 // Definitions are further down.
144144 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
145145 uint64_t Address, const void *Decoder);
146 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
147 uint64_t Address, const void *Decoder);
148146 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
149147 unsigned RegNo, uint64_t Address,
150148 const void *Decoder);
151149 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
152 unsigned RegNo, uint64_t Address,
153 const void *Decoder);
154 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst,
155150 unsigned RegNo, uint64_t Address,
156151 const void *Decoder);
157152 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
365360 uint64_t Address, const void* Decoder);
366361 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
367362 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val,
369 uint64_t Address, const void *Decoder);
370363 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
371364 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
373 uint64_t Address,
374 const void *Decoder);
375365 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
376366 uint64_t Address, const void *Decoder);
377367 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
420410 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
421411 uint64_t Address, const void *Decoder);
422412
423 template
424 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
425 uint64_t Address, const void *Decoder);
426 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
427 uint64_t Address,
428 const void *Decoder);
429 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
430 uint64_t Address,
431 const void *Decoder);
432 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
433 const void *Decoder);
434 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
435 const void *Decoder);
436 template
437 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
438 uint64_t Address,
439 const void *Decoder);
440413 #include "ARMGenDisassemblerTables.inc"
441414
442415 static MCDisassembler *createARMDisassembler(const Target &T,
630603 case ARM::t2CPS3p:
631604 case ARM::t2CPS2p:
632605 case ARM::t2CPS1p:
633 case ARM::t2CSEL:
634 case ARM::t2CSINC:
635 case ARM::t2CSINV:
636 case ARM::t2CSNEG:
637606 case ARM::tMOVSr:
638607 case ARM::tSETEND:
639608 // Some instructions (mostly conditional branches) are not
922891 ARM::R12, ARM::SP, ARM::LR, ARM::PC
923892 };
924893
925 static const uint16_t CLRMGPRDecoderTable[] = {
926 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
927 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
928 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
929 ARM::R12, 0, ARM::LR, ARM::APSR
930 };
931
932894 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
933895 uint64_t Address, const void *Decoder) {
934896 if (RegNo > 15)
935897 return MCDisassembler::Fail;
936898
937899 unsigned Register = GPRDecoderTable[RegNo];
938 Inst.addOperand(MCOperand::createReg(Register));
939 return MCDisassembler::Success;
940 }
941
942 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
943 uint64_t Address,
944 const void *Decoder) {
945 if (RegNo > 15)
946 return MCDisassembler::Fail;
947
948 unsigned Register = CLRMGPRDecoderTable[RegNo];
949 if (Register == 0)
950 return MCDisassembler::Fail;
951
952900 Inst.addOperand(MCOperand::createReg(Register));
953901 return MCDisassembler::Success;
954902 }
976924 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
977925 return MCDisassembler::Success;
978926 }
979
980 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
981 return S;
982 }
983
984 static DecodeStatus
985 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
986 uint64_t Address, const void *Decoder) {
987 DecodeStatus S = MCDisassembler::Success;
988
989 if (RegNo == 15)
990 {
991 Inst.addOperand(MCOperand::createReg(ARM::ZR));
992 return MCDisassembler::Success;
993 }
994
995 if (RegNo == 13)
996 S = MCDisassembler::SoftFail;
997927
998928 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
999929 return S;
13081238
13091239 bool NeedDisjointWriteback = false;
13101240 unsigned WritebackReg = 0;
1311 bool CLRM = false;
13121241 switch (Inst.getOpcode()) {
13131242 default:
13141243 break;
13231252 NeedDisjointWriteback = true;
13241253 WritebackReg = Inst.getOperand(0).getReg();
13251254 break;
1326 case ARM::t2CLRM:
1327 CLRM = true;
1328 break;
13291255 }
13301256
13311257 // Empty register lists are not allowed.
13321258 if (Val == 0) return MCDisassembler::Fail;
13331259 for (unsigned i = 0; i < 16; ++i) {
13341260 if (Val & (1 << i)) {
1335 if (CLRM) {
1336 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
1337 return MCDisassembler::Fail;
1338 }
1339 } else {
1340 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1341 return MCDisassembler::Fail;
1342 // Writeback not allowed if Rn is in the target list.
1343 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1344 Check(S, MCDisassembler::SoftFail);
1345 }
1261 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1262 return MCDisassembler::Fail;
1263 // Writeback not allowed if Rn is in the target list.
1264 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1265 Check(S, MCDisassembler::SoftFail);
13461266 }
13471267 }
13481268
14351355 unsigned imm = fieldFromInstruction(Insn, 0, 8);
14361356 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
14371357 unsigned U = fieldFromInstruction(Insn, 23, 1);
1438 const FeatureBitset &featureBits =
1439 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
14401358
14411359 switch (Inst.getOpcode()) {
14421360 case ARM::LDC_OFFSET:
14711389 case ARM::t2STCL_PRE:
14721390 case ARM::t2STCL_POST:
14731391 case ARM::t2STCL_OPTION:
1474 case ARM::t2LDC2_OFFSET:
1475 case ARM::t2LDC2L_OFFSET:
1476 case ARM::t2LDC2_PRE:
1477 case ARM::t2LDC2L_PRE:
1478 case ARM::t2STC2_OFFSET:
1479 case ARM::t2STC2L_OFFSET:
1480 case ARM::t2STC2_PRE:
1481 case ARM::t2STC2L_PRE:
1482 case ARM::LDC2_OFFSET:
1483 case ARM::LDC2L_OFFSET:
1484 case ARM::LDC2_PRE:
1485 case ARM::LDC2L_PRE:
1486 case ARM::STC2_OFFSET:
1487 case ARM::STC2L_OFFSET:
1488 case ARM::STC2_PRE:
1489 case ARM::STC2L_PRE:
1490 case ARM::t2LDC2_OPTION:
1491 case ARM::t2STC2_OPTION:
1492 case ARM::t2LDC2_POST:
1493 case ARM::t2LDC2L_POST:
1494 case ARM::t2STC2_POST:
1495 case ARM::t2STC2L_POST:
1496 case ARM::LDC2_POST:
1497 case ARM::LDC2L_POST:
1498 case ARM::STC2_POST:
1499 case ARM::STC2L_POST:
1500 if (coproc == 0xA || coproc == 0xB ||
1501 (featureBits[ARM::HasV8_1MMainlineOps] &&
1502 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1503 coproc == 0xE || coproc == 0xF)))
1392 if (coproc == 0xA || coproc == 0xB)
15041393 return MCDisassembler::Fail;
15051394 break;
15061395 default:
15071396 break;
15081397 }
15091398
1399 const FeatureBitset &featureBits =
1400 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
15101401 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
15111402 return MCDisassembler::Fail;
15121403
38433734 return MCDisassembler::Success;
38443735 }
38453736
3846 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
3847 const void *Decoder) {
3848 if (Val == 0)
3849 Inst.addOperand(MCOperand::createImm(INT32_MIN));
3850 else {
3851 int imm = Val & 0x7F;
3852
3853 if (!(Val & 0x80))
3854 imm *= -1;
3855 Inst.addOperand(MCOperand::createImm(imm * 4));
3856 }
3857
3858 return MCDisassembler::Success;
3859 }
3860
38613737 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
38623738 uint64_t Address, const void *Decoder) {
38633739 DecodeStatus S = MCDisassembler::Success;
38683744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
38693745 return MCDisassembler::Fail;
38703746 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3871 return MCDisassembler::Fail;
3872
3873 return S;
3874 }
3875
3876 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
3877 uint64_t Address,
3878 const void *Decoder) {
3879 DecodeStatus S = MCDisassembler::Success;
3880
3881 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3882 unsigned imm = fieldFromInstruction(Val, 0, 8);
3883
3884 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3885 return MCDisassembler::Fail;
3886 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
38873747 return MCDisassembler::Fail;
38883748
38893749 return S;
41424002 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
41434003
41444004 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
4145 return MCDisassembler::Fail;
4146
4147 // For Armv8.1-M Mainline coprocessors matching 100x,101x or 111x should
4148 // decode as VFP/MVE instructions.
4149 if (featureBits[ARM::HasV8_1MMainlineOps] &&
4150 ((Val & 0xE) == 0x8 || (Val & 0xE) == 0xA ||
4151 (Val & 0xE) == 0xE))
41524005 return MCDisassembler::Fail;
41534006
41544007 Inst.addOperand(MCOperand::createImm(Val));
55165369 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
55175370 DecodeStatus S = MCDisassembler::Success;
55185371
5519 // Add explicit operand for the destination sysreg, for cases where
5520 // we have to model it for code generation purposes.
5521 switch (Inst.getOpcode()) {
5522 case ARM::VMSR_FPSCR_NZCVQC:
5523 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
5524 break;
5525 case ARM::VMSR_P0:
5526 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5527 break;
5528 }
5529
5530 if (Inst.getOpcode() != ARM::FMSTAT) {
5531 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5532
5533 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
5534 if (Rt == 13 || Rt == 15)
5535 S = MCDisassembler::SoftFail;
5536 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
5537 } else
5538 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
5539 }
5540
5541 // Add explicit operand for the source sysreg, similarly to above.
5542 switch (Inst.getOpcode()) {
5543 case ARM::VMRS_FPSCR_NZCVQC:
5544 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
5545 break;
5546 case ARM::VMRS_P0:
5547 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5548 break;
5549 }
5372 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5373
5374 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
5375 if (Rt == 13 || Rt == 15)
5376 S = MCDisassembler::SoftFail;
5377 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
5378 } else
5379 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
55505380
55515381 if (featureBits[ARM::ModeThumb]) {
55525382 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
55595389
55605390 return S;
55615391 }
5562
5563 template
5564 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
5565 uint64_t Address,
5566 const void *Decoder) {
5567 DecodeStatus S = MCDisassembler::Success;
5568 if (Val == 0)
5569 S = MCDisassembler::SoftFail;
5570
5571 uint64_t DecVal;
5572 if (isSigned)
5573 DecVal = SignExtend32(Val << 1);
5574 else
5575 DecVal = (Val << 1);
5576
5577 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst,
5578 Decoder))
5579 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal));
5580 return S;
5581 }
5582
5583 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val,
5584 uint64_t Address,
5585 const void *Decoder) {
5586
5587 uint64_t LocImm = Inst.getOperand(0).getImm();
5588 Val = LocImm + (2 << Val);
5589 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,
5590 Decoder))
5591 Inst.addOperand(MCOperand::createImm(Val));
5592 return MCDisassembler::Success;
5593 }
5594
5595 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
5596 uint64_t Address,
5597 const void *Decoder) {
5598 if (Val >= ARMCC::AL) // also exclude the non-condition NV
5599 return MCDisassembler::Fail;
5600 Inst.addOperand(MCOperand::createImm(Val));
5601 return MCDisassembler::Success;
5602 }
5603
5604 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
5605 const void *Decoder) {
5606 DecodeStatus S = MCDisassembler::Success;
5607
5608 unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
5609 fieldFromInstruction(Insn, 1, 10) << 1;
5610 switch (Inst.getOpcode()) {
5611 case ARM::t2LEUpdate:
5612 Inst.addOperand(MCOperand::createReg(ARM::LR));
5613 Inst.addOperand(MCOperand::createReg(ARM::LR));
5614 LLVM_FALLTHROUGH;
5615 case ARM::t2LE:
5616 if (!Check(S, DecodeBFLabelOperand(Inst, Imm, Address,
5617 Decoder)))
5618 return MCDisassembler::Fail;
5619 break;
5620 case ARM::t2WLS:
5621 Inst.addOperand(MCOperand::createReg(ARM::LR));
5622 if (!Check(S,
5623 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),
5624 Address, Decoder)) ||
5625 !Check(S, DecodeBFLabelOperand(Inst, Imm, Address,
5626 Decoder)))
5627 return MCDisassembler::Fail;
5628 break;
5629 case ARM::t2DLS:
5630 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5631 if (Rn == 0xF) {
5632 return MCDisassembler::Fail;
5633 } else {
5634 Inst.addOperand(MCOperand::createReg(ARM::LR));
5635 if (!Check(S, DecoderGPRRegisterClass(Inst,
5636 fieldFromInstruction(Insn, 16, 4),
5637 Address, Decoder)))
5638 return MCDisassembler::Fail;
5639 }
5640 break;
5641 }
5642 return S;
5643 }
5644
5645 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
5646 const void *Decoder) {
5647 DecodeStatus S = MCDisassembler::Success;
5648
5649 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
5650 Inst.addOperand(MCOperand::createReg(0));
5651 if (Inst.getOpcode() == ARM::VSCCLRMD) {
5652 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) |
5653 (fieldFromInstruction(Insn, 12, 4) << 8) |
5654 (fieldFromInstruction(Insn, 22, 1) << 12);
5655 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) {
5656 return MCDisassembler::Fail;
5657 }
5658 } else {
5659 unsigned reglist = fieldFromInstruction(Insn, 0, 8) |
5660 (fieldFromInstruction(Insn, 22, 1) << 8) |
5661 (fieldFromInstruction(Insn, 12, 4) << 9);
5662 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) {
5663 return MCDisassembler::Fail;
5664 }
5665 }
5666 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5667
5668 return S;
5669 }
5670
5671 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) {
5672 switch (Opcode) {
5673 case ARM::VSTR_P0_off:
5674 case ARM::VSTR_P0_pre:
5675 case ARM::VSTR_P0_post:
5676 case ARM::VLDR_P0_off:
5677 case ARM::VLDR_P0_pre:
5678 case ARM::VLDR_P0_post:
5679 return ARM::P0;
5680 default:
5681 return 0;
5682 }
5683 }
5684
5685 template
5686 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
5687 uint64_t Address,
5688 const void *Decoder) {
5689 switch (Inst.getOpcode()) {
5690 case ARM::VSTR_FPSCR_pre:
5691 case ARM::VSTR_FPSCR_NZCVQC_pre:
5692 case ARM::VLDR_FPSCR_pre:
5693 case ARM::VLDR_FPSCR_NZCVQC_pre:
5694 case ARM::VSTR_FPSCR_off:
5695 case ARM::VSTR_FPSCR_NZCVQC_off:
5696 case ARM::VLDR_FPSCR_off:
5697 case ARM::VLDR_FPSCR_NZCVQC_off:
5698 case ARM::VSTR_FPSCR_post:
5699 case ARM::VSTR_FPSCR_NZCVQC_post:
5700 case ARM::VLDR_FPSCR_post:
5701 case ARM::VLDR_FPSCR_NZCVQC_post:
5702 const FeatureBitset &featureBits =
5703 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5704
5705 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
5706 return MCDisassembler::Fail;
5707 }
5708
5709 DecodeStatus S = MCDisassembler::Success;
5710 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
5711 Inst.addOperand(MCOperand::createReg(Sysreg));
5712 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5713 unsigned addr = fieldFromInstruction(Val, 0, 7) |
5714 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
5715
5716 if (Writeback) {
5717 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5718 return MCDisassembler::Fail;
5719 }
5720 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
5721 return MCDisassembler::Fail;
5722
5723 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
5724 Inst.addOperand(MCOperand::createReg(0));
5725
5726 return S;
5727 }
2828 #include "llvm/MC/MCSectionMachO.h"
2929 #include "llvm/MC/MCSubtargetInfo.h"
3030 #include "llvm/MC/MCValue.h"
31 #include "llvm/MC/MCAsmLayout.h"
3231 #include "llvm/Support/Debug.h"
3332 #include "llvm/Support/EndianStream.h"
3433 #include "llvm/Support/ErrorHandling.h"
104103 {"fixup_t2_movw_lo16", 0, 20, 0},
105104 {"fixup_arm_mod_imm", 0, 12, 0},
106105 {"fixup_t2_so_imm", 0, 26, 0},
107 {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
108 {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
109 {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
110 {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
111 {"fixup_bfcsel_else_target", 0, 32, 0},
112 {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
113 {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}
114106 };
115107 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
116108 // This table *must* be in the order that the fixup_* kinds are defined in
162154 {"fixup_t2_movw_lo16", 12, 20, 0},
163155 {"fixup_arm_mod_imm", 20, 12, 0},
164156 {"fixup_t2_so_imm", 26, 6, 0},
165 {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
166 {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
167 {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
168 {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
169 {"fixup_bfcsel_else_target", 0, 32, 0},
170 {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
171 {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}
172157 };
173158
174159 if (Kind < FirstTargetFixupKind)
270255 return "will be converted to nop";
271256 break;
272257 }
273 case ARM::fixup_bf_branch: {
274 int64_t Offset = int64_t(Value) - 4;
275 if (Offset < 0 || Offset > 30)
276 return "out of range pc-relative fixup value";
277 break;
278 }
279 case ARM::fixup_bf_target: {
280 int64_t Offset = int64_t(Value) - 4;
281 if (Offset > 65534 || Offset < -65536)
282 return "out of range pc-relative fixup value";
283 break;
284 }
285 case ARM::fixup_bfl_target: {
286 int64_t Offset = int64_t(Value) - 4;
287 if (Offset > 262142 || Offset < -262144)
288 return "out of range pc-relative fixup value";
289 break;
290 }
291 case ARM::fixup_bfc_target: {
292 int64_t Offset = int64_t(Value) - 4;
293 if (Offset > 4094 || Offset < -4096)
294 return "out of range pc-relative fixup value";
295 break;
296 }
297 case ARM::fixup_bfcsel_else_target: {
298 if (Value != 2 && Value != 4)
299 return "out of range label-relative fixup value";
300 break;
301 }
302 case ARM::fixup_wls: {
303 uint64_t Offset = Value - 4;
304 if (Offset > 4094)
305 return "out of range pc-relative fixup value";
306 break;
307 }
308 case ARM::fixup_le: {
309 // The offset field in the LE and LETP instructions is an 11-bit
310 // value shifted left by 2 (i.e. 0,2,4,...,4094), and it is
311 // interpreted as a negative offset from the value read from pc,
312 // i.e. from instruction_address+4.
313 //
314 // So an LE instruction can in principle address the instruction
315 // immediately after itself, or (not very usefully) the address
316 // half way through the 4-byte LE.
317 uint64_t Offset = -Value + 4;
318 if (Offset > 4094)
319 return "out of range pc-relative fixup value";
320 break;
321 }
322
323258 default:
324259 llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!");
325260 }
824759 EncValue |= (Value & 0xff);
825760 return swapHalfWords(EncValue, Endian == support::little);
826761 }
827 case ARM::fixup_bf_branch: {
828 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
829 if (FixupDiagnostic) {
830 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
831 return 0;
832 }
833 uint32_t out = (((Value - 4) >> 1) & 0xf) << 23;
834 return swapHalfWords(out, Endian == support::little);
835 }
836 case ARM::fixup_bf_target:
837 case ARM::fixup_bfl_target:
838 case ARM::fixup_bfc_target: {
839 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
840 if (FixupDiagnostic) {
841 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
842 return 0;
843 }
844 uint32_t out = 0;
845 uint32_t HighBitMask = (Kind == ARM::fixup_bf_target ? 0xf800 :
846 Kind == ARM::fixup_bfl_target ? 0x3f800 : 0x800);
847 out |= (((Value - 4) >> 1) & 0x1) << 11;
848 out |= (((Value - 4) >> 1) & 0x7fe);
849 out |= (((Value - 4) >> 1) & HighBitMask) << 5;
850 return swapHalfWords(out, Endian == support::little);
851 }
852 case ARM::fixup_bfcsel_else_target: {
853 // If this is a fixup of a branch future's else target then it should be a
854 // constant MCExpr representing the distance between the branch targetted
855 // and the instruction after that same branch.
856 Value = Target.getConstant();
857
858 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
859 if (FixupDiagnostic) {
860 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
861 return 0;
862 }
863 uint32_t out = ((Value >> 2) & 1) << 17;
864 return swapHalfWords(out, Endian == support::little);
865 }
866 case ARM::fixup_wls:
867 case ARM::fixup_le: {
868 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
869 if (FixupDiagnostic) {
870 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
871 return 0;
872 }
873 uint64_t real_value = Value - 4;
874 uint32_t out = 0;
875 if (Kind == ARM::fixup_le)
876 real_value = -real_value;
877 out |= ((real_value >> 1) & 0x1) << 11;
878 out |= ((real_value >> 1) & 0x7fe);
879 return swapHalfWords(out, Endian == support::little);
880 }
881762 }
882763 }
883764
972853 case ARM::fixup_t2_movt_hi16:
973854 case ARM::fixup_t2_movw_lo16:
974855 case ARM::fixup_t2_so_imm:
975 case ARM::fixup_bf_branch:
976 case ARM::fixup_bf_target:
977 case ARM::fixup_bfl_target:
978 case ARM::fixup_bfc_target:
979 case ARM::fixup_bfcsel_else_target:
980 case ARM::fixup_wls:
981 case ARM::fixup_le:
982856 return 4;
983857
984858 case FK_SecRel_2:
1035909 case ARM::fixup_t2_movw_lo16:
1036910 case ARM::fixup_arm_mod_imm:
1037911 case ARM::fixup_t2_so_imm:
1038 case ARM::fixup_bf_branch:
1039 case ARM::fixup_bf_target:
1040 case ARM::fixup_bfl_target:
1041 case ARM::fixup_bfc_target:
1042 case ARM::fixup_bfcsel_else_target:
1043 case ARM::fixup_wls:
1044 case ARM::fixup_le:
1045912 // Instruction size is 4 bytes.
1046913 return 4;
1047914 }
136136 default:
137137 return ELF::R_ARM_THM_CALL;
138138 }
139 case ARM::fixup_bf_target:
140 return ELF::R_ARM_THM_BF16;
141 case ARM::fixup_bfc_target:
142 return ELF::R_ARM_THM_BF12;
143 case ARM::fixup_bfl_target:
144 return ELF::R_ARM_THM_BF18;
145139 }
146140 }
147141 switch ((unsigned)Fixup.getKind()) {
102102 // Fixup for Thumb2 8-bit rotated operand
103103 fixup_t2_so_imm,
104104
105 // Fixups for Branch Future.
106 fixup_bf_branch,
107 fixup_bf_target,
108 fixup_bfl_target,
109 fixup_bfc_target,
110 fixup_bfcsel_else_target,
111 fixup_wls,
112 fixup_le,
113
114105 // Marker
115106 LastTargetFixupKind,
116107 NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
770770 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
771771 const MCSubtargetInfo &STI,
772772 raw_ostream &O) {
773 if (MI->getOpcode() != ARM::t2CLRM) {
774 assert(std::is_sorted(MI->begin() + OpNum, MI->end(),
775 [&](const MCOperand &LHS, const MCOperand &RHS) {
776 return MRI.getEncodingValue(LHS.getReg()) <
777 MRI.getEncodingValue(RHS.getReg());
778 }));
779 }
773 assert(std::is_sorted(MI->begin() + OpNum, MI->end(),
774 [&](const MCOperand &LHS, const MCOperand &RHS) {
775 return MRI.getEncodingValue(LHS.getReg()) <
776 MRI.getEncodingValue(RHS.getReg());
777 }));
780778
781779 O << "{";
782780 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
931929 O << ARMCondCodeToString(CC);
932930 }
933931
934 void ARMInstPrinter::printMandatoryRestrictedPredicateOperand(
935 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
936 raw_ostream &O) {
937 if ((ARMCC::CondCodes)MI->getOperand(OpNum).getImm() == ARMCC::HS)
938 O << "cs";
939 else
940 printMandatoryPredicateOperand(MI, OpNum, STI, O);
941 }
942
943932 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
944933 unsigned OpNum,
945934 const MCSubtargetInfo &STI,
946935 raw_ostream &O) {
947936 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
948937 O << ARMCondCodeToString(CC);
949 }
950
951 void ARMInstPrinter::printMandatoryInvertedPredicateOperand(const MCInst *MI,
952 unsigned OpNum,
953 const MCSubtargetInfo &STI,
954 raw_ostream &O) {
955 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
956 O << ARMCondCodeToString(ARMCC::getOppositeCondition(CC));
957938 }
958939
959940 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
169169 void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum,
170170 const MCSubtargetInfo &STI,
171171 raw_ostream &O);
172 void printMandatoryRestrictedPredicateOperand(const MCInst *MI,
173 unsigned OpNum,
174 const MCSubtargetInfo &STI,
175 raw_ostream &O);
176 void printMandatoryInvertedPredicateOperand(const MCInst *MI, unsigned OpNum,
177 const MCSubtargetInfo &STI,
178 raw_ostream &O);
179172 void printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
180173 const MCSubtargetInfo &STI, raw_ostream &O);
181174 void printRegisterList(const MCInst *MI, unsigned OpNum,
4848
4949 class ARMMCCodeEmitter : public MCCodeEmitter {
5050 const MCInstrInfo &MCII;
51 MCContext &CTX;
51 const MCContext &CTX;
5252 bool IsLittleEndian;
5353
5454 public:
179179 SmallVectorImpl &Fixups,
180180 const MCSubtargetInfo &STI) const;
181181
182 /// getT2AddrModeImm7s4OpValue - Return encoding info for 'reg +/- imm7<<2'
183 /// operand.
184 uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
185 SmallVectorImpl &Fixups,
186 const MCSubtargetInfo &STI) const;
187
188182 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
189183 /// operand.
190184 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
191185 SmallVectorImpl &Fixups,
192186 const MCSubtargetInfo &STI) const;
193187
194 /// getT2ScaledImmOpValue - Return encoding info for '+/- immX<'
188 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
195189 /// operand.
196 template
197 uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
198 SmallVectorImpl &Fixups,
199 const MCSubtargetInfo &STI) const;
190 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
191 SmallVectorImpl &Fixups,
192 const MCSubtargetInfo &STI) const;
193
200194
201195 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
202196 /// operand as needed by load/store instructions.
421415 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
422416 SmallVectorImpl &Fixups,
423417 const MCSubtargetInfo &STI) const override;
424
425 template
426 uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
427 SmallVectorImpl &Fixups,
428 const MCSubtargetInfo &STI) const;
429
430 uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
431 SmallVectorImpl &Fixups,
432 const MCSubtargetInfo &STI) const;
433418 };
434419
435420 } // end anonymous namespace
908893 return Binary;
909894 }
910895
911 template
912 uint32_t ARMMCCodeEmitter::
913 getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
914 SmallVectorImpl &Fixups,
915 const MCSubtargetInfo &STI) const {
896 /// getT2Imm8s4OpValue - Return encoding info for
897 /// '+/- imm8<<2' operand.
898 uint32_t ARMMCCodeEmitter::
899 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
900 SmallVectorImpl &Fixups,
901 const MCSubtargetInfo &STI) const {
916902 // FIXME: The immediate operand should have already been encoded like this
917903 // before ever getting here. The encoder method should just need to combine
918904 // the MI operands for the register and the offset into a single
920906 // style, unfortunately. As-is, we can't represent the distinct encoding
921907 // for #-0.
922908
923 // {Bits} = (U)nsigned (add == '1', sub == '0')
924 // {(Bits-1)-0} = immediate
925 int32_t Imm = MI.getOperand(OpIdx).getImm();
926 bool isAdd = Imm >= 0;
909 // {8} = (U)nsigned (add == '1', sub == '0')
910 // {7-0} = imm8
911 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
912 bool isAdd = Imm8 >= 0;
927913
928914 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
929 if (Imm < 0)
930 Imm = -(uint32_t)Imm;
931
932 Imm >>= Shift;
933
934 uint32_t Binary = Imm & ((1U << Bits) - 1);
915 if (Imm8 < 0)
916 Imm8 = -(uint32_t)Imm8;
917
918 // Scaled by 4.
919 Imm8 /= 4;
920
921 uint32_t Binary = Imm8 & 0xff;
935922 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
936923 if (isAdd)
937 Binary |= (1U << Bits);
924 Binary |= (1 << 8);
938925 return Binary;
939926 }
927
940928 /// getT2AddrModeImm8s4OpValue - Return encoding info for
941929 /// 'reg +/- imm8<<2' operand.
942930 uint32_t ARMMCCodeEmitter::
975963 if (isAdd)
976964 Binary |= (1 << 8);
977965 Binary |= (Reg << 9);
978 return Binary;
979 }
980
981 /// getT2AddrModeImm7s4OpValue - Return encoding info for
982 /// 'reg +/- imm7<<2' operand.
983 uint32_t
984 ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
985 SmallVectorImpl &Fixups,
986 const MCSubtargetInfo &STI) const {
987 // {11-8} = reg
988 // {7} = (A)dd (add == '1', sub == '0')
989 // {6-0} = imm7
990 unsigned Reg, Imm7;
991 // If The first operand isn't a register, we have a label reference.
992 bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI);
993
994 // FIXME: The immediate operand should have already been encoded like this
995 // before ever getting here. The encoder method should just need to combine
996 // the MI operands for the register and the offset into a single
997 // representation for the complex operand in the .td file. This isn't just
998 // style, unfortunately. As-is, we can't represent the distinct encoding
999 // for #-0.
1000 uint32_t Binary = (Imm7 >> 2) & 0xff;
1001 // Immediate is always encoded as positive. The 'A' bit controls add vs sub.
1002 if (isAdd)
1003 Binary |= (1 << 7);
1004 Binary |= (Reg << 8);
1005966 return Binary;
1006967 }
1007968
15371498 getRegisterListOpValue(const MCInst &MI, unsigned Op,
15381499 SmallVectorImpl &Fixups,
15391500 const MCSubtargetInfo &STI) const {
1540 // VLDM/VSTM/VSCCLRM:
1501 // VLDM/VSTM:
15411502 // {12-8} = Vd
15421503 // {7-0} = Number of registers
15431504 //
15461507 unsigned Reg = MI.getOperand(Op).getReg();
15471508 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
15481509 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1549 bool CLRMRegs = MI.getOpcode() == ARM::t2CLRM;
15501510
15511511 unsigned Binary = 0;
15521512
15531513 if (SPRRegs || DPRRegs) {
1554 // VLDM/VSTM/VSCCLRM
1514 // VLDM/VSTM
15551515 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
15561516 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
15571517 Binary |= (RegNo & 0x1f) << 8;
1558
1559 // Ignore VPR
1560 if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS)
1561 --NumRegs;
15621518 if (SPRRegs)
15631519 Binary |= NumRegs;
15641520 else
15651521 Binary |= NumRegs * 2;
15661522 } else {
15671523 const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
1568 if (!CLRMRegs) {
1569 assert(std::is_sorted(MI.begin() + Op, MI.end(),
1570 [&](const MCOperand &LHS, const MCOperand &RHS) {
1571 return MRI.getEncodingValue(LHS.getReg()) <
1572 MRI.getEncodingValue(RHS.getReg());
1573 }));
1574 }
1524 assert(std::is_sorted(MI.begin() + Op, MI.end(),
1525 [&](const MCOperand &LHS, const MCOperand &RHS) {
1526 return MRI.getEncodingValue(LHS.getReg()) <
1527 MRI.getEncodingValue(RHS.getReg());
1528 }));
15751529
15761530 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1577 unsigned RegNo;
1578 if (CLRMRegs && MI.getOperand(I).getReg() == ARM::APSR) {
1579 RegNo = 15;
1580 } else {
1581 RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
1582 }
1531 unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
15831532 Binary |= 1 << RegNo;
15841533 }
15851534 }
17251674 ++MCNumEmitted; // Keep track of the # of mi's emitted.
17261675 }
17271676
1728 template
1729 uint32_t
1730 ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1731 SmallVectorImpl &Fixups,
1732 const MCSubtargetInfo &STI) const {
1733 const MCOperand MO = MI.getOperand(OpIdx);
1734 if (MO.isExpr())
1735 return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1736 return isNeg ? -(MO.getImm() >> 1) : (MO.getImm() >> 1);
1737 }
1738
1739 uint32_t
1740 ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1741 SmallVectorImpl &Fixups,
1742 const MCSubtargetInfo &STI) const {
1743 const MCOperand MO = MI.getOperand(OpIdx);
1744 const MCOperand BranchMO = MI.getOperand(0);
1745
1746 if (MO.isExpr()) {
1747 assert(BranchMO.isExpr());
1748 const MCExpr *DiffExpr = MCBinaryExpr::createSub(
1749 MO.getExpr(), BranchMO.getExpr(), CTX);
1750 MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target);
1751 Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc()));
1752 return 0;
1753 }
1754
1755 assert(MO.isImm() && BranchMO.isImm());
1756 int Diff = MO.getImm() - BranchMO.getImm();
1757 assert(Diff == 4 || Diff == 2);
1758
1759 return Diff == 4;
1760 }
17611677 #include "ARMGenMCCodeEmitter.inc"
17621678
17631679 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
276276 public:
277277 ThumbMCInstrAnalysis(const MCInstrInfo *Info) : ARMMCInstrAnalysis(Info) {}
278278
279 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
280 uint64_t &Target) const override {
281 unsigned OpId;
282 switch (Inst.getOpcode()) {
283 default:
284 OpId = 0;
285 break;
286 case ARM::t2WLS:
287 case ARM::t2LEUpdate:
288 OpId = 2;
289 break;
290 case ARM::t2LE:
291 OpId = 1;
292 break;
293 }
294
279 bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
280 uint64_t Size, uint64_t &Target) const override {
295281 // We only handle PCRel branches for now.
296 if (Info->get(Inst.getOpcode()).OpInfo[OpId].OperandType !=
297 MCOI::OPERAND_PCREL)
282 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
298283 return false;
299284
300 // In Thumb mode the PC is always off by 4 bytes.
301 Target = Addr + Inst.getOperand(OpId).getImm() + 4;
285 int64_t Imm = Inst.getOperand(0).getImm();
286 Target = Addr+Imm+4; // In Thumb mode the PC is always off by 4 bytes.
302287 return true;
303288 }
304289 };
160160 // otherwise).
161161 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
162162 MachineRegisterInfo *MRI = &MF.getRegInfo();
163 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_GPRwithAPSRnospRegClass);
163 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
164164 }
165165
166166 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
202202 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
203203 MachineRegisterInfo *MRI = &MF.getRegInfo();
204204 MRI->constrainRegClass(DestReg,
205 &ARM::GPRPair_with_gsub_1_in_GPRwithAPSRnospRegClass);
205 &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
206206 }
207207
208208 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
55
66 declare void @bar1()
77 define void @foo()#0 {
8 ; CHECK: foo Clobbered Registers: $apsr $apsr_nzcv $cpsr $fpcxtns $fpcxts $fpexc $fpinst $fpscr $fpscr_nzcv $fpscr_nzcvqc $fpsid $itstate $pc $sp $spsr $vpr $zr $d0 $d1 $d2 $d3 $d4 $d5 $d6 $d7 $d16 $d17 $d18 $d19 $d20 $d21 $d22 $d23 $d24 $d25 $d26 $d27 $d28 $d29 $d30 $d31 $fpinst2 $mvfr0 $mvfr1 $mvfr2 $p0 $q0 $q1 $q2 $q3 $q8 $q9 $q10 $q11 $q12 $q13 $q14 $q15 $r0 $r1 $r2 $r3 $r12 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $s8 $s9 $s10 $s11 $s12 $s13 $s14 $s15 $d0_d2 $d1_d3 $d2_d4 $d3_d5 $d4_d6 $d5_d7 $d6_d8 $d7_d9 $d14_d16 $d15_d17 $d16_d18 $d17_d19 $d18_d20 $d19_d21 $d20_d22 $d21_d23 $d22_d24 $d23_d25 $d24_d26 $d25_d27 $d26_d28 $d27_d29 $d28_d30 $d29_d31 $q0_q1 $q1_q2 $q2_q3 $q3_q4 $q7_q8 $q8_q9 $q9_q10 $q10_q11 $q11_q12 $q12_q13 $q13_q14 $q14_q15 $q0_q1_q2_q3 $q1_q2_q3_q4 $q2_q3_q4_q5 $q3_q4_q5_q6 $q5_q6_q7_q8 $q6_q7_q8_q9 $q7_q8_q9_q10 $q8_q9_q10_q11 $q9_q10_q11_q12 $q10_q11_q12_q13 $q11_q12_q13_q14 $q12_q13_q14_q15 $r12_sp $r0_r1 $r2_r3 $d0_d1_d2 $d1_d2_d3 $d2_d3_d4 $d3_d4_d5 $d4_d5_d6 $d5_d6_d7 $d6_d7_d8 $d7_d8_d9 $d14_d15_d16 $d15_d16_d17 $d16_d17_d18 $d17_d18_d19 $d18_d19_d20 $d19_d20_d21 $d20_d21_d22 $d21_d22_d23 $d22_d23_d24 $d23_d24_d25 $d24_d25_d26 $d25_d26_d27 $d26_d27_d28 $d27_d28_d29 $d28_d29_d30 $d29_d30_d31 $d0_d2_d4 $d1_d3_d5 $d2_d4_d6 $d3_d5_d7 $d4_d6_d8 $d5_d7_d9 $d6_d8_d10 $d7_d9_d11 $d12_d14_d16 $d13_d15_d17 $d14_d16_d18 $d15_d17_d19 $d16_d18_d20 $d17_d19_d21 $d18_d20_d22 $d19_d21_d23 $d20_d22_d24 $d21_d23_d25 $d22_d24_d26 $d23_d25_d27 $d24_d26_d28 $d25_d27_d29 $d26_d28_d30 $d27_d29_d31 $d0_d2_d4_d6 $d1_d3_d5_d7 $d2_d4_d6_d8 $d3_d5_d7_d9 $d4_d6_d8_d10 $d5_d7_d9_d11 $d6_d8_d10_d12 $d7_d9_d11_d13 $d10_d12_d14_d16 $d11_d13_d15_d17 $d12_d14_d16_d18 $d13_d15_d17_d19 $d14_d16_d18_d20 $d15_d17_d19_d21 $d16_d18_d20_d22 $d17_d19_d21_d23 $d18_d20_d22_d24 $d19_d21_d23_d25 $d20_d22_d24_d26 $d21_d23_d25_d27 $d22_d24_d26_d28 $d23_d25_d27_d29 $d24_d26_d28_d30 $d25_d27_d29_d31 $d1_d2 $d3_d4 $d5_d6 $d7_d8 $d15_d16 $d17_d18 $d19_d20 $d21_d22 $d23_d24 $d25_d26 $d27_d28 $d29_d30 $d1_d2_d3_d4 $d3_d4_d5_d6 $d5_d6_d7_d8 $d7_d8_d9_d10 $d13_d14_d15_d16 $d15_d16_d17_d18 $d17_d18_d19_d20 $d19_d20_d21_d22 $d21_d22_d23_d24 $d23_d24_d25_d26 $d25_d26_d27_d28 $d27_d28_d29_d30
8 ; CHECK: foo Clobbered Registers: $apsr $apsr_nzcv $cpsr $fpexc $fpinst $fpscr $fpscr_nzcv $fpsid $itstate $pc $sp $spsr $d0 $d1 $d2 $d3 $d4 $d5 $d6 $d7 $d16 $d17 $d18 $d19 $d20 $d21 $d22 $d23 $d24 $d25 $d26 $d27 $d28 $d29 $d30 $d31 $fpinst2 $mvfr0 $mvfr1 $mvfr2 $q0 $q1 $q2 $q3 $q8 $q9 $q10 $q11 $q12 $q13 $q14 $q15 $r0 $r1 $r2 $r3 $r12 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $s8 $s9 $s10 $s11 $s12 $s13 $s14 $s15 $d0_d2 $d1_d3 $d2_d4 $d3_d5 $d4_d6 $d5_d7 $d6_d8 $d7_d9 $d14_d16 $d15_d17 $d16_d18 $d17_d19 $d18_d20 $d19_d21 $d20_d22 $d21_d23 $d22_d24 $d23_d25 $d24_d26 $d25_d27 $d26_d28 $d27_d29 $d28_d30 $d29_d31 $q0_q1 $q1_q2 $q2_q3 $q3_q4 $q7_q8 $q8_q9 $q9_q10 $q10_q11 $q11_q12 $q12_q13 $q13_q14 $q14_q15 $q0_q1_q2_q3 $q1_q2_q3_q4 $q2_q3_q4_q5 $q3_q4_q5_q6 $q5_q6_q7_q8 $q6_q7_q8_q9 $q7_q8_q9_q10 $q8_q9_q10_q11 $q9_q10_q11_q12 $q10_q11_q12_q13 $q11_q12_q13_q14 $q12_q13_q14_q15 $r12_sp $r0_r1 $r2_r3 $d0_d1_d2 $d1_d2_d3 $d2_d3_d4 $d3_d4_d5 $d4_d5_d6 $d5_d6_d7 $d6_d7_d8 $d7_d8_d9 $d14_d15_d16 $d15_d16_d17 $d16_d17_d18 $d17_d18_d19 $d18_d19_d20 $d19_d20_d21 $d20_d21_d22 $d21_d22_d23 $d22_d23_d24 $d23_d24_d25 $d24_d25_d26 $d25_d26_d27 $d26_d27_d28 $d27_d28_d29 $d28_d29_d30 $d29_d30_d31 $d0_d2_d4 $d1_d3_d5 $d2_d4_d6 $d3_d5_d7 $d4_d6_d8 $d5_d7_d9 $d6_d8_d10 $d7_d9_d11 $d12_d14_d16 $d13_d15_d17 $d14_d16_d18 $d15_d17_d19 $d16_d18_d20 $d17_d19_d21 $d18_d20_d22 $d19_d21_d23 $d20_d22_d24 $d21_d23_d25 $d22_d24_d26 $d23_d25_d27 $d24_d26_d28 $d25_d27_d29 $d26_d28_d30 $d27_d29_d31 $d0_d2_d4_d6 $d1_d3_d5_d7 $d2_d4_d6_d8 $d3_d5_d7_d9 $d4_d6_d8_d10 $d5_d7_d9_d11 $d6_d8_d10_d12 $d7_d9_d11_d13 $d10_d12_d14_d16 $d11_d13_d15_d17 $d12_d14_d16_d18 $d13_d15_d17_d19 $d14_d16_d18_d20 $d15_d17_d19_d21 $d16_d18_d20_d22 $d17_d19_d21_d23 $d18_d20_d22_d24 $d19_d21_d23_d25 $d20_d22_d24_d26 $d21_d23_d25_d27 $d22_d24_d26_d28 $d23_d25_d27_d29 $d24_d26_d28_d30 $d25_d27_d29_d31 $d1_d2 $d3_d4 $d5_d6 $d7_d8 $d15_d16 $d17_d18 $d19_d20 $d21_d22 $d23_d24 $d25_d26 $d27_d28 $d29_d30 $d1_d2_d3_d4 $d3_d4_d5_d6 $d5_d6_d7_d8 $d7_d8_d9_d10 $d13_d14_d15_d16 $d15_d16_d17_d18 $d17_d18_d19_d20 $d19_d20_d21_d22 $d21_d22_d23_d24 $d23_d24_d25_d26 $d25_d26_d27_d28 $d27_d28_d29_d30
99 call void @bar1()
1010 call void @bar2()
1111 ret void
+0
-28
test/MC/ARM/clrm-asm.s less more
None // RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2>%t \
1 // RUN: | FileCheck --check-prefix=CHECK %s
2 // RUN: FileCheck --check-prefix=ERROR < %t %s
3
4 // CHECK: clrm {r0, r1, r2, r3} @ encoding: [0x9f,0xe8,0x0f,0x00]
5 clrm {r0, r1, r2, r3}
6
7 // CHECK: clrm {r1, r2, r3, r4} @ encoding: [0x9f,0xe8,0x1e,0x00]
8 // ERROR-NOT: register list not in ascending order
9 clrm {r3, r4, r1, r2}
10
11 // CHECK: clrm {r0, apsr, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr} @ encoding: [0x9f,0xe8,0xff,0xdf]
12 clrm {r0-r12, lr, apsr}
13
14 // CHECK: clrm {apsr, lr} @ encoding: [0x9f,0xe8,0x00,0xc0]
15 clrm {apsr, lr}
16
17 // CHECK: clrm {r0, apsr, r1, r2, r3, r4, lr} @ encoding: [0x9f,0xe8,0x1f,0xc0]
18 clrm {r0-r4, apsr, lr}
19
20 // ERROR: invalid register in register list. Valid registers are r0-r12, lr/r14 and APSR.
21 clrm {sp}
22
23 // ERROR: invalid register in register list. Valid registers are r0-r12, lr/r14 and APSR.
24 clrm {r13}
25
26 // ERROR: invalid register in register list. Valid registers are r0-r12, lr/r14 and APSR.
27 clrm {r0-r12, sp}
+0
-98
test/MC/ARM/thumbv8.1m-vmrs-vmsr.s less more
None // RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext,+mve -show-encoding < %s \
1 // RUN: | FileCheck --check-prefix=CHECK %s
2 // RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=-8msecext,+mve -show-encoding < %s 2>%t \
3 // RUN: | FileCheck --check-prefix=CHECK-NOSEC %s
4 // RUN: FileCheck --check-prefix=ERROR-NOSEC < %t %s
5 // RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext,-mve,+vfp2 -show-encoding < %s 2> %t \
6 // RUN: | FileCheck --check-prefix=CHECK-NOMVE %s
7 // RUN: FileCheck --check-prefix=ERROR-NOMVE < %t %s
8 // RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext,+mve,-vfp2 -show-encoding < %s \
9 // RUN: | FileCheck --check-prefix=CHECK-NOVFP %s
10 // RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=-8msecext,-mve,-vfp2 -show-encoding < %s 2> %t
11 // RUN: FileCheck --check-prefix=ERROR-NONE < %t %s
12 // RUN: not llvm-mc -triple=thumbv8m.main-none-eabi -mattr=+8msecext,+vfp2 -show-encoding < %s 2> %t
13 // RUN: FileCheck --check-prefix=ERROR-V8M < %t %s
14
15 // ERROR-V8M: instruction requires: armv8.1m.main
16 // ERROR-NONE: instruction requires: fp registers
17 // CHECK-NOVFP: vmsr fpscr_nzcvqc, r0 @ encoding: [0xe2,0xee,0x10,0x0a]
18 // CHECK-NOMVE: vmsr fpscr_nzcvqc, r0 @ encoding: [0xe2,0xee,0x10,0x0a]
19 // CHECK-NOSEC: vmsr fpscr_nzcvqc, r0 @ encoding: [0xe2,0xee,0x10,0x0a]
20 // CHECK: vmsr fpscr_nzcvqc, r0 @ encoding: [0xe2,0xee,0x10,0x0a]
21 vmsr fpscr_nzcvqc, r0
22
23 // ERROR-V8M: instruction requires: armv8.1m.main
24 // ERROR-NONE: instruction requires: fp registers
25 // CHECK-NOVFP: vmrs r10, fpscr_nzcvqc @ encoding: [0xf2,0xee,0x10,0xaa]
26 // CHECK-NOMVE: vmrs r10, fpscr_nzcvqc @ encoding: [0xf2,0xee,0x10,0xaa]
27 // CHECK-NOSEC: vmrs r10, fpscr_nzcvqc @ encoding: [0xf2,0xee,0x10,0xaa]
28 // CHECK: vmrs r10, fpscr_nzcvqc @ encoding: [0xf2,0xee,0x10,0xaa]
29 vmrs r10, fpscr_nzcvqc
30
31 // ERROR-V8M: instruction requires: armv8.1m.main
32 // ERROR-NONE: instruction requires: ARMv8-M Security Extensions
33 // CHECK-NOVFP: vmrs r0, fpcxtns @ encoding: [0xfe,0xee,0x10,0x0a]
34 // CHECK-NOMVE: vmrs r0, fpcxtns @ encoding: [0xfe,0xee,0x10,0x0a]
35 // ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
36 // CHECK: vmrs r0, fpcxtns @ encoding: [0xfe,0xee,0x10,0x0a]
37 vmrs r0, fpcxtns
38
39 // ERROR-V8M: instruction requires: armv8.1m.main
40 // ERROR-NONE: instruction requires: ARMv8-M Security Extensions
41 // CHECK-NOVFP: vmsr fpcxtns, r10 @ encoding: [0xee,0xee,0x10,0xaa]
42 // CHECK-NOMVE: vmsr fpcxtns, r10 @ encoding: [0xee,0xee,0x10,0xaa]
43 // ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
44 // CHECK: vmsr fpcxtns, r10 @ encoding: [0xee,0xee,0x10,0xaa]
45 vmsr fpcxtns, r10
46
47 // ERROR-V8M: instruction requires: armv8.1m.main
48 // ERROR-NONE: instruction requires: ARMv8-M Security Extensions
49 // CHECK-NOVFP: vmsr fpcxts, r5 @ encoding: [0xef,0xee,0x10,0x5a]
50 // CHECK-NOMVE: vmsr fpcxts, r5 @ encoding: [0xef,0xee,0x10,0x5a]
51 // ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
52 // CHECK: vmsr fpcxts, r5 @ encoding: [0xef,0xee,0x10,0x5a]
53 vmsr fpcxts, r5
54
55 // ERROR-V8M: instruction requires: armv8.1m.main
56 // ERROR-NONE: instruction requires: ARMv8-M Security Extensions
57 // CHECK-NOVFP: vmrs r3, fpcxtns @ encoding: [0xfe,0xee,0x10,0x3a]
58 // CHECK-NOMVE: vmrs r3, fpcxtns @ encoding: [0xfe,0xee,0x10,0x3a]
59 // ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
60 // CHECK: vmrs r3, fpcxtns @ encoding: [0xfe,0xee,0x10,0x3a]
61 vmrs r3, fpcxtns
62
63 // ERROR-V8M: instruction requires: armv8.1m.main
64 // ERROR-NONE: instruction requires: ARMv8-M Security Extensions
65 // CHECK-NOVFP: vmrs r0, fpcxts @ encoding: [0xff,0xee,0x10,0x0a]
66 // CHECK-NOMVE: vmrs r0, fpcxts @ encoding: [0xff,0xee,0x10,0x0a]
67 // ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
68 // CHECK: vmrs r0, fpcxts @ encoding: [0xff,0xee,0x10,0x0a]
69 vmrs r0, fpcxts
70
71 // ERROR-V8M: instruction requires: mve armv8.1m.main
72 // ERROR-NONE: instruction requires: mve
73 // ERROR-NOMVE: instruction requires: mve
74 // CHECK-NOSEC: vmrs r0, vpr @ encoding: [0xfc,0xee,0x10,0x0a]
75 // CHECK: vmrs r0, vpr @ encoding: [0xfc,0xee,0x10,0x0a]
76 vmrs r0, vpr
77
78 // ERROR-V8M: instruction requires: mve armv8.1m.main
79 // ERROR-NONE: instruction requires: mve
80 // ERROR-NOMVE: instruction requires: mve
81 // CHECK-NOSEC: vmrs r4, p0 @ encoding: [0xfd,0xee,0x10,0x4a]
82 // CHECK: vmrs r4, p0 @ encoding: [0xfd,0xee,0x10,0x4a]
83 vmrs r4, p0
84
85 // ERROR-V8M: instruction requires: mve armv8.1m.main
86 // ERROR-NONE: instruction requires: mve
87 // ERROR-NOMVE: instruction requires: mve
88 // CHECK-NOSEC: vmsr vpr, r0 @ encoding: [0xec,0xee,0x10,0x0a]
89 // CHECK: vmsr vpr, r0 @ encoding: [0xec,0xee,0x10,0x0a]
90 vmsr vpr, r0
91
92 // ERROR-V8M: instruction requires: mve armv8.1m.main
93 // ERROR-NONE: instruction requires: mve
94 // ERROR-NOMVE: instruction requires: mve
95 // CHECK-NOSEC: vmsr p0, r4 @ encoding: [0xed,0xee,0x10,0x4a]
96 // CHECK: vmsr p0, r4 @ encoding: [0xed,0xee,0x10,0x4a]
97 vmsr p0, r4
+0
-1114
test/MC/ARM/thumbv8.1m.s less more
None // RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2>%t \
1 // RUN: | FileCheck --check-prefix=CHECK %s
2 // RUN: FileCheck --check-prefix=ERROR < %t %s
3 // RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+fp-armv8d16sp,+fullfp16 -show-encoding < %s 2>%t \
4 // RUN: | FileCheck --check-prefix=CHECK-FP %s
5 // RUN: FileCheck --check-prefix=ERROR-FP < %t %s
6 // RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=-lob -show-encoding < %s 2>%t \
7 // RUN: | FileCheck --check-prefix=CHECK-NOLOB %s
8 // RUN: FileCheck --check-prefix=ERROR-NOLOB < %t %s
9
10 // Check that .arm is invalid
11 // ERROR: target does not support ARM mode
12 // ERROR-FP: target does not support ARM mode
13 .arm
14
15 // Make sure the addition of CLRM does not mess up normal register lists
16 // ERROR: invalid operand for instruction
17 // ERROR-FP: invalid operand for instruction
18 push {r0, apsr}
19
20 // Instruction availibility checks
21
22 // 'Branch Future and Low Overhead Loop instructions'
23
24 // For tests where the LOB extension is turned off, we can't always
25 // depend on the nice diagnostic 'error: instruction requires: lob',
26 // because if AsmMatcher can find anything else wrong with the
27 // instruction, it won't report a specific cause of failure ('multiple
28 // types of mismatch, so not reporting near-miss'). This can happen in
29 // the error cases below where the instruction deliberately has
30 // something else wrong with it, and it can also happen when the
31 // instruction takes a condition-code argument, because with LOB
32 // turned off, the operand parsing will reinterpret 'eq' or 'ne' or
33 // similar as a SymbolRef, and then it won't even match against
34 // MCK_CondCodeNoAL. So that counts as a second cause of failure from
35 // AsmMatcher's point of view as well. Hence, a lot of the NOLOB error
36 // checks just check for "error:", enforcing that MC found *something*
37 // wrong with the instruction.
38
39 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
40 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
41 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
42 bf #-2, #10
43
44 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
45 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
46 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
47 bf #0, #10
48
49 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
50 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
51 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
52 bf #7, #10
53
54 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
55 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
56 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
57 bfx #-4, r3
58
59 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
60 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
61 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
62 bfx #0, r3
63
64 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
65 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
66 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
67 bfx #13, r3
68
69 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
70 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
71 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
72 bfl #-2, #20
73
74 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
75 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
76 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
77 bfl #0, #20
78
79 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
80 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
81 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
82 bfl #13, #20
83
84 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
85 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
86 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
87 bf #4, #65536
88
89 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
90 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
91 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
92 bf #4, #-65538
93
94 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
95 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
96 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
97 bfl #4, #262144
98
99 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
100 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
101 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
102 bfl #4, #-262146
103
104 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
105 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
106 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
107 bfcsel #-2, #10, #2, eq
108
109 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
110 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
111 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
112 bfcsel #0, #10, #2, eq
113
114 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
115 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
116 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
117 bfcsel #13, #10, #15, eq
118
119 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
120 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
121 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
122 bfcsel #4, #65536, #6, eq
123
124 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
125 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
126 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
127 bfcsel #4, #-65538, #8, eq
128
129 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: else branch target must be 2 or 4 greater than the branch location
130 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: else branch target must be 2 or 4 greater than the branch location
131 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
132 bfcsel #4, #65534, #10, eq
133
134 // CHECK: bf .Lbranch, .Ltarget @ encoding: [0x40'B',0xf0'B',0x01'B',0xe0'B']
135 // CHECK-FP: bf .Lbranch, .Ltarget @ encoding: [0x40'B',0xf0'B',0x01'B',0xe0'B']
136 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
137 bf .Lbranch, .Ltarget
138
139 // CHECK: bfcsel .Lbranch, .Lthen, .Lelse, ne @ encoding: [0x04'C',0xf0'C',0x01'C',0xe0'C']
140 // CHECK-FP: bfcsel .Lbranch, .Lthen, .Lelse, ne @ encoding: [0x04'C',0xf0'C',0x01'C',0xe0'C']
141 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
142 bfcsel .Lbranch, .Lthen, .Lelse, ne
143
144 // CHECK: bfx .Lbranch, r3 @ encoding: [0x63'A',0xf0'A',0x01'A',0xe0'A']
145 // CHECK-FP: bfx .Lbranch, r3 @ encoding: [0x63'A',0xf0'A',0x01'A',0xe0'A']
146 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
147 bfx .Lbranch, r3
148
149 // CHECK: bfl .Lbranch, .Ltarget @ encoding: [B,0xf0'B',0x01'B',0xc0'B']
150 // CHECK-FP: bfl .Lbranch, .Ltarget @ encoding: [B,0xf0'B',0x01'B',0xc0'B']
151 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
152 bfl .Lbranch, .Ltarget
153
154 // CHECK: bflx .Lbranch, r7 @ encoding: [0x77'A',0xf0'A',0x01'A',0xe0'A']
155 // CHECK-FP: bflx .Lbranch, r7 @ encoding: [0x77'A',0xf0'A',0x01'A',0xe0'A']
156 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
157 bflx .Lbranch, r7
158
159 // CHECK: wls lr, r2, .Lend @ encoding: [0x42'A',0xf0'A',0x01'A',0xc0'A']
160 // CHECK-FP: wls lr, r2, .Lend @ encoding: [0x42'A',0xf0'A',0x01'A',0xc0'A']
161 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
162 wls lr, r2, .Lend
163
164 // CHECK: dls lr, r2 @ encoding: [0x42,0xf0,0x01,0xe0]
165 // CHECK-FP: dls lr, r2 @ encoding: [0x42,0xf0,0x01,0xe0]
166 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
167 dls lr, r2
168
169 // CHECK: le lr, .Lstart @ encoding: [0x0f'A',0xf0'A',0x01'A',0xc0'A']
170 // CHECK-FP: le lr, .Lstart @ encoding: [0x0f'A',0xf0'A',0x01'A',0xc0'A']
171 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
172 le lr, .Lstart
173
174 // CHECK: le .Lstart @ encoding: [0x2f'A',0xf0'A',0x01'A',0xc0'A']
175 // CHECK-FP: le .Lstart @ encoding: [0x2f'A',0xf0'A',0x01'A',0xc0'A']
176 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
177 le .Lstart
178
179 // CHECK: dls lr, lr @ encoding: [0x4e,0xf0,0x01,0xe0]
180 // CHECK-FP: dls lr, lr @ encoding: [0x4e,0xf0,0x01,0xe0]
181 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
182 dls lr, lr
183
184 // CHECK: dls lr, r0 @ encoding: [0x40,0xf0,0x01,0xe0]
185 // CHECK-FP: dls lr, r0 @ encoding: [0x40,0xf0,0x01,0xe0]
186 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
187 dls lr, r0
188
189 // CHECK: dls lr, r1 @ encoding: [0x41,0xf0,0x01,0xe0]
190 // CHECK-FP: dls lr, r1 @ encoding: [0x41,0xf0,0x01,0xe0]
191 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
192 dls lr, r1
193
194 // CHECK: dls lr, r10 @ encoding: [0x4a,0xf0,0x01,0xe0]
195 // CHECK-FP: dls lr, r10 @ encoding: [0x4a,0xf0,0x01,0xe0]
196 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
197 dls lr, r10
198
199 // CHECK: dls lr, r11 @ encoding: [0x4b,0xf0,0x01,0xe0]
200 // CHECK-FP: dls lr, r11 @ encoding: [0x4b,0xf0,0x01,0xe0]
201 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
202 dls lr, r11
203
204 // CHECK: dls lr, r12 @ encoding: [0x4c,0xf0,0x01,0xe0]
205 // CHECK-FP: dls lr, r12 @ encoding: [0x4c,0xf0,0x01,0xe0]
206 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
207 dls lr, r12
208
209 // CHECK: dls lr, r2 @ encoding: [0x42,0xf0,0x01,0xe0]
210 // CHECK-FP: dls lr, r2 @ encoding: [0x42,0xf0,0x01,0xe0]
211 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
212 dls lr, r2
213
214 // CHECK: dls lr, r3 @ encoding: [0x43,0xf0,0x01,0xe0]
215 // CHECK-FP: dls lr, r3 @ encoding: [0x43,0xf0,0x01,0xe0]
216 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
217 dls lr, r3
218
219 // CHECK: dls lr, r5 @ encoding: [0x45,0xf0,0x01,0xe0]
220 // CHECK-FP: dls lr, r5 @ encoding: [0x45,0xf0,0x01,0xe0]
221 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
222 dls lr, r5
223
224 // CHECK: dls lr, r6 @ encoding: [0x46,0xf0,0x01,0xe0]
225 // CHECK-FP: dls lr, r6 @ encoding: [0x46,0xf0,0x01,0xe0]
226 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
227 dls lr, r6
228
229 // CHECK: dls lr, r7 @ encoding: [0x47,0xf0,0x01,0xe0]
230 // CHECK-FP: dls lr, r7 @ encoding: [0x47,0xf0,0x01,0xe0]
231 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
232 dls lr, r7
233
234 // CHECK: dls lr, r8 @ encoding: [0x48,0xf0,0x01,0xe0]
235 // CHECK-FP: dls lr, r8 @ encoding: [0x48,0xf0,0x01,0xe0]
236 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
237 dls lr, r8
238
239 // CHECK: dls lr, r9 @ encoding: [0x49,0xf0,0x01,0xe0]
240 // CHECK-FP: dls lr, r9 @ encoding: [0x49,0xf0,0x01,0xe0]
241 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
242 dls lr, r9
243
244 // CHECK: le #-106 @ encoding: [0x2f,0xf0,0x35,0xc8]
245 // CHECK-FP: le #-106 @ encoding: [0x2f,0xf0,0x35,0xc8]
246 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
247 le #-106
248
249 // CHECK: le #-1172 @ encoding: [0x2f,0xf0,0x4b,0xc2]
250 // CHECK-FP: le #-1172 @ encoding: [0x2f,0xf0,0x4b,0xc2]
251 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
252 le #-1172
253
254 // CHECK: le #-1210 @ encoding: [0x2f,0xf0,0x5d,0xca]
255 // CHECK-FP: le #-1210 @ encoding: [0x2f,0xf0,0x5d,0xca]
256 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
257 le #-1210
258
259 // CHECK: le #-1260 @ encoding: [0x2f,0xf0,0x77,0xc2]
260 // CHECK-FP: le #-1260 @ encoding: [0x2f,0xf0,0x77,0xc2]
261 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
262 le #-1260
263
264 // CHECK: le #-1262 @ encoding: [0x2f,0xf0,0x77,0xca]
265 // CHECK-FP: le #-1262 @ encoding: [0x2f,0xf0,0x77,0xca]
266 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
267 le #-1262
268
269 // CHECK: le #-1284 @ encoding: [0x2f,0xf0,0x83,0xc2]
270 // CHECK-FP: le #-1284 @ encoding: [0x2f,0xf0,0x83,0xc2]
271 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
272 le #-1284
273
274 // CHECK: le #-1286 @ encoding: [0x2f,0xf0,0x83,0xca]
275 // CHECK-FP: le #-1286 @ encoding: [0x2f,0xf0,0x83,0xca]
276 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
277 le #-1286
278
279 // CHECK: le #-1556 @ encoding: [0x2f,0xf0,0x0b,0xc3]
280 // CHECK-FP: le #-1556 @ encoding: [0x2f,0xf0,0x0b,0xc3]
281 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
282 le #-1556
283
284 // CHECK: le #-178 @ encoding: [0x2f,0xf0,0x59,0xc8]
285 // CHECK-FP: le #-178 @ encoding: [0x2f,0xf0,0x59,0xc8]
286 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
287 le #-178
288
289 // CHECK: le #-1882 @ encoding: [0x2f,0xf0,0xad,0xcb]
290 // CHECK-FP: le #-1882 @ encoding: [0x2f,0xf0,0xad,0xcb]
291 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
292 le #-1882
293
294 // CHECK: le #-1900 @ encoding: [0x2f,0xf0,0xb7,0xc3]
295 // CHECK-FP: le #-1900 @ encoding: [0x2f,0xf0,0xb7,0xc3]
296 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
297 le #-1900
298
299 // CHECK: le #-1910 @ encoding: [0x2f,0xf0,0xbb,0xcb]
300 // CHECK-FP: le #-1910 @ encoding: [0x2f,0xf0,0xbb,0xcb]
301 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
302 le #-1910
303
304 // CHECK: le #-2076 @ encoding: [0x2f,0xf0,0x0f,0xc4]
305 // CHECK-FP: le #-2076 @ encoding: [0x2f,0xf0,0x0f,0xc4]
306 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
307 le #-2076
308
309 // CHECK: le #-2266 @ encoding: [0x2f,0xf0,0x6d,0xcc]
310 // CHECK-FP: le #-2266 @ encoding: [0x2f,0xf0,0x6d,0xcc]
311 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
312 le #-2266
313
314 // CHECK: le #-2324 @ encoding: [0x2f,0xf0,0x8b,0xc4]
315 // CHECK-FP: le #-2324 @ encoding: [0x2f,0xf0,0x8b,0xc4]
316 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
317 le #-2324
318
319 // CHECK: le #-2328 @ encoding: [0x2f,0xf0,0x8d,0xc4]
320 // CHECK-FP: le #-2328 @ encoding: [0x2f,0xf0,0x8d,0xc4]
321 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
322 le #-2328
323
324 // CHECK: le #-2456 @ encoding: [0x2f,0xf0,0xcd,0xc4]
325 // CHECK-FP: le #-2456 @ encoding: [0x2f,0xf0,0xcd,0xc4]
326 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
327 le #-2456
328
329 // CHECK: le #-246 @ encoding: [0x2f,0xf0,0x7b,0xc8]
330 // CHECK-FP: le #-246 @ encoding: [0x2f,0xf0,0x7b,0xc8]
331 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
332 le #-246
333
334 // CHECK: le #-2476 @ encoding: [0x2f,0xf0,0xd7,0xc4]
335 // CHECK-FP: le #-2476 @ encoding: [0x2f,0xf0,0xd7,0xc4]
336 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
337 le #-2476
338
339 // CHECK: le #-2578 @ encoding: [0x2f,0xf0,0x09,0xcd]
340 // CHECK-FP: le #-2578 @ encoding: [0x2f,0xf0,0x09,0xcd]
341 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
342 le #-2578
343
344 // CHECK: le #-262 @ encoding: [0x2f,0xf0,0x83,0xc8]
345 // CHECK-FP: le #-262 @ encoding: [0x2f,0xf0,0x83,0xc8]
346 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
347 le #-262
348
349 // CHECK: le #-2660 @ encoding: [0x2f,0xf0,0x33,0xc5]
350 // CHECK-FP: le #-2660 @ encoding: [0x2f,0xf0,0x33,0xc5]
351 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
352 le #-2660
353
354 // CHECK: le #-2722 @ encoding: [0x2f,0xf0,0x51,0xcd]
355 // CHECK-FP: le #-2722 @ encoding: [0x2f,0xf0,0x51,0xcd]
356 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
357 le #-2722
358
359 // CHECK: le #-2868 @ encoding: [0x2f,0xf0,0x9b,0xc5]
360 // CHECK-FP: le #-2868 @ encoding: [0x2f,0xf0,0x9b,0xc5]
361 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
362 le #-2868
363
364 // CHECK: le #-2882 @ encoding: [0x2f,0xf0,0xa1,0xcd]
365 // CHECK-FP: le #-2882 @ encoding: [0x2f,0xf0,0xa1,0xcd]
366 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
367 le #-2882
368
369 // CHECK: le #-3154 @ encoding: [0x2f,0xf0,0x29,0xce]
370 // CHECK-FP: le #-3154 @ encoding: [0x2f,0xf0,0x29,0xce]
371 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
372 le #-3154
373
374 // CHECK: le #-3274 @ encoding: [0x2f,0xf0,0x65,0xce]
375 // CHECK-FP: le #-3274 @ encoding: [0x2f,0xf0,0x65,0xce]
376 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
377 le #-3274
378
379 // CHECK: le #-3352 @ encoding: [0x2f,0xf0,0x8d,0xc6]
380 // CHECK-FP: le #-3352 @ encoding: [0x2f,0xf0,0x8d,0xc6]
381 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
382 le #-3352
383
384 // CHECK: le #-338 @ encoding: [0x2f,0xf0,0xa9,0xc8]
385 // CHECK-FP: le #-338 @ encoding: [0x2f,0xf0,0xa9,0xc8]
386 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
387 le #-338
388
389 // CHECK: le #-3458 @ encoding: [0x2f,0xf0,0xc1,0xce]
390 // CHECK-FP: le #-3458 @ encoding: [0x2f,0xf0,0xc1,0xce]
391 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
392 le #-3458
393
394 // CHECK: le #-3480 @ encoding: [0x2f,0xf0,0xcd,0xc6]
395 // CHECK-FP: le #-3480 @ encoding: [0x2f,0xf0,0xcd,0xc6]
396 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
397 le #-3480
398
399 // CHECK: le #-3542 @ encoding: [0x2f,0xf0,0xeb,0xce]
400 // CHECK-FP: le #-3542 @ encoding: [0x2f,0xf0,0xeb,0xce]
401 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
402 le #-3542
403
404 // CHECK: le #-3644 @ encoding: [0x2f,0xf0,0x1f,0xc7]
405 // CHECK-FP: le #-3644 @ encoding: [0x2f,0xf0,0x1f,0xc7]
406 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
407 le #-3644
408
409 // CHECK: le #-3676 @ encoding: [0x2f,0xf0,0x2f,0xc7]
410 // CHECK-FP: le #-3676 @ encoding: [0x2f,0xf0,0x2f,0xc7]
411 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
412 le #-3676
413
414 // CHECK: le #-3692 @ encoding: [0x2f,0xf0,0x37,0xc7]
415 // CHECK-FP: le #-3692 @ encoding: [0x2f,0xf0,0x37,0xc7]
416 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
417 le #-3692
418
419 // CHECK: le #-3860 @ encoding: [0x2f,0xf0,0x8b,0xc7]
420 // CHECK-FP: le #-3860 @ encoding: [0x2f,0xf0,0x8b,0xc7]
421 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
422 le #-3860
423
424 // CHECK: le #-3986 @ encoding: [0x2f,0xf0,0xc9,0xcf]
425 // CHECK-FP: le #-3986 @ encoding: [0x2f,0xf0,0xc9,0xcf]
426 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
427 le #-3986
428
429 // CHECK: le #-4006 @ encoding: [0x2f,0xf0,0xd3,0xcf]
430 // CHECK-FP: le #-4006 @ encoding: [0x2f,0xf0,0xd3,0xcf]
431 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
432 le #-4006
433
434 // CHECK: le #-4034 @ encoding: [0x2f,0xf0,0xe1,0xcf]
435 // CHECK-FP: le #-4034 @ encoding: [0x2f,0xf0,0xe1,0xcf]
436 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
437 le #-4034
438
439 // CHECK: le #-4060 @ encoding: [0x2f,0xf0,0xef,0xc7]
440 // CHECK-FP: le #-4060 @ encoding: [0x2f,0xf0,0xef,0xc7]
441 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
442 le #-4060
443
444 // CHECK: le #-4068 @ encoding: [0x2f,0xf0,0xf3,0xc7]
445 // CHECK-FP: le #-4068 @ encoding: [0x2f,0xf0,0xf3,0xc7]
446 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
447 le #-4068
448
449 // CHECK: le #-478 @ encoding: [0x2f,0xf0,0xef,0xc8]
450 // CHECK-FP: le #-478 @ encoding: [0x2f,0xf0,0xef,0xc8]
451 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
452 le #-478
453
454 // CHECK: le #-544 @ encoding: [0x2f,0xf0,0x11,0xc1]
455 // CHECK-FP: le #-544 @ encoding: [0x2f,0xf0,0x11,0xc1]
456 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
457 le #-544
458
459 // CHECK: le #-586 @ encoding: [0x2f,0xf0,0x25,0xc9]
460 // CHECK-FP: le #-586 @ encoding: [0x2f,0xf0,0x25,0xc9]
461 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
462 le #-586
463
464 // CHECK: le #-606 @ encoding: [0x2f,0xf0,0x2f,0xc9]
465 // CHECK-FP: le #-606 @ encoding: [0x2f,0xf0,0x2f,0xc9]
466 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
467 le #-606
468
469 // CHECK: le #-656 @ encoding: [0x2f,0xf0,0x49,0xc1]
470 // CHECK-FP: le #-656 @ encoding: [0x2f,0xf0,0x49,0xc1]
471 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
472 le #-656
473
474 // CHECK: le #-740 @ encoding: [0x2f,0xf0,0x73,0xc1]
475 // CHECK-FP: le #-740 @ encoding: [0x2f,0xf0,0x73,0xc1]
476 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
477 le #-740
478
479 // CHECK: le #-762 @ encoding: [0x2f,0xf0,0x7d,0xc9]
480 // CHECK-FP: le #-762 @ encoding: [0x2f,0xf0,0x7d,0xc9]
481 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
482 le #-762
483
484 // CHECK: le #-862 @ encoding: [0x2f,0xf0,0xaf,0xc9]
485 // CHECK-FP: le #-862 @ encoding: [0x2f,0xf0,0xaf,0xc9]
486 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
487 le #-862
488
489 // CHECK: le #-870 @ encoding: [0x2f,0xf0,0xb3,0xc9]
490 // CHECK-FP: le #-870 @ encoding: [0x2f,0xf0,0xb3,0xc9]
491 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
492 le #-870
493
494 // CHECK: le lr, #-1080 @ encoding: [0x0f,0xf0,0x1d,0xc2]
495 // CHECK-FP: le lr, #-1080 @ encoding: [0x0f,0xf0,0x1d,0xc2]
496 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
497 le lr, #-1080
498
499 // CHECK: le lr, #-1104 @ encoding: [0x0f,0xf0,0x29,0xc2]
500 // CHECK-FP: le lr, #-1104 @ encoding: [0x0f,0xf0,0x29,0xc2]
501 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
502 le lr, #-1104
503
504 // CHECK: le lr, #-1152 @ encoding: [0x0f,0xf0,0x41,0xc2]
505 // CHECK-FP: le lr, #-1152 @ encoding: [0x0f,0xf0,0x41,0xc2]
506 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
507 le lr, #-1152
508
509 // CHECK: le lr, #-1462 @ encoding: [0x0f,0xf0,0xdb,0xca]
510 // CHECK-FP: le lr, #-1462 @ encoding: [0x0f,0xf0,0xdb,0xca]
511 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
512 le lr, #-1462
513
514 // CHECK: le lr, #-1470 @ encoding: [0x0f,0xf0,0xdf,0xca]
515 // CHECK-FP: le lr, #-1470 @ encoding: [0x0f,0xf0,0xdf,0xca]
516 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
517 le lr, #-1470
518
519 // CHECK: le lr, #-1612 @ encoding: [0x0f,0xf0,0x27,0xc3]
520 // CHECK-FP: le lr, #-1612 @ encoding: [0x0f,0xf0,0x27,0xc3]
521 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
522 le lr, #-1612
523
524 // CHECK: le lr, #-1632 @ encoding: [0x0f,0xf0,0x31,0xc3]
525 // CHECK-FP: le lr, #-1632 @ encoding: [0x0f,0xf0,0x31,0xc3]
526 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
527 le lr, #-1632
528
529 // CHECK: le lr, #-1694 @ encoding: [0x0f,0xf0,0x4f,0xcb]
530 // CHECK-FP: le lr, #-1694 @ encoding: [0x0f,0xf0,0x4f,0xcb]
531 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
532 le lr, #-1694
533
534 // CHECK: le lr, #-1714 @ encoding: [0x0f,0xf0,0x59,0xcb]
535 // CHECK-FP: le lr, #-1714 @ encoding: [0x0f,0xf0,0x59,0xcb]
536 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
537 le lr, #-1714
538
539 // CHECK: le lr, #-1850 @ encoding: [0x0f,0xf0,0x9d,0xcb]
540 // CHECK-FP: le lr, #-1850 @ encoding: [0x0f,0xf0,0x9d,0xcb]
541 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
542 le lr, #-1850
543
544 // CHECK: le lr, #-1878 @ encoding: [0x0f,0xf0,0xab,0xcb]
545 // CHECK-FP: le lr, #-1878 @ encoding: [0x0f,0xf0,0xab,0xcb]
546 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
547 le lr, #-1878
548
549 // CHECK: le lr, #-1896 @ encoding: [0x0f,0xf0,0xb5,0xc3]
550 // CHECK-FP: le lr, #-1896 @ encoding: [0x0f,0xf0,0xb5,0xc3]
551 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
552 le lr, #-1896
553
554 // CHECK: le lr, #-1922 @ encoding: [0x0f,0xf0,0xc1,0xcb]
555 // CHECK-FP: le lr, #-1922 @ encoding: [0x0f,0xf0,0xc1,0xcb]
556 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
557 le lr, #-1922
558
559 // CHECK: le lr, #-1926 @ encoding: [0x0f,0xf0,0xc3,0xcb]
560 // CHECK-FP: le lr, #-1926 @ encoding: [0x0f,0xf0,0xc3,0xcb]
561 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
562 le lr, #-1926
563
564 // CHECK: le lr, #-2 @ encoding: [0x0f,0xf0,0x01,0xc8]
565 // CHECK-FP: le lr, #-2 @ encoding: [0x0f,0xf0,0x01,0xc8]
566 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
567 le lr, #-2
568
569 // CHECK: le lr, #-2104 @ encoding: [0x0f,0xf0,0x1d,0xc4]
570 // CHECK-FP: le lr, #-2104 @ encoding: [0x0f,0xf0,0x1d,0xc4]
571 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
572 le lr, #-2104
573
574 // CHECK: le lr, #-2116 @ encoding: [0x0f,0xf0,0x23,0xc4]
575 // CHECK-FP: le lr, #-2116 @ encoding: [0x0f,0xf0,0x23,0xc4]
576 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
577 le lr, #-2116
578
579 // CHECK: le lr, #-2144 @ encoding: [0x0f,0xf0,0x31,0xc4]
580 // CHECK-FP: le lr, #-2144 @ encoding: [0x0f,0xf0,0x31,0xc4]
581 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
582 le lr, #-2144
583
584 // CHECK: le lr, #-2188 @ encoding: [0x0f,0xf0,0x47,0xc4]
585 // CHECK-FP: le lr, #-2188 @ encoding: [0x0f,0xf0,0x47,0xc4]
586 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
587 le lr, #-2188
588
589 // CHECK: le lr, #-2344 @ encoding: [0x0f,0xf0,0x95,0xc4]
590 // CHECK-FP: le lr, #-2344 @ encoding: [0x0f,0xf0,0x95,0xc4]
591 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
592 le lr, #-2344
593
594 // CHECK: le lr, #-2456 @ encoding: [0x0f,0xf0,0xcd,0xc4]
595 // CHECK-FP: le lr, #-2456 @ encoding: [0x0f,0xf0,0xcd,0xc4]
596 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
597 le lr, #-2456
598
599 // CHECK: le lr, #-2608 @ encoding: [0x0f,0xf0,0x19,0xc5]
600 // CHECK-FP: le lr, #-2608 @ encoding: [0x0f,0xf0,0x19,0xc5]
601 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
602 le lr, #-2608
603
604 // CHECK: le lr, #-2616 @ encoding: [0x0f,0xf0,0x1d,0xc5]
605 // CHECK-FP: le lr, #-2616 @ encoding: [0x0f,0xf0,0x1d,0xc5]
606 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
607 le lr, #-2616
608
609 // CHECK: le lr, #-2622 @ encoding: [0x0f,0xf0,0x1f,0xcd]
610 // CHECK-FP: le lr, #-2622 @ encoding: [0x0f,0xf0,0x1f,0xcd]
611 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
612 le lr, #-2622
613
614 // CHECK: le lr, #-2680 @ encoding: [0x0f,0xf0,0x3d,0xc5]
615 // CHECK-FP: le lr, #-2680 @ encoding: [0x0f,0xf0,0x3d,0xc5]
616 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
617 le lr, #-2680
618
619 // CHECK: le lr, #-2694 @ encoding: [0x0f,0xf0,0x43,0xcd]
620 // CHECK-FP: le lr, #-2694 @ encoding: [0x0f,0xf0,0x43,0xcd]
621 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
622 le lr, #-2694
623
624 // CHECK: le lr, #-2850 @ encoding: [0x0f,0xf0,0x91,0xcd]
625 // CHECK-FP: le lr, #-2850 @ encoding: [0x0f,0xf0,0x91,0xcd]
626 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
627 le lr, #-2850
628
629 // CHECK: le lr, #-2860 @ encoding: [0x0f,0xf0,0x97,0xc5]
630 // CHECK-FP: le lr, #-2860 @ encoding: [0x0f,0xf0,0x97,0xc5]
631 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
632 le lr, #-2860
633
634 // CHECK: le lr, #-3004 @ encoding: [0x0f,0xf0,0xdf,0xc5]
635 // CHECK-FP: le lr, #-3004 @ encoding: [0x0f,0xf0,0xdf,0xc5]
636 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
637 le lr, #-3004
638
639 // CHECK: le lr, #-3018 @ encoding: [0x0f,0xf0,0xe5,0xcd]
640 // CHECK-FP: le lr, #-3018 @ encoding: [0x0f,0xf0,0xe5,0xcd]
641 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
642 le lr, #-3018
643
644 // CHECK: le lr, #-304 @ encoding: [0x0f,0xf0,0x99,0xc0]
645 // CHECK-FP: le lr, #-304 @ encoding: [0x0f,0xf0,0x99,0xc0]
646 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
647 le lr, #-304
648
649 // CHECK: le lr, #-3098 @ encoding: [0x0f,0xf0,0x0d,0xce]
650 // CHECK-FP: le lr, #-3098 @ encoding: [0x0f,0xf0,0x0d,0xce]
651 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
652 le lr, #-3098
653
654 // CHECK: le lr, #-3228 @ encoding: [0x0f,0xf0,0x4f,0xc6]
655 // CHECK-FP: le lr, #-3228 @ encoding: [0x0f,0xf0,0x4f,0xc6]
656 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
657 le lr, #-3228
658
659 // CHECK: le lr, #-3316 @ encoding: [0x0f,0xf0,0x7b,0xc6]
660 // CHECK-FP: le lr, #-3316 @ encoding: [0x0f,0xf0,0x7b,0xc6]
661 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
662 le lr, #-3316
663
664 // CHECK: le lr, #-3332 @ encoding: [0x0f,0xf0,0x83,0xc6]
665 // CHECK-FP: le lr, #-3332 @ encoding: [0x0f,0xf0,0x83,0xc6]
666 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
667 le lr, #-3332
668
669 // CHECK: le lr, #-3354 @ encoding: [0x0f,0xf0,0x8d,0xce]
670 // CHECK-FP: le lr, #-3354 @ encoding: [0x0f,0xf0,0x8d,0xce]
671 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
672 le lr, #-3354
673
674 // CHECK: le lr, #-3962 @ encoding: [0x0f,0xf0,0xbd,0xcf]
675 // CHECK-FP: le lr, #-3962 @ encoding: [0x0f,0xf0,0xbd,0xcf]
676 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
677 le lr, #-3962
678
679 // CHECK: le lr, #-4042 @ encoding: [0x0f,0xf0,0xe5,0xcf]
680 // CHECK-FP: le lr, #-4042 @ encoding: [0x0f,0xf0,0xe5,0xcf]
681 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
682 le lr, #-4042
683
684 // CHECK: le lr, #-4052 @ encoding: [0x0f,0xf0,0xeb,0xc7]
685 // CHECK-FP: le lr, #-4052 @ encoding: [0x0f,0xf0,0xeb,0xc7]
686 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
687 le lr, #-4052
688
689 // CHECK: le lr, #-458 @ encoding: [0x0f,0xf0,0xe5,0xc8]
690 // CHECK-FP: le lr, #-458 @ encoding: [0x0f,0xf0,0xe5,0xc8]
691 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
692 le lr, #-458
693
694 // CHECK: le lr, #-56 @ encoding: [0x0f,0xf0,0x1d,0xc0]
695 // CHECK-FP: le lr, #-56 @ encoding: [0x0f,0xf0,0x1d,0xc0]
696 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
697 le lr, #-56
698
699 // CHECK: le lr, #-582 @ encoding: [0x0f,0xf0,0x23,0xc9]
700 // CHECK-FP: le lr, #-582 @ encoding: [0x0f,0xf0,0x23,0xc9]
701 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
702 le lr, #-582
703
704 // CHECK: le lr, #-676 @ encoding: [0x0f,0xf0,0x53,0xc1]
705 // CHECK-FP: le lr, #-676 @ encoding: [0x0f,0xf0,0x53,0xc1]
706 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
707 le lr, #-676
708
709 // CHECK: le lr, #-752 @ encoding: [0x0f,0xf0,0x79,0xc1]
710 // CHECK-FP: le lr, #-752 @ encoding: [0x0f,0xf0,0x79,0xc1]
711 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
712 le lr, #-752
713
714 // CHECK: le lr, #-76 @ encoding: [0x0f,0xf0,0x27,0xc0]
715 // CHECK-FP: le lr, #-76 @ encoding: [0x0f,0xf0,0x27,0xc0]
716 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
717 le lr, #-76
718
719 // CHECK: le lr, #-802 @ encoding: [0x0f,0xf0,0x91,0xc9]
720 // CHECK-FP: le lr, #-802 @ encoding: [0x0f,0xf0,0x91,0xc9]
721 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
722 le lr, #-802
723
724 // CHECK: le lr, #-862 @ encoding: [0x0f,0xf0,0xaf,0xc9]
725 // CHECK-FP: le lr, #-862 @ encoding: [0x0f,0xf0,0xaf,0xc9]
726 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
727 le lr, #-862
728
729 // CHECK: le lr, #-902 @ encoding: [0x0f,0xf0,0xc3,0xc9]
730 // CHECK-FP: le lr, #-902 @ encoding: [0x0f,0xf0,0xc3,0xc9]
731 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
732 le lr, #-902
733
734 // CHECK: le lr, #-968 @ encoding: [0x0f,0xf0,0xe5,0xc1]
735 // CHECK-FP: le lr, #-968 @ encoding: [0x0f,0xf0,0xe5,0xc1]
736 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
737 le lr, #-968
738
739 // CHECK: wls lr, lr, #1192 @ encoding: [0x4e,0xf0,0x55,0xc2]
740 // CHECK-FP: wls lr, lr, #1192 @ encoding: [0x4e,0xf0,0x55,0xc2]
741 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
742 wls lr, lr, #1192
743
744 // CHECK: wls lr, lr, #2134 @ encoding: [0x4e,0xf0,0x2b,0xcc]
745 // CHECK-FP: wls lr, lr, #2134 @ encoding: [0x4e,0xf0,0x2b,0xcc]
746 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
747 wls lr, lr, #2134
748
749 // CHECK: wls lr, lr, #962 @ encoding: [0x4e,0xf0,0xe1,0xc9]
750 // CHECK-FP: wls lr, lr, #962 @ encoding: [0x4e,0xf0,0xe1,0xc9]
751 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
752 wls lr, lr, #962
753
754 // CHECK: wls lr, r0, #1668 @ encoding: [0x40,0xf0,0x43,0xc3]
755 // CHECK-FP: wls lr, r0, #1668 @ encoding: [0x40,0xf0,0x43,0xc3]
756 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
757 wls lr, r0, #1668
758
759 // CHECK: wls lr, r0, #2706 @ encoding: [0x40,0xf0,0x49,0xcd]
760 // CHECK-FP: wls lr, r0, #2706 @ encoding: [0x40,0xf0,0x49,0xcd]
761 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
762 wls lr, r0, #2706
763
764 // CHECK: wls lr, r0, #3026 @ encoding: [0x40,0xf0,0xe9,0xcd]
765 // CHECK-FP: wls lr, r0, #3026 @ encoding: [0x40,0xf0,0xe9,0xcd]
766 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
767 wls lr, r0, #3026
768
769 // CHECK: wls lr, r0, #3436 @ encoding: [0x40,0xf0,0xb7,0xc6]
770 // CHECK-FP: wls lr, r0, #3436 @ encoding: [0x40,0xf0,0xb7,0xc6]
771 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
772 wls lr, r0, #3436
773
774 // CHECK: wls lr, r1, #1060 @ encoding: [0x41,0xf0,0x13,0xc2]
775 // CHECK-FP: wls lr, r1, #1060 @ encoding: [0x41,0xf0,0x13,0xc2]
776 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
777 wls lr, r1, #1060
778
779 // CHECK: wls lr, r1, #4036 @ encoding: [0x41,0xf0,0xe3,0xc7]
780 // CHECK-FP: wls lr, r1, #4036 @ encoding: [0x41,0xf0,0xe3,0xc7]
781 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
782 wls lr, r1, #4036
783
784 // CHECK: wls lr, r1, #538 @ encoding: [0x41,0xf0,0x0d,0xc9]
785 // CHECK-FP: wls lr, r1, #538 @ encoding: [0x41,0xf0,0x0d,0xc9]
786 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
787 wls lr, r1, #538
788
789 // CHECK: wls lr, r10, #1404 @ encoding: [0x4a,0xf0,0xbf,0xc2]
790 // CHECK-FP: wls lr, r10, #1404 @ encoding: [0x4a,0xf0,0xbf,0xc2]
791 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
792 wls lr, r10, #1404
793
794 // CHECK: wls lr, r10, #1408 @ encoding: [0x4a,0xf0,0xc1,0xc2]
795 // CHECK-FP: wls lr, r10, #1408 @ encoding: [0x4a,0xf0,0xc1,0xc2]
796 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
797 wls lr, r10, #1408
798
799 // CHECK: wls lr, r10, #2358 @ encoding: [0x4a,0xf0,0x9b,0xcc]
800 // CHECK-FP: wls lr, r10, #2358 @ encoding: [0x4a,0xf0,0x9b,0xcc]
801 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
802 wls lr, r10, #2358
803
804 // CHECK: wls lr, r10, #4086 @ encoding: [0x4a,0xf0,0xfb,0xcf]
805 // CHECK-FP: wls lr, r10, #4086 @ encoding: [0x4a,0xf0,0xfb,0xcf]
806 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
807 wls lr, r10, #4086
808
809 // CHECK: wls lr, r11, #1442 @ encoding: [0x4b,0xf0,0xd1,0xca]
810 // CHECK-FP: wls lr, r11, #1442 @ encoding: [0x4b,0xf0,0xd1,0xca]
811 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
812 wls lr, r11, #1442
813
814 // CHECK: wls lr, r11, #2678 @ encoding: [0x4b,0xf0,0x3b,0xcd]
815 // CHECK-FP: wls lr, r11, #2678 @ encoding: [0x4b,0xf0,0x3b,0xcd]
816 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
817 wls lr, r11, #2678
818
819 // CHECK: wls lr, r11, #3610 @ encoding: [0x4b,0xf0,0x0d,0xcf]
820 // CHECK-FP: wls lr, r11, #3610 @ encoding: [0x4b,0xf0,0x0d,0xcf]
821 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
822 wls lr, r11, #3610
823
824 // CHECK: wls lr, r12, #206 @ encoding: [0x4c,0xf0,0x67,0xc8]
825 // CHECK-FP: wls lr, r12, #206 @ encoding: [0x4c,0xf0,0x67,0xc8]
826 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
827 wls lr, r12, #206
828
829 // CHECK: wls lr, r12, #2896 @ encoding: [0x4c,0xf0,0xa9,0xc5]
830 // CHECK-FP: wls lr, r12, #2896 @ encoding: [0x4c,0xf0,0xa9,0xc5]
831 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
832 wls lr, r12, #2896
833
834 // CHECK: wls lr, r12, #3258 @ encoding: [0x4c,0xf0,0x5d,0xce]
835 // CHECK-FP: wls lr, r12, #3258 @ encoding: [0x4c,0xf0,0x5d,0xce]
836 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
837 wls lr, r12, #3258
838
839 // CHECK: wls lr, r2, #3242 @ encoding: [0x42,0xf0,0x55,0xce]
840 // CHECK-FP: wls lr, r2, #3242 @ encoding: [0x42,0xf0,0x55,0xce]
841 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
842 wls lr, r2, #3242
843
844 // CHECK: wls lr, r2, #3832 @ encoding: [0x42,0xf0,0x7d,0xc7]
845 // CHECK-FP: wls lr, r2, #3832 @ encoding: [0x42,0xf0,0x7d,0xc7]
846 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
847 wls lr, r2, #3832
848
849 // CHECK: wls lr, r2, #872 @ encoding: [0x42,0xf0,0xb5,0xc1]
850 // CHECK-FP: wls lr, r2, #872 @ encoding: [0x42,0xf0,0xb5,0xc1]
851 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
852 wls lr, r2, #872
853
854 // CHECK: wls lr, r3, #3514 @ encoding: [0x43,0xf0,0xdd,0xce]
855 // CHECK-FP: wls lr, r3, #3514 @ encoding: [0x43,0xf0,0xdd,0xce]
856 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
857 wls lr, r3, #3514
858
859 // CHECK: wls lr, r3, #3636 @ encoding: [0x43,0xf0,0x1b,0xc7]
860 // CHECK-FP: wls lr, r3, #3636 @ encoding: [0x43,0xf0,0x1b,0xc7]
861 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
862 wls lr, r3, #3636
863
864 // CHECK: wls lr, r3, #3942 @ encoding: [0x43,0xf0,0xb3,0xcf]
865 // CHECK-FP: wls lr, r3, #3942 @ encoding: [0x43,0xf0,0xb3,0xcf]
866 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
867 wls lr, r3, #3942
868
869 // CHECK: wls lr, r3, #712 @ encoding: [0x43,0xf0,0x65,0xc1]
870 // CHECK-FP: wls lr, r3, #712 @ encoding: [0x43,0xf0,0x65,0xc1]
871 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
872 wls lr, r3, #712
873
874 // CHECK: wls lr, r4, #2146 @ encoding: [0x44,0xf0,0x31,0xcc]
875 // CHECK-FP: wls lr, r4, #2146 @ encoding: [0x44,0xf0,0x31,0xcc]
876 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
877 wls lr, r4, #2146
878
879 // CHECK: wls lr, r4, #2486 @ encoding: [0x44,0xf0,0xdb,0xcc]
880 // CHECK-FP: wls lr, r4, #2486 @ encoding: [0x44,0xf0,0xdb,0xcc]
881 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
882 wls lr, r4, #2486
883
884 // CHECK: wls lr, r5, #1906 @ encoding: [0x45,0xf0,0xb9,0xcb]
885 // CHECK-FP: wls lr, r5, #1906 @ encoding: [0x45,0xf0,0xb9,0xcb]
886 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
887 wls lr, r5, #1906
888
889 // CHECK: wls lr, r5, #3396 @ encoding: [0x45,0xf0,0xa3,0xc6]
890 // CHECK-FP: wls lr, r5, #3396 @ encoding: [0x45,0xf0,0xa3,0xc6]
891 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
892 wls lr, r5, #3396
893
894 // CHECK: wls lr, r6, #3326 @ encoding: [0x46,0xf0,0x7f,0xce]
895 // CHECK-FP: wls lr, r6, #3326 @ encoding: [0x46,0xf0,0x7f,0xce]
896 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
897 wls lr, r6, #3326
898
899 // CHECK: wls lr, r6, #416 @ encoding: [0x46,0xf0,0xd1,0xc0]
900 // CHECK-FP: wls lr, r6, #416 @ encoding: [0x46,0xf0,0xd1,0xc0]
901 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
902 wls lr, r6, #416
903
904 // CHECK: wls lr, r6, #422 @ encoding: [0x46,0xf0,0xd3,0xc8]
905 // CHECK-FP: wls lr, r6, #422 @ encoding: [0x46,0xf0,0xd3,0xc8]
906 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
907 wls lr, r6, #422
908
909 // CHECK: wls lr, r7, #3474 @ encoding: [0x47,0xf0,0xc9,0xce]
910 // CHECK-FP: wls lr, r7, #3474 @ encoding: [0x47,0xf0,0xc9,0xce]
911 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
912 wls lr, r7, #3474
913
914 // CHECK: wls lr, r7, #3640 @ encoding: [0x47,0xf0,0x1d,0xc7]
915 // CHECK-FP: wls lr, r7, #3640 @ encoding: [0x47,0xf0,0x1d,0xc7]
916 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
917 wls lr, r7, #3640
918