llvm.org GIT mirror llvm / 68fc2da
Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105745 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
5 changed file(s) with 66 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
201201 unsigned DestReg, unsigned SubIdx,
202202 const MachineInstr *Orig,
203203 const TargetRegisterInfo &TRI) const = 0;
204
205 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
206 /// two-addrss instruction inserted by two-address pass.
207 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI,
208 MachineInstr *UseMI,
209 const TargetRegisterInfo &TRI) const {
210 // Do nothing.
211 }
204212
205213 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
206214 /// MachineFunction::CloneMachineInstr(), but the target may update operands
11031103 }
11041104 }
11051105 }
1106
1106
1107 // Schedule the source copy / remat inserted to form two-address
1108 // instruction. FIXME: Does it matter the distance map may not be
1109 // accurate after it's scheduled?
1110 TII->scheduleTwoAddrSource(prior(mi), mi, *TRI);
1111
11071112 MadeChange = true;
11081113
11091114 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
6060 unsigned Opc = MI->getOpcode();
6161 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
6262 return ARMCC::AL;
63
64 int PIdx = MI->findFirstPredOperandIdx();
65 if (PIdx == -1) {
66 PredReg = 0;
67 return ARMCC::AL;
68 }
69
70 PredReg = MI->getOperand(PIdx+1).getReg();
71 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
63 return llvm::getInstrPredicate(MI, PredReg);
7264 }
7365
7466 bool
241233 // Insert a new block for consecutive predicated instructions.
242234 MachineFunction *MF = MBB->getParent();
243235 MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB->getBasicBlock());
244 MachineFunction::iterator Pos = MBB;
245 MF->insert(++Pos, NewMBB);
236 MachineFunction::iterator InsertPos = MBB;
237 MF->insert(++InsertPos, NewMBB);
246238
247239 // Move all the successors of this block to the specified block.
248240 NewMBB->transferSuccessors(MBB);
249241
250242 // Add an edge from CurMBB to NewMBB for the fall-through.
251243 MBB->addSuccessor(NewMBB);
252 NewMBB->splice(NewMBB->end(), MBB, ++MBBI, MBB->end());
244 NewMBB->splice(NewMBB->end(), MBB, ++MBBI, MBB->end());
253245 return true;
254246 }
255247
502502 Offset = (isSub) ? -Offset : Offset;
503503 return Offset == 0;
504504 }
505
506 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
507 /// two-addrss instruction inserted by two-address pass.
508 void
509 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
510 MachineInstr *UseMI,
511 const TargetRegisterInfo &TRI) const {
512 if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
513 SrcMI->getOperand(1).isKill())
514 return;
515
516 unsigned PredReg = 0;
517 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
518 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
519 return;
520
521 // Schedule the copy so it doesn't come between previous instructions
522 // and UseMI which can form an IT block.
523 unsigned SrcReg = SrcMI->getOperand(1).getReg();
524 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
525 MachineBasicBlock *MBB = UseMI->getParent();
526 MachineBasicBlock::iterator MBBI = SrcMI;
527 unsigned NumInsts = 0;
528 while (--MBBI != MBB->begin()) {
529 if (MBBI->isDebugValue())
530 continue;
531
532 MachineInstr *NMI = &*MBBI;
533 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
534 if (!(NCC == CC || NCC == OCC) ||
535 NMI->modifiesRegister(SrcReg, &TRI) ||
536 NMI->definesRegister(ARM::CPSR))
537 break;
538 if (++NumInsts == 4)
539 // Too many in a row!
540 return;
541 }
542
543 if (NumInsts) {
544 MBB->remove(SrcMI);
545 MBB->insert(++MBBI, SrcMI);
546 }
547 }
4949 const TargetRegisterClass *RC,
5050 const TargetRegisterInfo *TRI) const;
5151
52 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
53 /// two-addrss instruction inserted by two-address pass.
54 void scheduleTwoAddrSource(MachineInstr *SrcMI, MachineInstr *UseMI,
55 const TargetRegisterInfo &TRI) const;
56
5257 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
5358 /// such, whenever a client has an instance of instruction info, it should
5459 /// always be able to get register info as well (through this method).